* [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
@ 2019-07-26 17:49 Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
` (68 more replies)
0 siblings, 69 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
This unifies the implementation of the actual instructions
for a32, t32, and t16. In order to make this happen, we
need several preliminary cleanups. Most importantly to how
we handle the architectural representation of PC.
I attempt to convert single groups of instructions at once,
as they are grouped in the sections of the encoding sections
of the manual.
This has been tested by running the debian 9 armhf installer,
which does a far amount of switching between arm and thumb modes.
I've also run Peter's ARM TFM image, and all of the existing
RISU tests that we have. (Our RISU test cases are nowhere near
complete for 32-bit mode, but it did find 3 bugs, so not useless.)
What's left is converting NEON and iwmmxt, then we could start
merging some of the decoders and tidying the top-level interface
further.
We will need to convert NEON in order to have a good chance at
finishing the ARMv8.2-FHP extension.
r~
Richard Henderson (67):
decodetree: Allow !function with no input bits
target/arm: Remove offset argument to gen_exception_insn
target/arm: Remove offset argument to gen_exception_bkpt_insn
target/arm: Remove offset argument to gen_exception_internal_insn
target/arm: Use the saved value of the insn address
target/arm: Introduce pc_read
target/arm: Introduce add_reg_for_lit
target/arm: Use store_reg_from_load in thumb2 code
target/arm: Fold a pc load into load_reg
target/arm: Move test for AL into arm_skip_unless
target/arm: Add stubs for aa32 decodetree
target/arm: Introduce gen_illegal_op
target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
target/arm: Convert multiply and multiply accumulate
target/arm: Convert Saturating addition and subtraction
target/arm: Convert Halfword multiply and multiply accumulate
target/arm: Convert MSR (immediate) and hints
target/arm: Convert MRS/MSR (banked, register)
target/arm: Convert Cyclic Redundancy Check
target/arm: Convert the rest of A32 Miscelaneous instructions
target/arm: Convert T32 ADDW/SUBW
target/arm: Convert load/store (register, immediate, literal)
target/arm: Convert Synchronization primitives
target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
target/arm: Convert Parallel addition and subtraction
target/arm: Convert Packing, unpacking, saturation, and reversal
target/arm: Convert Signed multiply, signed and unsigned divide
target/arm: Convert MOVW, MOVT
target/arm: Convert LDM, STM
target/arm: Convert B, BL, BLX (immediate)
target/arm: Convert SVC
target/arm: Convert RFE and SRS
target/arm: Convert Clear-Exclusive, Barriers
target/arm: Convert CPS (privileged)
target/arm: Convert SETEND
target/arm: Convert PLI, PLD, PLDW
target/arm: Convert Unallocated memory hint
target/arm: Convert Table Branch
target/arm: Convert SG
target/arm: Convert TT
target/arm: Simplify disas_thumb2_insn
target/arm: Simplify disas_arm_insn
target/arm: Add skeleton for T16 decodetree
target/arm: Convert T16 data-processing (two low regs)
target/arm: Convert T16 load/store (register offset)
target/arm: Convert T16 load/store (immediate offset)
target/arm: Convert T16 add pc/sp (immediate)
target/arm: Convert T16 load/store multiple
target/arm: Convert T16 add/sub (3 low, 2 low and imm)
target/arm: Convert T16 one low register and immediate
target/arm: Convert T16 branch and exchange
target/arm: Convert T16 add, compare, move (two high registers)
target/arm: Convert T16 adjust sp (immediate)
target/arm: Convert T16, extract
target/arm: Convert T16, Change processor state
target/arm: Convert T16, Reverse bytes
target/arm: Convert T16, nop hints
target/arm: Convert T16, push and pop
target/arm: Convert T16, Conditional branches, Supervisor call
target/arm: Convert T16, Miscellaneous 16-bit instructions
target/arm: Convert T16, shift immediate
target/arm: Convert T16, load (literal)
target/arm: Convert T16, Unconditional branch
target/arm: Convert T16, long branches
target/arm: Clean up disas_thumb_insn
target/arm: Move singlestep check from gen_jmp to gen_goto_tb
target/arm: Merge gen_bx_im into trans_BLX_i
target/arm/helper.h | 1 -
target/arm/translate.h | 10 +
target/arm/op_helper.c | 15 -
target/arm/translate-vfp.inc.c | 41 +-
target/arm/translate.c | 7142 ++++++++++++-----------------
scripts/decodetree.py | 5 +-
target/arm/Makefile.objs | 24 +
target/arm/a32-uncond.decode | 74 +
target/arm/a32.decode | 534 +++
target/arm/t16.decode | 279 ++
target/arm/t32.decode | 629 +++
tests/decode/succ_function.decode | 2 +
12 files changed, 4559 insertions(+), 4197 deletions(-)
create mode 100644 target/arm/a32-uncond.decode
create mode 100644 target/arm/a32.decode
create mode 100644 target/arm/t16.decode
create mode 100644 target/arm/t32.decode
create mode 100644 tests/decode/succ_function.decode
--
2.17.1
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 13:43 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
` (67 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
With this, we can have the function return a value from the DisasContext.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
scripts/decodetree.py | 5 ++++-
tests/decode/succ_function.decode | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
create mode 100644 tests/decode/succ_function.decode
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index d7a59d63ac..4259d87a95 100755
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -195,7 +195,10 @@ class MultiField:
"""Class representing a compound instruction field"""
def __init__(self, subs, mask):
self.subs = subs
- self.sign = subs[0].sign
+ if len(subs):
+ self.sign = subs[0].sign
+ else:
+ self.sign = 0
self.mask = mask
def __str__(self):
diff --git a/tests/decode/succ_function.decode b/tests/decode/succ_function.decode
new file mode 100644
index 0000000000..632a9de252
--- /dev/null
+++ b/tests/decode/succ_function.decode
@@ -0,0 +1,2 @@
+%foo !function=foo
+foo 00000000000000000000000000000000 %foo
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 13:48 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
` (66 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
The address of the current insn is still available in s->base.pc_next.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 6 +++---
target/arm/translate.c | 32 ++++++++++++++++----------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 092eb5ec53..e7389bc057 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -96,10 +96,10 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
{
if (s->fp_excp_el) {
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(),
s->fp_excp_el);
} else {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_fp_access_trap(1, 0xe, false),
s->fp_excp_el);
}
@@ -108,7 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7853462b21..33f78296eb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1247,11 +1247,11 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
s->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
- int syn, uint32_t target_el)
+static void gen_exception_insn(DisasContext *s, int excp, int syn,
+ uint32_t target_el)
{
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - offset);
+ gen_set_pc_im(s, s->base.pc_next);
gen_exception(excp, syn, target_el);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1298,7 +1298,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
return;
}
- gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
@@ -3175,7 +3175,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
undef:
/* If we get here then some access check did not pass */
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), exc_target);
return false;
}
@@ -3569,7 +3569,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -4840,7 +4840,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -6968,7 +6968,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
}
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -7091,7 +7091,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
off_rm = vfp_reg_offset(0, rm);
}
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -7584,7 +7584,7 @@ static void gen_srs(DisasContext *s,
* For the UNPREDICTABLE cases we choose to UNDEF.
*/
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), 3);
return;
}
@@ -7620,7 +7620,7 @@ static void gen_srs(DisasContext *s,
}
if (undef) {
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return;
}
@@ -7711,7 +7711,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
* UsageFault exception.
*/
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
return;
}
@@ -9254,7 +9254,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
break;
default:
illegal_op:
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
break;
}
@@ -10288,7 +10288,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
/* All other insns: NOCP */
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));
break;
}
@@ -10972,7 +10972,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
return;
illegal_op:
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
@@ -11809,7 +11809,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
return;
illegal_op:
undef:
- gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 13:50 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
` (65 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
The address of the current insn is still available in s->base.pc_next.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 33f78296eb..19b126d4f3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1256,12 +1256,12 @@ static void gen_exception_insn(DisasContext *s, int excp, int syn,
s->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
{
TCGv_i32 tcg_syn;
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - offset);
+ gen_set_pc_im(s, s->base.pc_next);
tcg_syn = tcg_const_i32(syn);
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
tcg_temp_free_i32(tcg_syn);
@@ -8139,7 +8139,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 1:
/* bkpt */
ARCH(5);
- gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
break;
case 2:
/* Hypervisor call (v7) */
@@ -11611,7 +11611,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
int imm8 = extract32(insn, 0, 8);
ARCH(5);
- gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
break;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (2 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 13:52 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
` (64 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
The actual argument is 0 for all callers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 19b126d4f3..0848fb933a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1239,10 +1239,10 @@ static inline void gen_smc(DisasContext *s)
s->base.is_jmp = DISAS_SMC;
}
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
+static void gen_exception_internal_insn(DisasContext *s, int excp)
{
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - offset);
+ gen_set_pc_im(s, s->pc);
gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1294,7 +1294,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
s->current_el != 0 &&
#endif
(imm == (s->thumb ? 0x3c : 0xf000))) {
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
return;
}
@@ -11984,7 +11984,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
/* End the TB early; it's likely not going to be executed */
dc->base.is_jmp = DISAS_TOO_MANY;
} else {
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
+ gen_exception_internal_insn(dc, EXCP_DEBUG);
/* The address covered by the breakpoint must be
included in [tb->pc, tb->pc + tb->size) in order
to for it to be properly cleared -- thus we
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (3 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 13:54 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
` (63 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
The address of the current insn is still available in s->base.pc_next,
and need not be recomputed from s->pc - 4.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0848fb933a..595385e1b1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1212,7 +1212,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
* as an undefined insn by runtime configuration (ie before
* the insn really executes).
*/
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
gen_helper_pre_hvc(cpu_env);
/* Otherwise we will treat this as a real exception which
* happens after execution of the insn. (The distinction matters
@@ -1231,7 +1231,7 @@ static inline void gen_smc(DisasContext *s)
*/
TCGv_i32 tmp;
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
tmp = tcg_const_i32(syn_aa32_smc());
gen_helper_pre_smc(cpu_env, tmp);
tcg_temp_free_i32(tmp);
@@ -3190,7 +3190,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
/* Sync state because msr_banked() can raise exceptions */
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
tcg_reg = load_reg(s, rn);
tcg_tgtmode = tcg_const_i32(tgtmode);
tcg_regno = tcg_const_i32(regno);
@@ -3212,7 +3212,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
/* Sync state because mrs_banked() can raise exceptions */
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
tcg_reg = tcg_temp_new_i32();
tcg_tgtmode = tcg_const_i32(tgtmode);
tcg_regno = tcg_const_i32(regno);
@@ -7219,7 +7219,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
tcg_isread = tcg_const_i32(isread);
@@ -7629,7 +7629,7 @@ static void gen_srs(DisasContext *s,
tmp = tcg_const_i32(mode);
/* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - 4);
+ gen_set_pc_im(s, s->base.pc_next);
gen_helper_get_r13_banked(addr, cpu_env, tmp);
tcg_temp_free_i32(tmp);
switch (amode) {
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (4 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:05 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
` (62 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
We currently have 3 different ways of computing the architectural
value of "PC" as seen in the ARM ARM.
The value of s->pc has been incremented past the current insn,
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
for t16, PC = s->pc + 2. These differing computations make it
impossible at present to unify the various code paths.
Let s->pc_read hold the architectural value of PC for all cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 10 ++++++++
target/arm/translate.c | 53 ++++++++++++++++++------------------------
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index a20f6e2056..2dfdd8ca66 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -9,7 +9,17 @@ typedef struct DisasContext {
DisasContextBase base;
const ARMISARegisters *isar;
+ /*
+ * Summary of the various values for "PC":
+ * base.pc_next -- the start of the current insn
+ * pc -- the start of the next insn
+ * pc_read -- the value for "PC" in the ARM ARM;
+ * in arm mode, the current insn + 8;
+ * in thumb mode, the current insn + 4;
+ * in aa64 mode, unused.
+ */
target_ulong pc;
+ target_ulong pc_read;
target_ulong page_start;
uint32_t insn;
/* Nonzero if this instruction has been conditionally skipped. */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 595385e1b1..a48e9a90f8 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -200,13 +200,7 @@ static inline void store_cpu_offset(TCGv_i32 var, int offset)
static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
{
if (reg == 15) {
- uint32_t addr;
- /* normally, since we updated PC, we need only to add one insn */
- if (s->thumb)
- addr = (long)s->pc + 2;
- else
- addr = (long)s->pc + 4;
- tcg_gen_movi_i32(var, addr);
+ tcg_gen_movi_i32(var, s->pc_read);
} else {
tcg_gen_mov_i32(var, cpu_R[reg]);
}
@@ -7868,16 +7862,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* branch link and change to thumb (blx <offset>) */
int32_t offset;
- val = (uint32_t)s->pc;
tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
+ tcg_gen_movi_i32(tmp, s->pc);
store_reg(s, 14, tmp);
/* Sign-extend the 24-bit offset */
offset = (((int32_t)insn) << 8) >> 8;
+ val = s->pc_read;
/* offset * 4 + bit24 * 2 + (thumb bit) */
val += (offset << 2) | ((insn >> 23) & 2) | 1;
- /* pipeline offset */
- val += 4;
/* protected by ARCH(5); above, near the start of uncond block */
gen_bx_im(s, val);
return;
@@ -9154,9 +9146,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* store */
if (i == 15) {
/* special case: r15 = PC + 8 */
- val = (long)s->pc + 4;
tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
+ tcg_gen_movi_i32(tmp, s->pc_read);
} else if (user) {
tmp = tcg_temp_new_i32();
tmp2 = tcg_const_i32(i);
@@ -9222,14 +9213,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
int32_t offset;
/* branch (and link) */
- val = (int32_t)s->pc;
if (insn & (1 << 24)) {
tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
+ tcg_gen_movi_i32(tmp, s->pc);
store_reg(s, 14, tmp);
}
offset = sextract32(insn << 2, 0, 26);
- val += offset + 4;
+ val = s->pc_read + offset;
gen_jmp(s, val);
}
break;
@@ -9484,7 +9474,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~3);
+ tcg_gen_movi_i32(addr, s->pc_read & ~3);
} else {
addr = load_reg(s, rn);
}
@@ -9590,7 +9580,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Table Branch. */
if (rn == 15) {
addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc);
+ tcg_gen_movi_i32(addr, s->pc_read);
} else {
addr = load_reg(s, rn);
}
@@ -9609,7 +9599,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
tcg_temp_free_i32(addr);
tcg_gen_shli_i32(tmp, tmp, 1);
- tcg_gen_addi_i32(tmp, tmp, s->pc);
+ tcg_gen_addi_i32(tmp, tmp, s->pc_read);
store_reg(s, 15, tmp);
} else {
bool is_lasr = false;
@@ -10342,7 +10332,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
}
- offset += s->pc;
+ offset += s->pc_read;
if (insn & (1 << 12)) {
/* b/bl */
gen_jmp(s, offset);
@@ -10583,7 +10573,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
offset |= (insn & (1 << 11)) << 8;
/* jump to the offset */
- gen_jmp(s, s->pc + offset);
+ gen_jmp(s, s->pc_read + offset);
}
} else {
/*
@@ -10694,7 +10684,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
} else {
/* Add/sub 12-bit immediate. */
if (rn == 15) {
- offset = s->pc & ~(uint32_t)3;
+ offset = s->pc_read & ~(uint32_t)3;
if (insn & (1 << 23))
offset -= imm;
else
@@ -10830,8 +10820,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
if (rn == 15) {
addr = tcg_temp_new_i32();
/* PC relative. */
- /* s->pc has already been incremented by 4. */
- imm = s->pc & 0xfffffffc;
+ imm = s->pc_read & 0xfffffffc;
if (insn & (1 << 23))
imm += insn & 0xfff;
else
@@ -11077,7 +11066,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
if (insn & (1 << 11)) {
rd = (insn >> 8) & 7;
/* load pc-relative. Bit 1 of PC is ignored. */
- val = s->pc + 2 + ((insn & 0xff) * 4);
+ val = s->pc_read + ((insn & 0xff) * 4);
val &= ~(uint32_t)2;
addr = tcg_temp_new_i32();
tcg_gen_movi_i32(addr, val);
@@ -11464,7 +11453,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
} else {
/* PC. bit 1 is ignored. */
tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
+ tcg_gen_movi_i32(tmp, s->pc_read & ~(uint32_t)2);
}
val = (insn & 0xff) * 4;
tcg_gen_addi_i32(tmp, tmp, val);
@@ -11584,7 +11573,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
tcg_temp_free_i32(tmp);
offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
- val = (uint32_t)s->pc + 2;
+ val = s->pc_read;
val += offset;
gen_jmp(s, val);
break;
@@ -11750,7 +11739,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
arm_skip_unless(s, cond);
/* jump to the offset */
- val = (uint32_t)s->pc + 2;
+ val = s->pc_read;
offset = ((int32_t)insn << 24) >> 24;
val += offset << 1;
gen_jmp(s, val);
@@ -11776,9 +11765,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
break;
}
/* unconditional branch */
- val = (uint32_t)s->pc;
+ val = s->pc_read;
offset = ((int32_t)insn << 21) >> 21;
- val += (offset << 1) + 2;
+ val += offset << 1;
gen_jmp(s, val);
break;
@@ -11802,7 +11791,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
uint32_t uoffset = ((int32_t)insn << 21) >> 9;
- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
+ tcg_gen_movi_i32(cpu_R[14], s->pc_read + uoffset);
}
break;
}
@@ -12055,6 +12044,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
dc->insn = insn;
+ dc->pc_read = dc->pc + 8;
dc->pc += 4;
disas_arm_insn(dc, insn);
@@ -12123,6 +12113,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
is_16bit = thumb_insn_is_16bit(dc, insn);
+ dc->pc_read = dc->pc + 4;
dc->pc += 2;
if (!is_16bit) {
uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (5 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:15 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
` (61 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Used only on the thumb side so far, but will be more obvious
once we start unifying the implementation of A32+T32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 34 +------
target/arm/translate.c | 163 +++++++++++++++------------------
2 files changed, 76 insertions(+), 121 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e7389bc057..4066b2febf 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -941,14 +941,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
offset = -offset;
}
- if (s->thumb && a->rn == 15) {
- /* This is actually UNPREDICTABLE */
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~2);
- } else {
- addr = load_reg(s, a->rn);
- }
- tcg_gen_addi_i32(addr, addr, offset);
+ addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
@@ -983,14 +976,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
offset = -offset;
}
- if (s->thumb && a->rn == 15) {
- /* This is actually UNPREDICTABLE */
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~2);
- } else {
- addr = load_reg(s, a->rn);
- }
- tcg_gen_addi_i32(addr, addr, offset);
+ addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i64();
if (a->l) {
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
@@ -1029,13 +1015,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
return true;
}
- if (s->thumb && a->rn == 15) {
- /* This is actually UNPREDICTABLE */
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~2);
- } else {
- addr = load_reg(s, a->rn);
- }
+ addr = add_reg_for_lit(s, a->rn, 0);
if (a->p) {
/* pre-decrement */
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
@@ -1112,13 +1092,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
return true;
}
- if (s->thumb && a->rn == 15) {
- /* This is actually UNPREDICTABLE */
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~2);
- } else {
- addr = load_reg(s, a->rn);
- }
+ addr = add_reg_for_lit(s, a->rn, 0);
if (a->p) {
/* pre-decrement */
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a48e9a90f8..5e2dd8bb16 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -214,6 +214,23 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
return tmp;
}
+/*
+ * Create a new temp, incremented by OFS, except PC is aligned but not
+ * incremented for thumb. This is used for load/store for which use of
+ * PC implies (literal), or ADD that implies ADR.
+ */
+static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ if (reg == 15) {
+ tcg_gen_movi_i32(tmp, (s->pc_read & ~3) + ofs);
+ } else {
+ tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
+ }
+ return tmp;
+}
+
/* Set a CPU register. The source must be a temporary and will be
marked as dead. */
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
@@ -9468,16 +9485,12 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
*/
bool wback = extract32(insn, 21, 1);
- if (rn == 15) {
- if (insn & (1 << 21)) {
- /* UNPREDICTABLE */
- goto illegal_op;
- }
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc_read & ~3);
- } else {
- addr = load_reg(s, rn);
+ if (rn == 15 && (insn & (1 << 21))) {
+ /* UNPREDICTABLE */
+ goto illegal_op;
}
+
+ addr = add_reg_for_lit(s, rn, 0);
offset = (insn & 0xff) * 4;
if ((insn & (1 << 23)) == 0) {
offset = -offset;
@@ -10683,27 +10696,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
store_reg(s, rd, tmp);
} else {
/* Add/sub 12-bit immediate. */
- if (rn == 15) {
- offset = s->pc_read & ~(uint32_t)3;
- if (insn & (1 << 23))
- offset -= imm;
- else
- offset += imm;
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, offset);
- store_reg(s, rd, tmp);
+ if (insn & (1 << 23)) {
+ imm = -imm;
+ }
+ tmp = add_reg_for_lit(s, rn, imm);
+ if (rn == 13 && rd == 13) {
+ /* ADD SP, SP, imm or SUB SP, SP, imm */
+ store_sp_checked(s, tmp);
} else {
- tmp = load_reg(s, rn);
- if (insn & (1 << 23))
- tcg_gen_subi_i32(tmp, tmp, imm);
- else
- tcg_gen_addi_i32(tmp, tmp, imm);
- if (rn == 13 && rd == 13) {
- /* ADD SP, SP, imm or SUB SP, SP, imm */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
+ store_reg(s, rd, tmp);
}
}
}
@@ -10817,60 +10818,51 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
memidx = get_mem_index(s);
- if (rn == 15) {
- addr = tcg_temp_new_i32();
- /* PC relative. */
- imm = s->pc_read & 0xfffffffc;
- if (insn & (1 << 23))
- imm += insn & 0xfff;
- else
- imm -= insn & 0xfff;
- tcg_gen_movi_i32(addr, imm);
+ imm = insn & 0xfff;
+ if (insn & (1 << 23)) {
+ /* PC relative or Positive offset. */
+ addr = add_reg_for_lit(s, rn, imm);
+ } else if (rn == 15) {
+ /* PC relative with negative offset. */
+ addr = add_reg_for_lit(s, rn, -imm);
} else {
addr = load_reg(s, rn);
- if (insn & (1 << 23)) {
- /* Positive offset. */
- imm = insn & 0xfff;
- tcg_gen_addi_i32(addr, addr, imm);
- } else {
- imm = insn & 0xff;
- switch ((insn >> 8) & 0xf) {
- case 0x0: /* Shifted Register. */
- shift = (insn >> 4) & 0xf;
- if (shift > 3) {
- tcg_temp_free_i32(addr);
- goto illegal_op;
- }
- tmp = load_reg(s, rm);
- if (shift)
- tcg_gen_shli_i32(tmp, tmp, shift);
- tcg_gen_add_i32(addr, addr, tmp);
- tcg_temp_free_i32(tmp);
- break;
- case 0xc: /* Negative offset. */
- tcg_gen_addi_i32(addr, addr, -imm);
- break;
- case 0xe: /* User privilege. */
- tcg_gen_addi_i32(addr, addr, imm);
- memidx = get_a32_user_mem_index(s);
- break;
- case 0x9: /* Post-decrement. */
- imm = -imm;
- /* Fall through. */
- case 0xb: /* Post-increment. */
- postinc = 1;
- writeback = 1;
- break;
- case 0xd: /* Pre-decrement. */
- imm = -imm;
- /* Fall through. */
- case 0xf: /* Pre-increment. */
- writeback = 1;
- break;
- default:
+ imm = insn & 0xff;
+ switch ((insn >> 8) & 0xf) {
+ case 0x0: /* Shifted Register. */
+ shift = (insn >> 4) & 0xf;
+ if (shift > 3) {
tcg_temp_free_i32(addr);
goto illegal_op;
}
+ tmp = load_reg(s, rm);
+ tcg_gen_shli_i32(tmp, tmp, shift);
+ tcg_gen_add_i32(addr, addr, tmp);
+ tcg_temp_free_i32(tmp);
+ break;
+ case 0xc: /* Negative offset. */
+ tcg_gen_addi_i32(addr, addr, -imm);
+ break;
+ case 0xe: /* User privilege. */
+ tcg_gen_addi_i32(addr, addr, imm);
+ memidx = get_a32_user_mem_index(s);
+ break;
+ case 0x9: /* Post-decrement. */
+ imm = -imm;
+ /* Fall through. */
+ case 0xb: /* Post-increment. */
+ postinc = 1;
+ writeback = 1;
+ break;
+ case 0xd: /* Pre-decrement. */
+ imm = -imm;
+ /* Fall through. */
+ case 0xf: /* Pre-increment. */
+ writeback = 1;
+ break;
+ default:
+ tcg_temp_free_i32(addr);
+ goto illegal_op;
}
}
@@ -11066,10 +11058,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
if (insn & (1 << 11)) {
rd = (insn >> 8) & 7;
/* load pc-relative. Bit 1 of PC is ignored. */
- val = s->pc_read + ((insn & 0xff) * 4);
- val &= ~(uint32_t)2;
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, val);
+ addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
tmp = tcg_temp_new_i32();
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
rd | ISSIs16Bit);
@@ -11447,16 +11436,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
* - Add PC/SP (immediate)
*/
rd = (insn >> 8) & 7;
- if (insn & (1 << 11)) {
- /* SP */
- tmp = load_reg(s, 13);
- } else {
- /* PC. bit 1 is ignored. */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, s->pc_read & ~(uint32_t)2);
- }
val = (insn & 0xff) * 4;
- tcg_gen_addi_i32(tmp, tmp, val);
+ tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
store_reg(s, rd, tmp);
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (6 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:26 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
` (60 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
There is an extra always-true ARMv5 test, but this will
become more obvious once we start unifying the
implementation of A32+T32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5e2dd8bb16..e316eeb312 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9773,13 +9773,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Load. */
tmp = tcg_temp_new_i32();
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- if (i == 15) {
- gen_bx_excret(s, tmp);
- } else if (i == rn) {
+ if (i == rn) {
loaded_var = tmp;
loaded_base = 1;
} else {
- store_reg(s, i, tmp);
+ store_reg_from_load(s, i, tmp);
}
} else {
/* Store. */
@@ -10914,11 +10912,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(addr);
goto illegal_op;
}
- if (rs == 15) {
- gen_bx_excret(s, tmp);
- } else {
- store_reg(s, rs, tmp);
- }
+ store_reg_from_load(s, rs, tmp);
} else {
/* Store. */
tmp = load_reg(s, rs);
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (7 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:27 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
` (59 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e316eeb312..53c46fcdc4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9161,11 +9161,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
} else {
/* store */
- if (i == 15) {
- /* special case: r15 = PC + 8 */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, s->pc_read);
- } else if (user) {
+ if (user && i != 15) {
tmp = tcg_temp_new_i32();
tmp2 = tcg_const_i32(i);
gen_helper_get_user_reg(tmp, cpu_env, tmp2);
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (8 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:32 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
` (58 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
We will shortly be calling this function much more often.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 53c46fcdc4..36419025db 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7705,8 +7705,14 @@ static void arm_gen_condlabel(DisasContext *s)
/* Skip this instruction if the ARM condition is false */
static void arm_skip_unless(DisasContext *s, uint32_t cond)
{
- arm_gen_condlabel(s);
- arm_gen_test_cc(cond ^ 1, s->condlabel);
+ /*
+ * Conditionally skip the insn. Note that both 0xe and 0xf mean
+ * "always"; 0xf is not "never".
+ */
+ if (cond < 0xe) {
+ arm_gen_condlabel(s);
+ arm_gen_test_cc(cond ^ 1, s->condlabel);
+ }
}
static void disas_arm_insn(DisasContext *s, unsigned int insn)
@@ -7944,11 +7950,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
goto illegal_op;
}
- if (cond != 0xe) {
- /* if not always execute, we generate a conditional jump to
- next instruction */
- arm_skip_unless(s, cond);
- }
+
+ arm_skip_unless(s, cond);
+
if ((insn & 0x0f900000) == 0x03000000) {
if ((insn & (1 << 21)) == 0) {
ARCH(6T2);
@@ -12095,15 +12099,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
dc->insn = insn;
if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
- uint32_t cond = dc->condexec_cond;
-
- /*
- * Conditionally skip the insn. Note that both 0xe and 0xf mean
- * "always"; 0xf is not "never".
- */
- if (cond < 0x0e) {
- arm_skip_unless(dc, cond);
- }
+ arm_skip_unless(dc, dc->condexec_cond);
}
if (is_16bit) {
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (9 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:42 ` Peter Maydell
` (2 more replies)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
` (57 subsequent siblings)
68 siblings, 3 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Add the infrastructure that will become the new decoder.
No instructions adjusted so far.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++-
target/arm/Makefile.objs | 18 +++++++++++++++
target/arm/a32-uncond.decode | 23 ++++++++++++++++++
target/arm/a32.decode | 23 ++++++++++++++++++
target/arm/t32.decode | 20 ++++++++++++++++
5 files changed, 128 insertions(+), 1 deletion(-)
create mode 100644 target/arm/a32-uncond.decode
create mode 100644 target/arm/a32.decode
create mode 100644 target/arm/t32.decode
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 36419025db..4738b91957 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7715,6 +7715,33 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
}
}
+/*
+ * Include the generated decoders.
+ * Note that the T32 decoder reuses some of the trans_* functions
+ * initially declared by the A32 decoder, which results in duplicate
+ * declaration warnings. Suppress them.
+ */
+
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif
+
+#include "decode-a32.inc.c"
+#include "decode-a32-uncond.inc.c"
+#include "decode-t32.inc.c"
+
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif
+
+/*
+ * Legacy decoder.
+ */
+
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
@@ -7733,7 +7760,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
return;
}
cond = insn >> 28;
- if (cond == 0xf){
+
+ if (cond == 0xf) {
/* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
* choose to UNDEF. In ARMv5 and above the space is used
* for miscellaneous unconditional instructions.
@@ -7741,6 +7769,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5);
/* Unconditional instructions. */
+ if (disas_a32_uncond(s, insn)) {
+ return;
+ }
+ /* fall back to legacy decoder */
+
if (((insn >> 25) & 7) == 1) {
/* NEON Data processing. */
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -7953,6 +7986,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
arm_skip_unless(s, cond);
+ if (disas_a32(s, insn)) {
+ return;
+ }
+ /* fall back to legacy decoder */
+
if ((insn & 0x0f900000) == 0x03000000) {
if ((insn & (1 << 21)) == 0) {
ARCH(6T2);
@@ -9440,6 +9478,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
ARCH(6T2);
}
+ if (disas_t32(s, insn)) {
+ return;
+ }
+ /* fall back to legacy decoder */
+
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 5cafc1eb6c..7806b4dac0 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D
$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
+target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
+ $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
+ "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
+ $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
+ "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
+ $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
+ "GEN", $(TARGET_DIR)$@)
+
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
target/arm/translate.o: target/arm/decode-vfp.inc.c
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
+target/arm/translate.o: target/arm/decode-a32.inc.c
+target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
+target/arm/translate.o: target/arm/decode-t32.inc.c
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
new file mode 100644
index 0000000000..8dee26d3b6
--- /dev/null
+++ b/target/arm/a32-uncond.decode
@@ -0,0 +1,23 @@
+# A32 unconditional instructions
+#
+# Copyright (c) 2019 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+# All insns that have 0xf in insn[31:28] are decoded here.
+# All of those that have a COND field in insn[31:28] are in a32.decode
+#
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
new file mode 100644
index 0000000000..2d84a02861
--- /dev/null
+++ b/target/arm/a32.decode
@@ -0,0 +1,23 @@
+# A32 conditional instructions
+#
+# Copyright (c) 2019 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+# All of the insn that have a COND field in insn[31:28] are here.
+# All insns that have 0xf in insn[31:28] are in a32u.decode.
+#
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
new file mode 100644
index 0000000000..ac01fb6958
--- /dev/null
+++ b/target/arm/t32.decode
@@ -0,0 +1,20 @@
+# Thumb2 instructions
+#
+# Copyright (c) 2019 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (10 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 14:44 ` Peter Maydell
2019-08-06 21:43 ` Philippe Mathieu-Daudé
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
` (56 subsequent siblings)
68 siblings, 2 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Unify the code sequence for generating an illegal opcode exception.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 3 +--
target/arm/translate.c | 21 +++++++++++----------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 4066b2febf..1b08930649 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4738b91957..0f21ee9ce7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1279,6 +1279,12 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
s->base.is_jmp = DISAS_NORETURN;
}
+static void gen_illegal_op(DisasContext *s)
+{
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
+ default_exception_el(s));
+}
+
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@@ -1309,8 +1315,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
return;
}
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
@@ -7631,8 +7636,7 @@ static void gen_srs(DisasContext *s,
}
if (undef) {
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
return;
}
@@ -9299,8 +9303,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
break;
default:
illegal_op:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
break;
}
}
@@ -10990,8 +10993,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
return;
illegal_op:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@@ -11816,8 +11818,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
return;
illegal_op:
undef:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (11 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-29 15:25 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
` (55 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Do these all in one lump because these are all logically intertwined.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 747 ++++++++++++++++++++---------------------
target/arm/a32.decode | 84 +++++
target/arm/t32.decode | 91 +++++
3 files changed, 536 insertions(+), 386 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0f21ee9ce7..ee7d53dfa5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -480,12 +480,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
tcg_temp_free_i32(t1);
}
-/* Set CF to the top bit of var. */
-static void gen_set_CF_bit31(TCGv_i32 var)
-{
- tcg_gen_shri_i32(cpu_CF, var, 31);
-}
-
/* Set N and Z flags from var. */
static inline void gen_logic_CC(TCGv_i32 var)
{
@@ -905,25 +899,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label)
arm_free_cc(&cmp);
}
-static const uint8_t table_logic_cc[16] = {
- 1, /* and */
- 1, /* xor */
- 0, /* sub */
- 0, /* rsb */
- 0, /* add */
- 0, /* adc */
- 0, /* sbc */
- 0, /* rsc */
- 1, /* andl */
- 1, /* xorl */
- 0, /* cmp */
- 0, /* cmn */
- 1, /* orr */
- 1, /* mov */
- 1, /* bic */
- 1, /* mvn */
-};
-
static inline void gen_set_condexec(DisasContext *s)
{
if (s->condexec_mask) {
@@ -7719,6 +7694,49 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
}
}
+/*
+ * Constant expanders for the decoders.
+ */
+
+static int times_2(DisasContext *s, int x)
+{
+ return x * 2;
+}
+
+/* Return only the rotation part of T32ExpandImm. */
+static int t32_expandimm_rot(DisasContext *s, int x)
+{
+ return x & 0xc00 ? extract32(x, 7, 5) : 0;
+}
+
+/* Return the unrotated immediate from T32ExpandImm. */
+static int t32_expandimm_imm(DisasContext *s, int x)
+{
+ int imm = extract32(x, 0, 8);
+
+ switch (extract32(x, 8, 4)) {
+ case 0: /* XY */
+ /* Nothing to do. */
+ break;
+ case 1: /* 00XY00XY */
+ imm |= imm << 16;
+ break;
+ case 2: /* XY00XY00 */
+ imm |= imm << 16;
+ imm <<= 8;
+ break;
+ case 3: /* XYXYXYXY */
+ imm |= imm << 8;
+ imm |= imm << 16;
+ break;
+ default:
+ /* Rotated constant. */
+ imm |= 0x80;
+ break;
+ }
+ return imm;
+}
+
/*
* Include the generated decoders.
* Note that the T32 decoder reuses some of the trans_* functions
@@ -7742,6 +7760,314 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
# pragma GCC diagnostic pop
#endif
+/* Helpers to swap operands for reverse-subtract. */
+static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_sub_i32(dst, b, a);
+}
+
+static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_sub_CC(dst, b, a);
+}
+
+static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_sub_carry(dest, b, a);
+}
+
+static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_sbc_CC(dest, b, a);
+}
+
+/*
+ * Helper for the data processing routines.
+ * After the computation store the results back.
+ * This may be suppressed altogether (STREG_NONE), require a runtime
+ * check against the stack limits (STREG_SP_CHECK), or generate an
+ * exception return. Oh, or store into a register.
+ */
+typedef enum {
+ STREG_NORMAL,
+ STREG_NONE,
+ STREG_SP_CHECK,
+ STREG_EXC_RET,
+} StoreRegKind;
+
+static bool store_reg_flags(DisasContext *s, int rd,
+ TCGv_i32 val, StoreRegKind kind)
+{
+ switch (kind) {
+ case STREG_NORMAL:
+ break;
+ case STREG_NONE:
+ tcg_temp_free_i32(val);
+ return true;
+ case STREG_SP_CHECK:
+ if (rd == 13) {
+ store_sp_checked(s, val);
+ return true;
+ }
+ break;
+ case STREG_EXC_RET:
+ gen_exception_return(s, val);
+ return true;
+ default:
+ g_assert_not_reached();
+ }
+ /* ALUWritePC: Interworking only from a32 mode. */
+ if (s->thumb) {
+ store_reg(s, rd, val);
+ } else {
+ store_reg_bx(s, rd, val);
+ }
+ return true;
+}
+
+/*
+ * Data Processing (register)
+ *
+ * Operate, with set flags, one register source,
+ * one immediate shifted register source, and a destination.
+ * Here, we return the result without storing into a destination.
+ */
+static TCGv_i32 op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a,
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp1, tmp2;
+
+ tmp2 = load_reg(s, a->rm);
+ gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc);
+ tmp1 = load_reg(s, a->rn);
+
+ gen(tmp1, tmp1, tmp2);
+ tcg_temp_free_i32(tmp2);
+
+ if (logic_cc) {
+ gen_logic_CC(tmp1);
+ }
+ return tmp1;
+}
+
+static TCGv_i32 op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a,
+ void (*gen)(TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp;
+
+ tmp = load_reg(s, a->rm);
+ gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc);
+
+ gen(tmp, tmp);
+ if (logic_cc) {
+ gen_logic_CC(tmp);
+ }
+ return tmp;
+}
+
+/*
+ * Data-processing (register-shifted register)
+ *
+ * Operate, with set flags, one register source,
+ * one register shifted register source, and a destination.
+ * Here, we return the result without storing into a destination.
+ */
+static TCGv_i32 op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a,
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp1, tmp2;
+
+ tmp1 = load_reg(s, a->rs);
+ tmp2 = load_reg(s, a->rm);
+ gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc);
+ tmp1 = load_reg(s, a->rn);
+
+ gen(tmp1, tmp1, tmp2);
+ tcg_temp_free_i32(tmp2);
+
+ if (logic_cc) {
+ gen_logic_CC(tmp1);
+ }
+ return tmp1;
+}
+
+static TCGv_i32 op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a,
+ void (*gen)(TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp1, tmp2;
+
+ tmp1 = load_reg(s, a->rs);
+ tmp2 = load_reg(s, a->rm);
+ gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc);
+
+ gen(tmp2, tmp2);
+ if (logic_cc) {
+ gen_logic_CC(tmp2);
+ }
+ return tmp2;
+}
+
+/*
+ * Data-processing (immediate)
+ *
+ * Operate, with set flags, one register source,
+ * one rotated immediate, and a destination.
+ * Here, we return the result without storing into a destination.
+ */
+static TCGv_i32 op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a,
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp1, tmp2;
+ uint32_t imm;
+
+ imm = ror32(a->imm, a->rot);
+ if (logic_cc && a->rot) {
+ tcg_gen_movi_i32(cpu_CF, imm >> 31);
+ }
+ tmp2 = tcg_const_i32(imm);
+ tmp1 = load_reg(s, a->rn);
+
+ gen(tmp1, tmp1, tmp2);
+ tcg_temp_free_i32(tmp2);
+
+ if (logic_cc) {
+ gen_logic_CC(tmp1);
+ }
+ return tmp1;
+}
+
+static TCGv_i32 op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a,
+ void (*gen)(TCGv_i32, TCGv_i32),
+ int logic_cc)
+{
+ TCGv_i32 tmp;
+ uint32_t imm;
+
+ imm = ror32(a->imm, a->rot);
+ if (logic_cc && a->rot) {
+ tcg_gen_movi_i32(cpu_CF, imm >> 31);
+ }
+ tmp = tcg_const_i32(imm);
+
+ gen(tmp, tmp);
+ if (logic_cc) {
+ gen_logic_CC(tmp);
+ }
+ return tmp;
+}
+
+#define DO_ANY3(NAME, OPERATION, LOGIC_CC, FLAGS) \
+static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rrr_shi(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+} \
+static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rrr_shr(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+} \
+static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rri_rot(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+}
+
+#define DO_ANY2(NAME, OPERATION, LOGIC_CC, FLAGS) \
+static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rxr_shi(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+} \
+static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rxr_shr(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+} \
+static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \
+{ \
+ StoreRegKind flags = FLAGS; \
+ TCGv_i32 val = op_s_rxi_rot(s, a, OPERATION, LOGIC_CC); \
+ return store_reg_flags(s, a->rd, val, flags); \
+}
+
+#define DO_LOGIC(NAME, OPERATION, FLAGS) DO_ANY3(NAME, OPERATION, a->s, FLAGS)
+
+DO_LOGIC(AND, tcg_gen_and_i32, STREG_NORMAL)
+DO_LOGIC(EOR, tcg_gen_xor_i32, STREG_NORMAL)
+DO_LOGIC(ORR, tcg_gen_or_i32, STREG_NORMAL)
+DO_LOGIC(BIC, tcg_gen_andc_i32, STREG_NORMAL)
+
+DO_ANY2(MOV, tcg_gen_mov_i32, a->s,
+ ({
+ int result = STREG_SP_CHECK;
+ if (a->s && a->rd == 15) {
+ if (IS_USER(s)) {
+ return false;
+ }
+ result = STREG_EXC_RET;
+ }
+ result;
+ }))
+
+DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL)
+
+DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL)
+DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL)
+DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL)
+DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL)
+
+DO_ANY3(TST, tcg_gen_and_i32, true, STREG_NONE)
+DO_ANY3(TEQ, tcg_gen_xor_i32, true, STREG_NONE)
+DO_ANY3(CMN, gen_add_CC, false, STREG_NONE)
+DO_ANY3(CMP, gen_sub_CC, false, STREG_NONE)
+
+DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false,
+ ({
+ int result = STREG_SP_CHECK;
+ if (a->s && a->rd == 15) {
+ if (IS_USER(s)) {
+ return false;
+ }
+ result = STREG_EXC_RET;
+ } else if (a->rn == 13) {
+ result = STREG_SP_CHECK;
+ }
+ result;
+ }))
+
+DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false,
+ a->rn == 13 ? STREG_SP_CHECK : STREG_NORMAL)
+
+/*
+ * ORN is only available with T32, and so there is no c_s_rrr_shr decode.
+ * Using the DO_LOGIC macro would create an unused function.
+ */
+static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a)
+{
+ TCGv_i32 val = op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s);
+ return store_reg_flags(s, a->rd, val, STREG_NORMAL);
+}
+
+static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a)
+{
+ TCGv_i32 val = op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s);
+ return store_reg_flags(s, a->rd, val, STREG_NORMAL);
+}
+
+#undef DO_ANY
+#undef DO_LOGIC
+
/*
* Legacy decoder.
*/
@@ -8273,184 +8599,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
} else if (((insn & 0x0e000000) == 0 &&
(insn & 0x00000090) != 0x90) ||
((insn & 0x0e000000) == (1 << 25))) {
- int set_cc, logic_cc, shiftop;
-
- op1 = (insn >> 21) & 0xf;
- set_cc = (insn >> 20) & 1;
- logic_cc = table_logic_cc[op1] & set_cc;
-
- /* data processing instruction */
- if (insn & (1 << 25)) {
- /* immediate operand */
- val = insn & 0xff;
- shift = ((insn >> 8) & 0xf) * 2;
- if (shift) {
- val = (val >> shift) | (val << (32 - shift));
- }
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, val);
- if (logic_cc && shift) {
- gen_set_CF_bit31(tmp2);
- }
- } else {
- /* register */
- rm = (insn) & 0xf;
- tmp2 = load_reg(s, rm);
- shiftop = (insn >> 5) & 3;
- if (!(insn & (1 << 4))) {
- shift = (insn >> 7) & 0x1f;
- gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
- } else {
- rs = (insn >> 8) & 0xf;
- tmp = load_reg(s, rs);
- gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
- }
- }
- if (op1 != 0x0f && op1 != 0x0d) {
- rn = (insn >> 16) & 0xf;
- tmp = load_reg(s, rn);
- } else {
- tmp = NULL;
- }
- rd = (insn >> 12) & 0xf;
- switch(op1) {
- case 0x00:
- tcg_gen_and_i32(tmp, tmp, tmp2);
- if (logic_cc) {
- gen_logic_CC(tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x01:
- tcg_gen_xor_i32(tmp, tmp, tmp2);
- if (logic_cc) {
- gen_logic_CC(tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x02:
- if (set_cc && rd == 15) {
- /* SUBS r15, ... is used for exception return. */
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_sub_CC(tmp, tmp, tmp2);
- gen_exception_return(s, tmp);
- } else {
- if (set_cc) {
- gen_sub_CC(tmp, tmp, tmp2);
- } else {
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- }
- store_reg_bx(s, rd, tmp);
- }
- break;
- case 0x03:
- if (set_cc) {
- gen_sub_CC(tmp, tmp2, tmp);
- } else {
- tcg_gen_sub_i32(tmp, tmp2, tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x04:
- if (set_cc) {
- gen_add_CC(tmp, tmp, tmp2);
- } else {
- tcg_gen_add_i32(tmp, tmp, tmp2);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x05:
- if (set_cc) {
- gen_adc_CC(tmp, tmp, tmp2);
- } else {
- gen_add_carry(tmp, tmp, tmp2);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x06:
- if (set_cc) {
- gen_sbc_CC(tmp, tmp, tmp2);
- } else {
- gen_sub_carry(tmp, tmp, tmp2);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x07:
- if (set_cc) {
- gen_sbc_CC(tmp, tmp2, tmp);
- } else {
- gen_sub_carry(tmp, tmp2, tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x08:
- if (set_cc) {
- tcg_gen_and_i32(tmp, tmp, tmp2);
- gen_logic_CC(tmp);
- }
- tcg_temp_free_i32(tmp);
- break;
- case 0x09:
- if (set_cc) {
- tcg_gen_xor_i32(tmp, tmp, tmp2);
- gen_logic_CC(tmp);
- }
- tcg_temp_free_i32(tmp);
- break;
- case 0x0a:
- if (set_cc) {
- gen_sub_CC(tmp, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp);
- break;
- case 0x0b:
- if (set_cc) {
- gen_add_CC(tmp, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp);
- break;
- case 0x0c:
- tcg_gen_or_i32(tmp, tmp, tmp2);
- if (logic_cc) {
- gen_logic_CC(tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- case 0x0d:
- if (logic_cc && rd == 15) {
- /* MOVS r15, ... is used for exception return. */
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_exception_return(s, tmp2);
- } else {
- if (logic_cc) {
- gen_logic_CC(tmp2);
- }
- store_reg_bx(s, rd, tmp2);
- }
- break;
- case 0x0e:
- tcg_gen_andc_i32(tmp, tmp, tmp2);
- if (logic_cc) {
- gen_logic_CC(tmp);
- }
- store_reg_bx(s, rd, tmp);
- break;
- default:
- case 0x0f:
- tcg_gen_not_i32(tmp2, tmp2);
- if (logic_cc) {
- gen_logic_CC(tmp2);
- }
- store_reg_bx(s, rd, tmp2);
- break;
- }
- if (op1 != 0x0f && op1 != 0x0d) {
- tcg_temp_free_i32(tmp2);
- }
+ /* Data-processing (reg, reg-shift-reg, imm). */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
} else {
/* other instructions */
op1 = (insn >> 24) & 0xf;
@@ -9348,89 +9499,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
return true;
}
-/* Return true if this is a Thumb-2 logical op. */
-static int
-thumb2_logic_op(int op)
-{
- return (op < 8);
-}
-
-/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
- then set condition code flags based on the result of the operation.
- If SHIFTER_OUT is nonzero then set the carry flag for logical operations
- to the high bit of T1.
- Returns zero if the opcode is valid. */
-
-static int
-gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
- TCGv_i32 t0, TCGv_i32 t1)
-{
- int logic_cc;
-
- logic_cc = 0;
- switch (op) {
- case 0: /* and */
- tcg_gen_and_i32(t0, t0, t1);
- logic_cc = conds;
- break;
- case 1: /* bic */
- tcg_gen_andc_i32(t0, t0, t1);
- logic_cc = conds;
- break;
- case 2: /* orr */
- tcg_gen_or_i32(t0, t0, t1);
- logic_cc = conds;
- break;
- case 3: /* orn */
- tcg_gen_orc_i32(t0, t0, t1);
- logic_cc = conds;
- break;
- case 4: /* eor */
- tcg_gen_xor_i32(t0, t0, t1);
- logic_cc = conds;
- break;
- case 8: /* add */
- if (conds)
- gen_add_CC(t0, t0, t1);
- else
- tcg_gen_add_i32(t0, t0, t1);
- break;
- case 10: /* adc */
- if (conds)
- gen_adc_CC(t0, t0, t1);
- else
- gen_adc(t0, t1);
- break;
- case 11: /* sbc */
- if (conds) {
- gen_sbc_CC(t0, t0, t1);
- } else {
- gen_sub_carry(t0, t0, t1);
- }
- break;
- case 13: /* sub */
- if (conds)
- gen_sub_CC(t0, t0, t1);
- else
- tcg_gen_sub_i32(t0, t0, t1);
- break;
- case 14: /* rsb */
- if (conds)
- gen_sub_CC(t0, t1, t0);
- else
- tcg_gen_sub_i32(t0, t1, t0);
- break;
- default: /* 5, 6, 7, 9, 12, 15. */
- return 1;
- }
- if (logic_cc) {
- gen_logic_CC(t0);
- if (shifter_out)
- gen_set_CF_bit31(t1);
- }
- return 0;
-}
-
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
@@ -9442,9 +9510,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
TCGv_i32 addr;
TCGv_i64 tmp64;
int op;
- int shiftop;
- int conds;
- int logic_cc;
/*
* ARMv6-M supports a limited subset of Thumb2 instructions.
@@ -9881,33 +9946,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
store_reg(s, rd, tmp);
} else {
/* Data processing register constant shift. */
- if (rn == 15) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else {
- tmp = load_reg(s, rn);
- }
- tmp2 = load_reg(s, rm);
-
- shiftop = (insn >> 4) & 3;
- shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
- conds = (insn & (1 << 20)) != 0;
- logic_cc = (conds && thumb2_logic_op(op));
- gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
- if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
- goto illegal_op;
- tcg_temp_free_i32(tmp2);
- if (rd == 13 &&
- ((op == 2 && rn == 15) ||
- (op == 8 && rn == 13) ||
- (op == 13 && rn == 13))) {
- /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */
- store_sp_checked(s, tmp);
- } else if (rd != 15) {
- store_reg(s, rd, tmp);
- } else {
- tcg_temp_free_i32(tmp);
- }
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
}
break;
case 13: /* Misc data processing. */
@@ -9915,22 +9955,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
if (op < 4 && (insn & 0xf000) != 0xf000)
goto illegal_op;
switch (op) {
- case 0: /* Register controlled shift. */
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- if ((insn & 0x70) != 0)
- goto illegal_op;
- /*
- * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx:
- * - MOV, MOVS (register-shifted register), flagsetting
- */
- op = (insn >> 21) & 3;
- logic_cc = (insn & (1 << 20)) != 0;
- gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
- if (logic_cc)
- gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
- break;
+ case 0: /* Register controlled shift, in decodetree */
+ goto illegal_op;
case 1: /* Sign/zero extend. */
op = (insn >> 20) & 7;
switch (op) {
@@ -10753,60 +10779,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
} else {
- /*
- * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx
- * - Data-processing (modified immediate)
- */
- int shifter_out = 0;
- /* modified 12-bit immediate. */
- shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
- imm = (insn & 0xff);
- switch (shift) {
- case 0: /* XY */
- /* Nothing to do. */
- break;
- case 1: /* 00XY00XY */
- imm |= imm << 16;
- break;
- case 2: /* XY00XY00 */
- imm |= imm << 16;
- imm <<= 8;
- break;
- case 3: /* XYXYXYXY */
- imm |= imm << 16;
- imm |= imm << 8;
- break;
- default: /* Rotated constant. */
- shift = (shift << 1) | (imm >> 7);
- imm |= 0x80;
- imm = imm << (32 - shift);
- shifter_out = 1;
- break;
- }
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, imm);
- rn = (insn >> 16) & 0xf;
- if (rn == 15) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else {
- tmp = load_reg(s, rn);
- }
- op = (insn >> 21) & 0xf;
- if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
- shifter_out, tmp, tmp2))
- goto illegal_op;
- tcg_temp_free_i32(tmp2);
- rd = (insn >> 8) & 0xf;
- if (rd == 13 && rn == 13
- && (op == 8 || op == 13)) {
- /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */
- store_sp_checked(s, tmp);
- } else if (rd != 15) {
- store_reg(s, rd, tmp);
- } else {
- tcg_temp_free_i32(tmp);
- }
+ /* Data-processing (modified immediate) */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
}
}
break;
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 2d84a02861..1db621576f 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -21,3 +21,87 @@
# All of the insn that have a COND field in insn[31:28] are here.
# All insns that have 0xf in insn[31:28] are in a32u.decode.
#
+
+&s_rrr_shi s rd rn rm shim shty
+&s_rrr_shr s rn rd rm rs shty
+&s_rri_rot s rn rd imm rot
+
+# Data-processing (register)
+
+@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
+ &s_rrr_shi
+@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
+ &s_rrr_shi rn=0
+@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
+ &s_rrr_shi s=1 rd=0
+
+AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi
+EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi
+SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi
+RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi
+ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi
+ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi
+SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi
+RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi
+TST_rrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi
+TEQ_rrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi
+CMP_rrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi
+CMN_rrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi
+ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi
+MOV_rrri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
+BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
+MVN_rrri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
+
+# Data-processing (register-shifted register)
+
+@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
+ &s_rrr_shr
+@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
+ &s_rrr_shr rn=0
+@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
+ &s_rrr_shr rd=0 s=1
+
+AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr
+EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr
+SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr
+RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr
+ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr
+ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr
+SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr
+RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr
+TST_rrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
+TEQ_rrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
+CMP_rrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
+CMN_rrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
+ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr
+MOV_rrrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
+BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr
+MVN_rrrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
+
+# Data-processing (immediate)
+
+%a32extrot 8:4 !function=times_2
+
+@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \
+ &s_rri_rot rot=%a32extrot
+@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \
+ &s_rri_rot rot=%a32extrot rn=0
+@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \
+ &s_rri_rot rot=%a32extrot rd=0 s=1
+
+AND_rri .... 001 0000 . .... .... ............ @s_rri_rot
+EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot
+SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot
+RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot
+ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot
+ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot
+SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot
+RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot
+TST_rri .... 001 1000 1 .... 0000 ............ @S_xri_rot
+TEQ_rri .... 001 1001 1 .... 0000 ............ @S_xri_rot
+CMP_rri .... 001 1010 1 .... 0000 ............ @S_xri_rot
+CMN_rri .... 001 1011 1 .... 0000 ............ @S_xri_rot
+ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot
+MOV_rri .... 001 1101 . 0000 .... ............ @s_rxi_rot
+BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot
+MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index ac01fb6958..7bfd8ee854 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -18,3 +18,94 @@
#
# This file is processed by scripts/decodetree.py
#
+
+&s_rrr_shi !extern s rd rn rm shim shty
+&s_rrr_shr !extern s rn rd rm rs shty
+&s_rri_rot !extern s rn rd imm rot
+
+# Data-processing (register-shifted register)
+
+MOV_rrrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
+ &s_rrr_shr rn=0
+
+# Data-processing (register)
+
+%imm5_12_6 12:3 6:2
+
+@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
+ &s_rrr_shi shim=%imm5_12_6
+@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
+ &s_rrr_shi shim=%imm5_12_6 rn=0
+@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
+ &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
+
+{
+ TST_rrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
+ AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
+}
+BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
+{
+ MOV_rrri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
+ ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
+}
+{
+ MVN_rrri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
+ ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi
+}
+{
+ TEQ_rrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi
+ EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi
+}
+# PKHBT, PKHTB at opc1 = 0110
+{
+ CMN_rrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
+ ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
+}
+ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi
+SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
+{
+ CMP_rrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi
+ SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi
+}
+RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
+
+# Data-processing (immediate)
+
+%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot
+%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm
+
+@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \
+ &s_rri_rot imm=%t32extimm rot=%t32extrot
+@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \
+ &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
+@S_xri_rot ....... .... . rn:4 . ... .... ........ \
+ &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
+
+{
+ TST_rri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot
+ AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot
+}
+BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot
+{
+ MOV_rri 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot
+ ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot
+}
+{
+ MVN_rri 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot
+ ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot
+}
+{
+ TEQ_rri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot
+ EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot
+}
+{
+ CMN_rri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
+ ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
+}
+ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot
+SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
+{
+ CMP_rri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot
+ SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
+}
+RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (12 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-08-05 15:32 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
` (54 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 214 ++++++++++++++++++++++++-----------------
target/arm/a32.decode | 17 ++++
target/arm/t32.decode | 19 ++++
3 files changed, 163 insertions(+), 87 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ee7d53dfa5..354a52d36c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7376,21 +7376,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
store_reg(s, rhigh, tmp);
}
-/* load a 32-bit value from a register and perform a 64-bit accumulate. */
-static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
-{
- TCGv_i64 tmp;
- TCGv_i32 tmp2;
-
- /* Load value and extend to 64 bits. */
- tmp = tcg_temp_new_i64();
- tmp2 = load_reg(s, rlow);
- tcg_gen_extu_i32_i64(tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- tcg_gen_add_i64(val, val, tmp);
- tcg_temp_free_i64(tmp);
-}
-
/* load and add a 64-bit value from a register pair. */
static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
{
@@ -8068,6 +8053,128 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a)
#undef DO_ANY
#undef DO_LOGIC
+/*
+ * Multiply and multiply accumulate
+ */
+
+static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add)
+{
+ TCGv_i32 t1, t2;
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ tcg_gen_mul_i32(t1, t1, t2);
+ tcg_temp_free_i32(t2);
+ if (add) {
+ t2 = load_reg(s, a->ra);
+ tcg_gen_add_i32(t1, t1, t2);
+ tcg_temp_free_i32(t2);
+ }
+ if (a->s) {
+ gen_logic_CC(t1);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool trans_MUL(DisasContext *s, arg_MUL *a)
+{
+ return op_mla(s, a, false);
+}
+
+static bool trans_MLA(DisasContext *s, arg_MLA *a)
+{
+ return op_mla(s, a, true);
+}
+
+static bool trans_MLS(DisasContext *s, arg_MLS *a)
+{
+ TCGv_i32 t1, t2;
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ tcg_gen_mul_i32(t1, t1, t2);
+ tcg_temp_free_i32(t2);
+ t2 = load_reg(s, a->ra);
+ tcg_gen_sub_i32(t1, t2, t1);
+ tcg_temp_free_i32(t2);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add)
+{
+ TCGv_i32 t0, t1, t2, t3;
+
+ t0 = load_reg(s, a->rm);
+ t1 = load_reg(s, a->rn);
+ if (uns) {
+ tcg_gen_mulu2_i32(t0, t1, t0, t1);
+ } else {
+ tcg_gen_muls2_i32(t0, t1, t0, t1);
+ }
+ if (add) {
+ t2 = load_reg(s, a->ra);
+ t3 = load_reg(s, a->rd);
+ tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ store_reg(s, a->ra, t0);
+ store_reg(s, a->rd, t1);
+ if (a->s) {
+ gen_logicq_cc(t0, t1);
+ }
+ return true;
+}
+
+static bool trans_UMULL(DisasContext *s, arg_UMULL *a)
+{
+ return op_mlal(s, a, true, false);
+}
+
+static bool trans_SMULL(DisasContext *s, arg_SMULL *a)
+{
+ return op_mlal(s, a, false, false);
+}
+
+static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a)
+{
+ return op_mlal(s, a, true, true);
+}
+
+static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a)
+{
+ return op_mlal(s, a, false, true);
+}
+
+static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
+{
+ TCGv_i32 t0, t1, t2, zero;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rm);
+ t1 = load_reg(s, a->rn);
+ tcg_gen_mulu2_i32(t0, t1, t0, t1);
+ zero = tcg_const_i32(0);
+ t2 = load_reg(s, a->ra);
+ tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
+ tcg_temp_free_i32(t2);
+ t2 = load_reg(s, a->rd);
+ tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(zero);
+ store_reg(s, a->ra, t0);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+
/*
* Legacy decoder.
*/
@@ -8612,71 +8719,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
sh = (insn >> 5) & 3;
if (sh == 0) {
if (op1 == 0x0) {
- rd = (insn >> 16) & 0xf;
- rn = (insn >> 12) & 0xf;
- rs = (insn >> 8) & 0xf;
- rm = (insn) & 0xf;
- op1 = (insn >> 20) & 0xf;
- switch (op1) {
- case 0: case 1: case 2: case 3: case 6:
- /* 32 bit mul */
- tmp = load_reg(s, rs);
- tmp2 = load_reg(s, rm);
- tcg_gen_mul_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (insn & (1 << 22)) {
- /* Subtract (mls) */
- ARCH(6T2);
- tmp2 = load_reg(s, rn);
- tcg_gen_sub_i32(tmp, tmp2, tmp);
- tcg_temp_free_i32(tmp2);
- } else if (insn & (1 << 21)) {
- /* Add */
- tmp2 = load_reg(s, rn);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- if (insn & (1 << 20))
- gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
- break;
- case 4:
- /* 64 bit mul double accumulate (UMAAL) */
- ARCH(6);
- tmp = load_reg(s, rs);
- tmp2 = load_reg(s, rm);
- tmp64 = gen_mulu_i64_i32(tmp, tmp2);
- gen_addq_lo(s, tmp64, rn);
- gen_addq_lo(s, tmp64, rd);
- gen_storeq_reg(s, rn, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- break;
- case 8: case 9: case 10: case 11:
- case 12: case 13: case 14: case 15:
- /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
- tmp = load_reg(s, rs);
- tmp2 = load_reg(s, rm);
- if (insn & (1 << 22)) {
- tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
- } else {
- tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
- }
- if (insn & (1 << 21)) { /* mult accumulate */
- TCGv_i32 al = load_reg(s, rn);
- TCGv_i32 ah = load_reg(s, rd);
- tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah);
- tcg_temp_free_i32(al);
- tcg_temp_free_i32(ah);
- }
- if (insn & (1 << 20)) {
- gen_logicq_cc(tmp, tmp2);
- }
- store_reg(s, rn, tmp);
- store_reg(s, rd, tmp2);
- break;
- default:
- goto illegal_op;
- }
+ /* Multiply and multiply accumulate. */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
} else {
rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf;
@@ -10292,13 +10337,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
if (op & 4) {
- /* umaal */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i64(tmp64);
- goto illegal_op;
- }
- gen_addq_lo(s, tmp64, rs);
- gen_addq_lo(s, tmp64, rd);
+ /* umaal, in decodetree */
+ goto illegal_op;
} else if (op & 0x40) {
/* 64-bit accumulate. */
gen_addq(s, tmp64, rs, rd);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 1db621576f..71846b79fd 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -25,6 +25,8 @@
&s_rrr_shi s rd rn rm shim shty
&s_rrr_shr s rn rd rm rs shty
&s_rri_rot s rn rd imm rot
+&s_rrrr s rd rn rm ra
+&rrrr rd rn rm ra
# Data-processing (register)
@@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot
MOV_rri .... 001 1101 . 0000 .... ............ @s_rxi_rot
BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot
MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot
+
+# Multiply and multiply accumulate
+
+@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
+@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
+@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
+
+MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
+MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
+UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn
+MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn
+UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn
+UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn
+SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn
+SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 7bfd8ee854..8e301ed2a1 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -22,6 +22,8 @@
&s_rrr_shi !extern s rd rn rm shim shty
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
+&s_rrrr !extern s rd rn rm ra
+&rrrr !extern rd rn rm ra
# Data-processing (register-shifted register)
@@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
+
+# Multiply and multiply accumulate
+
+@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
+@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
+@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
+
+{
+ MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm
+ MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm
+}
+MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm
+SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm
+UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
+SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
+UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
+UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (13 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-08-05 15:40 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
` (53 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 1 -
target/arm/op_helper.c | 15 ---------
target/arm/translate.c | 74 +++++++++++++++++++++++++++---------------
target/arm/a32.decode | 10 ++++++
target/arm/t32.decode | 9 +++++
5 files changed, 66 insertions(+), 43 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 132aa1682e..1fb2cb5a77 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -6,7 +6,6 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32)
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
-DEF_HELPER_2(double_saturate, i32, env, s32)
DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32)
DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 1ab91f915e..142239b03a 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -135,21 +135,6 @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
return res;
}
-uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
-{
- uint32_t res;
- if (val >= 0x40000000) {
- res = ~SIGNBIT;
- env->QF = 1;
- } else if (val <= (int32_t)0xc0000000) {
- res = SIGNBIT;
- env->QF = 1;
- } else {
- res = val << 1;
- }
- return res;
-}
-
uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 354a52d36c..85f829c1bb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8174,6 +8174,47 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
return true;
}
+/*
+ * Saturating addition and subtraction
+ */
+
+static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub)
+{
+ TCGv_i32 t0, t1;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rm);
+ t1 = load_reg(s, a->rn);
+ if (doub) {
+ gen_helper_add_saturate(t1, cpu_env, t1, t1);
+ }
+ if (add) {
+ gen_helper_add_saturate(t0, cpu_env, t0, t1);
+ } else {
+ gen_helper_sub_saturate(t0, cpu_env, t0, t1);
+ }
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ return true;
+}
+
+#define DO_QADDSUB(NAME, ADD, DOUB) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+{ \
+ return op_qaddsub(s, a, ADD, DOUB); \
+}
+
+DO_QADDSUB(QADD, true, false)
+DO_QADDSUB(QSUB, false, false)
+DO_QADDSUB(QDADD, true, true)
+DO_QADDSUB(QDSUB, false, true)
+
+#undef DO_QADDSUB
/*
* Legacy decoder.
@@ -8582,21 +8623,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
store_reg(s, rd, tmp);
break;
}
- case 0x5: /* saturating add/subtract */
- ARCH(5TE);
- rd = (insn >> 12) & 0xf;
- rn = (insn >> 16) & 0xf;
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rn);
- if (op1 & 2)
- gen_helper_double_saturate(tmp2, cpu_env, tmp2);
- if (op1 & 1)
- gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
- else
- gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
+ case 0x5:
+ /* Saturating addition and subtraction. */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
case 0x6: /* ERET */
if (op1 != 3) {
goto illegal_op;
@@ -10070,18 +10100,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
if (op < 4) {
/* Saturating add/subtract. */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- if (op & 1)
- gen_helper_double_saturate(tmp, cpu_env, tmp);
- if (op & 2)
- gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
- else
- gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
} else {
switch (op) {
case 0x0a: /* rbit */
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 71846b79fd..af6712a9e8 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -27,6 +27,7 @@
&s_rri_rot s rn rd imm rot
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
+&rrr rd rn rm
# Data-processing (register)
@@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn
UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn
SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn
SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn
+
+# Saturating addition and subtraction
+
+@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr
+
+QADD .... 0001 0000 .... .... 0000 0101 .... @rndm
+QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm
+QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm
+QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 8e301ed2a1..7a27b5cc5c 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -24,6 +24,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
+&rrr !extern rd rn rm
# Data-processing (register-shifted register)
@@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
+@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
{
MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm
@@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
+
+# Data-processing (two source registers)
+
+QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
+QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
+QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
+QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (14 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints Richard Henderson
` (52 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 216 ++++++++++++++++++++++-------------------
target/arm/a32.decode | 20 ++++
target/arm/t32.decode | 29 ++++++
3 files changed, 167 insertions(+), 98 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 85f829c1bb..2140671eb2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8216,6 +8216,114 @@ DO_QADDSUB(QDSUB, false, true)
#undef DO_QADDSUB
+/*
+ * Halfword multiply and multiply accumulate
+ */
+
+static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
+ int add_long, bool nt, bool mt)
+{
+ TCGv_i32 t0, t1, tl, th;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ gen_mulxy(t0, t1, nt, mt);
+ tcg_temp_free_i32(t1);
+
+ switch (add_long) {
+ case 0:
+ store_reg(s, a->rd, t0);
+ break;
+ case 1:
+ t1 = load_reg(s, a->ra);
+ gen_helper_add_setq(t0, cpu_env, t0, t1);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ break;
+ case 2:
+ tl = load_reg(s, a->ra);
+ th = load_reg(s, a->rd);
+ tcg_gen_add2_i32(tl, th, tl, th, t0, t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->ra, tl);
+ store_reg(s, a->rd, th);
+ }
+ return true;
+}
+
+#define DO_SMLAX(NAME, add, nt, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlaxxx(s, a, add, nt, mt); \
+}
+
+DO_SMLAX(SMULBB, 0, 0, 0)
+DO_SMLAX(SMULBT, 0, 0, 1)
+DO_SMLAX(SMULTB, 0, 1, 0)
+DO_SMLAX(SMULTT, 0, 1, 1)
+
+DO_SMLAX(SMLABB, 1, 0, 0)
+DO_SMLAX(SMLABT, 1, 0, 1)
+DO_SMLAX(SMLATB, 1, 1, 0)
+DO_SMLAX(SMLATT, 1, 1, 1)
+
+DO_SMLAX(SMLALBB, 2, 0, 0)
+DO_SMLAX(SMLALBT, 2, 0, 1)
+DO_SMLAX(SMLALTB, 2, 1, 0)
+DO_SMLAX(SMLALTT, 2, 1, 1)
+
+#undef DO_SMLAX
+
+static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
+{
+ TCGv_i32 t0, t1;
+
+ if (!ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ /*
+ * Since the nominal result is product<47:16>, shift the 16-bit
+ * input up by 16 bits, so that the result is at product<63:32>.
+ */
+ if (mt) {
+ tcg_gen_andi_i32(t1, t1, 0xffff0000);
+ } else {
+ tcg_gen_shli_i32(t1, t1, 16);
+ }
+ tcg_gen_muls2_i32(t0, t1, t0, t1);
+ tcg_temp_free_i32(t0);
+ if (add) {
+ t0 = load_reg(s, a->ra);
+ gen_helper_add_setq(t1, cpu_env, t1, t0);
+ tcg_temp_free_i32(t0);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+#define DO_SMLAWX(NAME, add, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlawx(s, a, add, mt); \
+}
+
+DO_SMLAWX(SMULWB, 0, 0)
+DO_SMLAWX(SMULWT, 0, 1)
+DO_SMLAWX(SMLAWB, 1, 0)
+DO_SMLAWX(SMLAWT, 1, 1)
+
+#undef DO_SMLAWX
+
/*
* Legacy decoder.
*/
@@ -8680,56 +8788,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
break;
}
- case 0x8: /* signed multiply */
+ case 0x8:
case 0xa:
case 0xc:
case 0xe:
- ARCH(5TE);
- rs = (insn >> 8) & 0xf;
- rn = (insn >> 12) & 0xf;
- rd = (insn >> 16) & 0xf;
- if (op1 == 1) {
- /* (32 * 16) >> 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- if (sh & 4)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if ((sh & 2) == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- } else {
- /* 16 * 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
- tcg_temp_free_i32(tmp2);
- if (op1 == 2) {
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
- gen_addq(s, tmp64, rn, rd);
- gen_storeq_reg(s, rn, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- } else {
- if (op1 == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- }
- }
- break;
+ /* Halfword multiply and multiply accumulate. */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
default:
goto illegal_op;
}
@@ -10189,11 +10254,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
switch ((insn >> 20) & 7) {
case 0: /* 32 x 32 -> 32 */
+ case 1: /* 16 x 16 -> 32 */
+ case 3: /* 32 * 16 -> 32msb */
+ /* in decodetree */
+ goto illegal_op;
case 7: /* Unsigned sum of absolute differences. */
break;
- case 1: /* 16 x 16 -> 32 */
case 2: /* Dual multiply add. */
- case 3: /* 32 * 16 -> 32msb */
case 4: /* Dual multiply subtract. */
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
@@ -10205,27 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
switch ((insn >> 20) & 7) {
- case 0: /* 32 x 32 -> 32 */
- tcg_gen_mul_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- if (op)
- tcg_gen_sub_i32(tmp, tmp2, tmp);
- else
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
- case 1: /* 16 x 16 -> 32 */
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 2: /* Dual multiply add. */
case 4: /* Dual multiply subtract. */
if (op)
@@ -10249,23 +10295,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp2);
}
break;
- case 3: /* 32 * 16 -> 32msb */
- if (op)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
tmp64 = gen_muls_i64_i32(tmp, tmp2);
if (rs != 15) {
@@ -10340,17 +10369,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp64 = gen_mulu_i64_i32(tmp, tmp2);
} else {
if (op & 8) {
- /* smlalxy */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- goto illegal_op;
- }
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
- tcg_temp_free_i32(tmp2);
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
+ /* smlalxy, in decodetree */
+ goto illegal_op;
} else {
/* Signed 64-bit multiply */
tmp64 = gen_muls_i64_i32(tmp, tmp2);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index af6712a9e8..8dc74dfdb8 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -114,6 +114,7 @@ MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot
@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
+@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0
MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
@@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm
QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm
QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm
QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm
+
+# Halfword multiply and multiply accumulate
+
+SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn
+SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn
+SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn
+SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn
+SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn
+SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn
+SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn
+SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn
+SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn
+SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn
+SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn
+SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn
+SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn
+SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn
+SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn
+SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 7a27b5cc5c..e611ac4969 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
+@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
{
@@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
+{
+ SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm
+ SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm
+ SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm
+ SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm
+ SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm
+ SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm
+}
+{
+ SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm
+ SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm
+}
+SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm
+SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm
+SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm
+SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
# Data-processing (two source registers)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (15 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
` (51 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 61 +++++++++++++++++++++++++++++-------------
target/arm/a32.decode | 25 +++++++++++++++++
target/arm/t32.decode | 17 ++++++++++++
3 files changed, 84 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2140671eb2..36c815caf3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8324,6 +8324,44 @@ DO_SMLAWX(SMLAWT, 1, 1)
#undef DO_SMLAWX
+/*
+ * MSR (immediate) and hints
+ */
+
+static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
+{
+ gen_nop_hint(s, 1);
+ return true;
+}
+
+static bool trans_WFE(DisasContext *s, arg_WFE *a)
+{
+ gen_nop_hint(s, 2);
+ return true;
+}
+
+static bool trans_WFI(DisasContext *s, arg_WFI *a)
+{
+ gen_nop_hint(s, 2);
+ return true;
+}
+
+static bool trans_NOP(DisasContext *s, arg_NOP *a)
+{
+ return true;
+}
+
+static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a)
+{
+ uint32_t val = ror32(a->imm, a->rot * 2);
+ uint32_t mask = msr_mask(s, a->mask, a->r);
+
+ if (gen_set_psr_im(s, mask, a->r, val)) {
+ gen_illegal_op(s);
+ }
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -8594,22 +8632,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
store_reg(s, rd, tmp);
} else {
- if (((insn >> 12) & 0xf) != 0xf)
- goto illegal_op;
- if (((insn >> 16) & 0xf) == 0) {
- gen_nop_hint(s, insn & 0xff);
- } else {
- /* CPSR = immediate */
- val = insn & 0xff;
- shift = ((insn >> 8) & 0xf) * 2;
- if (shift)
- val = (val >> shift) | (val << (32 - shift));
- i = ((insn & (1 << 22)) != 0);
- if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
- i, val)) {
- goto illegal_op;
- }
- }
+ /* MSR (immediate) and hints */
+ /* All done in decodetree. Illegal ops already signalled. */
+ g_assert_not_reached();
}
} else if ((insn & 0x0f900000) == 0x01000000
&& (insn & 0x00000090) != 0x00000090) {
@@ -10569,9 +10594,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
break;
case 2: /* cps, nop-hint. */
- if (((insn >> 8) & 7) == 0) {
- gen_nop_hint(s, insn & 0xff);
- }
+ /* nop hints in decodetree */
/* Implemented as NOP in user mode. */
if (IS_USER(s))
break;
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 8dc74dfdb8..4cefba6f0e 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -22,6 +22,7 @@
# All insns that have 0xf in insn[31:28] are in a32u.decode.
#
+&empty
&s_rrr_shi s rd rn rm shim shty
&s_rrr_shr s rn rd rm rs shty
&s_rri_rot s rn rd imm rot
@@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn
SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn
SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn
SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
+
+# MSR (immediate) and hints
+
+&msr_i r mask rot imm
+@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i
+
+{
+ {
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
+
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
+
+ # The canonical nop ends in 00000000, but the whole of the
+ # rest of the space executes as nop if otherwise unsupported.
+ NOP ---- 0011 0010 0000 1111 ---- ---- ----
+ }
+ # Note mask = 0 is covered by NOP
+ MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0
+}
+MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index e611ac4969..b4f0a9632d 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -19,6 +19,7 @@
# This file is processed by scripts/decodetree.py
#
+&empty !extern
&s_rrr_shi !extern s rd rn rm shim shty
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
@@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm
+
+# Branches and miscellaneous control
+
+{
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
+
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
+
+ # The canonical nop ends in 0000 0000, but the whole rest
+ # of the space is "reserved hint, behaves as nop".
+ NOP 1111 0011 1010 1111 1000 0000 ---- ----
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (16 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check Richard Henderson
` (50 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 226 ++++++++++++++++++-----------------------
target/arm/a32.decode | 14 +++
target/arm/t32.decode | 40 ++++++--
3 files changed, 142 insertions(+), 138 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 36c815caf3..fa0c048b38 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8362,6 +8362,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a)
return true;
}
+/*
+ * Miscellaneous instructions
+ */
+
+static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a)
+{
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ gen_mrs_banked(s, a->r, a->sysm, a->rd);
+ return true;
+}
+
+static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a)
+{
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ gen_msr_banked(s, a->r, a->sysm, a->rn);
+ return true;
+}
+
+static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a)
+{
+ TCGv_i32 tmp;
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ if (a->r) {
+ if (IS_USER(s)) {
+ gen_illegal_op(s);
+ return true;
+ }
+ tmp = load_cpu_field(spsr);
+ } else {
+ tmp = tcg_temp_new_i32();
+ gen_helper_cpsr_read(tmp, cpu_env);
+ }
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a)
+{
+ TCGv_i32 tmp;
+ uint32_t mask = msr_mask(s, a->mask, a->r);
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ tmp = load_reg(s, a->rn);
+ if (gen_set_psr(s, mask, a->r, tmp)) {
+ gen_illegal_op(s);
+ }
+ return true;
+}
+
+static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
+{
+ TCGv_i32 tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ tmp = tcg_const_i32(a->sysm);
+ gen_helper_v7m_mrs(tmp, cpu_env, tmp);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
+{
+ TCGv_i32 addr, reg;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ addr = tcg_const_i32((a->mask << 10) | a->sysm);
+ reg = load_reg(s, a->rn);
+ gen_helper_v7m_msr(cpu_env, addr, reg);
+ tcg_temp_free_i32(addr);
+ tcg_temp_free_i32(reg);
+ gen_lookup_tb(s);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -8643,46 +8730,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
sh = (insn >> 4) & 0xf;
rm = insn & 0xf;
switch (sh) {
- case 0x0: /* MSR, MRS */
- if (insn & (1 << 9)) {
- /* MSR (banked) and MRS (banked) */
- int sysm = extract32(insn, 16, 4) |
- (extract32(insn, 8, 1) << 4);
- int r = extract32(insn, 22, 1);
-
- if (op1 & 1) {
- /* MSR (banked) */
- gen_msr_banked(s, r, sysm, rm);
- } else {
- /* MRS (banked) */
- int rd = extract32(insn, 12, 4);
-
- gen_mrs_banked(s, r, sysm, rd);
- }
- break;
- }
-
- /* MSR, MRS (for PSRs) */
- if (op1 & 1) {
- /* PSR = reg */
- tmp = load_reg(s, rm);
- i = ((op1 & 2) != 0);
- if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp))
- goto illegal_op;
- } else {
- /* reg = PSR */
- rd = (insn >> 12) & 0xf;
- if (op1 & 2) {
- if (IS_USER(s))
- goto illegal_op;
- tmp = load_cpu_field(spsr);
- } else {
- tmp = tcg_temp_new_i32();
- gen_helper_cpsr_read(tmp, cpu_env);
- }
- store_reg(s, rd, tmp);
- }
- break;
+ case 0x0:
+ /* MSR/MRS (banked/register) */
+ /* All done in decodetree. Illegal ops already signalled. */
+ g_assert_not_reached();
case 0x1:
if (op1 == 1) {
/* branch/exchange thumb (bx). */
@@ -10559,40 +10610,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
} else {
op = (insn >> 20) & 7;
switch (op) {
- case 0: /* msr cpsr. */
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- tmp = load_reg(s, rn);
- /* the constant is the mask and SYSm fields */
- addr = tcg_const_i32(insn & 0xfff);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
- tcg_temp_free_i32(addr);
- tcg_temp_free_i32(tmp);
- gen_lookup_tb(s);
- break;
- }
- /* fall through */
- case 1: /* msr spsr. */
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
-
- if (extract32(insn, 5, 1)) {
- /* MSR (banked) */
- int sysm = extract32(insn, 8, 4) |
- (extract32(insn, 4, 1) << 4);
- int r = op & 1;
-
- gen_msr_banked(s, r, sysm, rm);
- break;
- }
-
- /* MSR (for PSRs) */
- tmp = load_reg(s, rn);
- if (gen_set_psr(s,
- msr_mask(s, (insn >> 8) & 0xf, op == 1),
- op == 1, tmp))
- goto illegal_op;
- break;
+ case 0: /* msr cpsr, in decodetree */
+ case 1: /* msr spsr, in decodetree */
+ goto illegal_op;
case 2: /* cps, nop-hint. */
/* nop hints in decodetree */
/* Implemented as NOP in user mode. */
@@ -10684,61 +10704,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
gen_exception_return(s, tmp);
break;
- case 6: /* MRS */
- if (extract32(insn, 5, 1) &&
- !arm_dc_feature(s, ARM_FEATURE_M)) {
- /* MRS (banked) */
- int sysm = extract32(insn, 16, 4) |
- (extract32(insn, 4, 1) << 4);
-
- gen_mrs_banked(s, 0, sysm, rd);
- break;
- }
-
- if (extract32(insn, 16, 4) != 0xf) {
- goto illegal_op;
- }
- if (!arm_dc_feature(s, ARM_FEATURE_M) &&
- extract32(insn, 0, 8) != 0) {
- goto illegal_op;
- }
-
- /* mrs cpsr */
- tmp = tcg_temp_new_i32();
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- addr = tcg_const_i32(insn & 0xff);
- gen_helper_v7m_mrs(tmp, cpu_env, addr);
- tcg_temp_free_i32(addr);
- } else {
- gen_helper_cpsr_read(tmp, cpu_env);
- }
- store_reg(s, rd, tmp);
- break;
- case 7: /* MRS */
- if (extract32(insn, 5, 1) &&
- !arm_dc_feature(s, ARM_FEATURE_M)) {
- /* MRS (banked) */
- int sysm = extract32(insn, 16, 4) |
- (extract32(insn, 4, 1) << 4);
-
- gen_mrs_banked(s, 1, sysm, rd);
- break;
- }
-
- /* mrs spsr. */
- /* Not accessible in user mode. */
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
-
- if (extract32(insn, 16, 4) != 0xf ||
- extract32(insn, 0, 8) != 0) {
- goto illegal_op;
- }
-
- tmp = load_cpu_field(spsr);
- store_reg(s, rd, tmp);
- break;
+ case 6: /* MRS, in decodetree */
+ case 7: /* MSR, in decodetree */
+ goto illegal_op;
}
}
} else {
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 4cefba6f0e..50449fa8ec 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -29,6 +29,10 @@
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
&rrr rd rn rm
+&msr_reg rn r mask
+&mrs_reg rd r
+&msr_bank rn r sysm
+&mrs_bank rd r sysm
# Data-processing (register)
@@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0
}
MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1
+
+# Miscellaneous instructions
+
+%sysm 8:1 16:4
+
+MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm
+MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm
+
+MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg
+MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index b4f0a9632d..40a2c520c1 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -26,6 +26,10 @@
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
+&msr_reg !extern rn r mask
+&mrs_reg !extern rd r
+&msr_bank !extern rn r sysm
+&mrs_bank !extern rd r sysm
# Data-processing (register-shifted register)
@@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm
# Branches and miscellaneous control
+%msr_sysm 4:1 8:4
+%mrs_sysm 4:1 16:4
+
{
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
+ {
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
- # TODO: Implement SEV, SEVL; may help SMP performance.
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
- # The canonical nop ends in 0000 0000, but the whole rest
- # of the space is "reserved hint, behaves as nop".
- NOP 1111 0011 1010 1111 1000 0000 ---- ----
+ # The canonical nop ends in 0000 0000, but the whole rest
+ # of the space is "reserved hint, behaves as nop".
+ NOP 1111 0011 1010 1111 1000 0000 ---- ----
+ }
+ # Note that the v7m insn overlaps both the normal and banked insn.
+ {
+ MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
+ &mrs_bank sysm=%mrs_sysm
+ MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
+ MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
+ }
+ {
+ MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
+ &msr_bank sysm=%msr_sysm
+ MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
+ MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
+ }
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (17 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
` (49 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 121 +++++++++++++++++++----------------------
target/arm/a32.decode | 9 +++
target/arm/t32.decode | 7 +++
3 files changed, 72 insertions(+), 65 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fa0c048b38..ed7041d0e4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8362,6 +8362,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a)
return true;
}
+/*
+ * Cyclic Redundancy Check
+ */
+
+static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz)
+{
+ TCGv_i32 t1, t2, t3;
+
+ if (!dc_isar_feature(aa32_crc32, s)) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ switch (sz) {
+ case MO_8:
+ gen_uxtb(t2);
+ break;
+ case MO_16:
+ gen_uxth(t2);
+ break;
+ case MO_32:
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ t3 = tcg_const_i32(1 << sz);
+ if (c) {
+ gen_helper_crc32c(t1, t1, t2, t3);
+ } else {
+ gen_helper_crc32(t1, t1, t2, t3);
+ }
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+#define DO_CRC32(NAME, c, sz) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+ { return op_crc32(s, a, c, sz); }
+
+DO_CRC32(CRC32B, false, MO_8)
+DO_CRC32(CRC32H, false, MO_16)
+DO_CRC32(CRC32W, false, MO_32)
+DO_CRC32(CRC32CB, true, MO_8)
+DO_CRC32(CRC32CH, true, MO_16)
+DO_CRC32(CRC32CW, true, MO_32)
+
+#undef DO_CRC32
+
/*
* Miscellaneous instructions
*/
@@ -8774,39 +8825,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
gen_bx(s, tmp);
break;
case 0x4:
- {
- /* crc32/crc32c */
- uint32_t c = extract32(insn, 8, 4);
-
- /* Check this CPU supports ARMv8 CRC instructions.
- * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
- * Bits 8, 10 and 11 should be zero.
- */
- if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) {
- goto illegal_op;
- }
-
- rn = extract32(insn, 16, 4);
- rd = extract32(insn, 12, 4);
-
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- if (op1 == 0) {
- tcg_gen_andi_i32(tmp2, tmp2, 0xff);
- } else if (op1 == 1) {
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
- }
- tmp3 = tcg_const_i32(1 << op1);
- if (c & 0x2) {
- gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
- } else {
- gen_helper_crc32(tmp, tmp, tmp2, tmp3);
- }
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp3);
- store_reg(s, rd, tmp);
- break;
- }
+ /* crc32 */
+ /* All done in decodetree. Illegal ops reach here. */
+ goto illegal_op;
case 0x5:
/* Saturating addition and subtraction. */
/* All done in decodetree. Reach here for illegal ops. */
@@ -10256,16 +10277,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
break;
- case 0x20: /* crc32/crc32c */
+ case 0x20: /* crc32/crc32c, in decodetree */
case 0x21:
case 0x22:
case 0x28:
case 0x29:
case 0x2a:
- if (!dc_isar_feature(aa32_crc32, s)) {
- goto illegal_op;
- }
- break;
+ goto illegal_op;
default:
goto illegal_op;
}
@@ -10294,33 +10312,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0x18: /* clz */
tcg_gen_clzi_i32(tmp, tmp, 32);
break;
- case 0x20:
- case 0x21:
- case 0x22:
- case 0x28:
- case 0x29:
- case 0x2a:
- {
- /* crc32/crc32c */
- uint32_t sz = op & 0x3;
- uint32_t c = op & 0x8;
-
- tmp2 = load_reg(s, rm);
- if (sz == 0) {
- tcg_gen_andi_i32(tmp2, tmp2, 0xff);
- } else if (sz == 1) {
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
- }
- tmp3 = tcg_const_i32(1 << sz);
- if (c) {
- gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
- } else {
- gen_helper_crc32(tmp, tmp, tmp2, tmp3);
- }
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp3);
- break;
- }
default:
g_assert_not_reached();
}
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 50449fa8ec..5751e615cd 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
}
MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1
+# Cyclic Redundancy Check
+
+CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm
+CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm
+CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm
+CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm
+CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm
+CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm
+
# Miscellaneous instructions
%sysm 8:1 16:4
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 40a2c520c1..30971787d4 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm
+CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm
+CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm
+CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm
+CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
+CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
+CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
+
# Branches and miscellaneous control
%msr_sysm 4:1 8:4
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (18 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW Richard Henderson
` (48 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM,
in that it may be executed from user mode as with any other encoding
of SUBS, not as ERET.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 273 +++++++++++++++--------------------------
target/arm/a32.decode | 21 ++++
target/arm/t32.decode | 20 +++
3 files changed, 143 insertions(+), 171 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ed7041d0e4..09310b1c3a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8500,6 +8500,101 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
return true;
}
+static bool trans_BX(DisasContext *s, arg_BX *a)
+{
+ if (!ENABLE_ARCH_4T) {
+ return false;
+ }
+ gen_bx(s, load_reg(s, a->rm));
+ return true;
+}
+
+static bool trans_BXJ(DisasContext *s, arg_BXJ *a)
+{
+ if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ /* Trivial implementation equivalent to bx. */
+ gen_bx(s, load_reg(s, a->rm));
+ return true;
+}
+
+static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_5) {
+ return false;
+ }
+ tmp = load_reg(s, a->rm);
+ tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb);
+ gen_bx(s, tmp);
+ return true;
+}
+
+static bool trans_CLZ(DisasContext *s, arg_CLZ *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_5) {
+ return false;
+ }
+ tmp = load_reg(s, a->rm);
+ tcg_gen_clzi_i32(tmp, tmp, 32);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_ERET(DisasContext *s, arg_ERET *a)
+{
+ TCGv_i32 tmp;
+
+ if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V7VE)) {
+ return false;
+ }
+ if (s->current_el == 2) {
+ /* ERET from Hyp uses ELR_Hyp, not LR */
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, 14);
+ }
+ gen_exception_return(s, tmp);
+ return true;
+}
+
+static bool trans_HLT(DisasContext *s, arg_HLT *a)
+{
+ gen_hlt(s, a->imm);
+ return true;
+}
+
+static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
+{
+ if (!ENABLE_ARCH_5) {
+ return false;
+ }
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
+ return true;
+}
+
+static bool trans_HVC(DisasContext *s, arg_HVC *a)
+{
+ if (!ENABLE_ARCH_7 || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ gen_hvc(s, a->imm);
+ return true;
+}
+
+static bool trans_SMC(DisasContext *s, arg_SMC *a)
+{
+ if (!ENABLE_ARCH_6K || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+ gen_smc(s);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -8777,124 +8872,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
} else if ((insn & 0x0f900000) == 0x01000000
&& (insn & 0x00000090) != 0x00000090) {
/* miscellaneous instructions */
- op1 = (insn >> 21) & 3;
- sh = (insn >> 4) & 0xf;
- rm = insn & 0xf;
- switch (sh) {
- case 0x0:
- /* MSR/MRS (banked/register) */
- /* All done in decodetree. Illegal ops already signalled. */
- g_assert_not_reached();
- case 0x1:
- if (op1 == 1) {
- /* branch/exchange thumb (bx). */
- ARCH(4T);
- tmp = load_reg(s, rm);
- gen_bx(s, tmp);
- } else if (op1 == 3) {
- /* clz */
- ARCH(5);
- rd = (insn >> 12) & 0xf;
- tmp = load_reg(s, rm);
- tcg_gen_clzi_i32(tmp, tmp, 32);
- store_reg(s, rd, tmp);
- } else {
- goto illegal_op;
- }
- break;
- case 0x2:
- if (op1 == 1) {
- ARCH(5J); /* bxj */
- /* Trivial implementation equivalent to bx. */
- tmp = load_reg(s, rm);
- gen_bx(s, tmp);
- } else {
- goto illegal_op;
- }
- break;
- case 0x3:
- if (op1 != 1)
- goto illegal_op;
-
- ARCH(5);
- /* branch link/exchange thumb (blx) */
- tmp = load_reg(s, rm);
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, s->pc);
- store_reg(s, 14, tmp2);
- gen_bx(s, tmp);
- break;
- case 0x4:
- /* crc32 */
- /* All done in decodetree. Illegal ops reach here. */
- goto illegal_op;
- case 0x5:
- /* Saturating addition and subtraction. */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- case 0x6: /* ERET */
- if (op1 != 3) {
- goto illegal_op;
- }
- if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
- goto illegal_op;
- }
- if ((insn & 0x000fff0f) != 0x0000000e) {
- /* UNPREDICTABLE; we choose to UNDEF */
- goto illegal_op;
- }
-
- if (s->current_el == 2) {
- tmp = load_cpu_field(elr_el[2]);
- } else {
- tmp = load_reg(s, 14);
- }
- gen_exception_return(s, tmp);
- break;
- case 7:
- {
- int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
- switch (op1) {
- case 0:
- /* HLT */
- gen_hlt(s, imm16);
- break;
- case 1:
- /* bkpt */
- ARCH(5);
- gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
- break;
- case 2:
- /* Hypervisor call (v7) */
- ARCH(7);
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_hvc(s, imm16);
- break;
- case 3:
- /* Secure monitor call (v6+) */
- ARCH(6K);
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_smc(s);
- break;
- default:
- g_assert_not_reached();
- }
- break;
- }
- case 0x8:
- case 0xa:
- case 0xc:
- case 0xe:
- /* Halfword multiply and multiply accumulate. */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- default:
- goto illegal_op;
- }
+ /* All done in decodetree. Illegal ops reach here. */
+ goto illegal_op;
} else if (((insn & 0x0e000000) == 0 &&
(insn & 0x00000090) != 0x90) ||
((insn & 0x0e000000) == (1 << 25))) {
@@ -10270,13 +10249,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0x08: /* rev */
case 0x09: /* rev16 */
case 0x0b: /* revsh */
- case 0x18: /* clz */
break;
case 0x10: /* sel */
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
goto illegal_op;
}
break;
+ case 0x18: /* clz, in decodetree */
case 0x20: /* crc32/crc32c, in decodetree */
case 0x21:
case 0x22:
@@ -10309,9 +10288,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp3);
tcg_temp_free_i32(tmp2);
break;
- case 0x18: /* clz */
- tcg_gen_clzi_i32(tmp, tmp, 32);
- break;
default:
g_assert_not_reached();
}
@@ -10578,26 +10554,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
if (insn & (1 << 26)) {
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- if (!(insn & (1 << 20))) {
- /* Hypervisor call (v7) */
- int imm16 = extract32(insn, 16, 4) << 12
- | extract32(insn, 0, 12);
- ARCH(7);
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_hvc(s, imm16);
- } else {
- /* Secure monitor call (v6+) */
- ARCH(6K);
- if (IS_USER(s)) {
- goto illegal_op;
- }
- gen_smc(s);
- }
+ /* hvc, smc, in decodetree */
+ goto illegal_op;
} else {
op = (insn >> 20) & 7;
switch (op) {
@@ -10666,35 +10624,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
break;
- case 4: /* bxj */
- /* Trivial implementation equivalent to bx.
- * This instruction doesn't exist at all for M-profile.
- */
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- tmp = load_reg(s, rn);
- gen_bx(s, tmp);
- break;
- case 5: /* Exception return. */
- if (IS_USER(s)) {
- goto illegal_op;
- }
- if (rn != 14 || rd != 15) {
- goto illegal_op;
- }
- if (s->current_el == 2) {
- /* ERET from Hyp uses ELR_Hyp, not LR */
- if (insn & 0xff) {
- goto illegal_op;
- }
- tmp = load_cpu_field(elr_el[2]);
- } else {
- tmp = load_reg(s, rn);
- tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
- }
- gen_exception_return(s, tmp);
- break;
+ case 4: /* bxj, in decodetree */
+ case 5: /* eret, in decodetree */
case 6: /* MRS, in decodetree */
case 7: /* MSR, in decodetree */
goto illegal_op;
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 5751e615cd..32d1833037 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -29,6 +29,9 @@
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
&rrr rd rn rm
+&rr rd rm
+&r rm
+&i imm
&msr_reg rn r mask
&mrs_reg rd r
&msr_bank rn r sysm
@@ -194,9 +197,27 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm
# Miscellaneous instructions
%sysm 8:1 16:4
+%imm16_8_0 8:12 0:4
+
+@rm ---- .... .... .... .... .... .... rm:4 &r
+@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr
+@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0
MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm
MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm
MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg
MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg
+
+BX .... 0001 0010 1111 1111 1111 0001 .... @rm
+BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm
+BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm
+
+CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm
+
+ERET ---- 0001 0110 0000 0000 0000 0110 1110
+
+HLT .... 0001 0000 .... .... .... 0111 .... @i16
+BKPT .... 0001 0010 .... .... .... 0111 .... @i16
+HVC .... 0001 0100 .... .... .... 0111 .... @i16
+SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 30971787d4..abd233180d 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -26,6 +26,9 @@
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
+&rr !extern rd rm
+&r !extern rm
+&i !extern imm
&msr_reg !extern rn r mask
&mrs_reg !extern rd r
&msr_bank !extern rn r sysm
@@ -125,6 +128,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
+@rdm .... .... .... .... .... rd:4 .... rm:4 &rr
{
MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm
@@ -179,10 +183,15 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
+# Ignore Rn, as allowed by constrained unpredictable.
+# This matches the behaviour of the legacy decoder.
+CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
+
# Branches and miscellaneous control
%msr_sysm 4:1 8:4
%mrs_sysm 4:1 16:4
+%imm16_16_0 16:4 0:12
{
{
@@ -211,4 +220,15 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
}
+ BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
+ {
+ # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
+ # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
+ ERET 1111 0011 1101 1110 1000 1111 0000 0000
+ SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
+ &s_rri_rot rot=0 s=1 rd=15 rn=14
+ }
+ SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
+ HVC 1111 0111 1110 .... 1000 .... .... .... \
+ &i imm=%imm16_16_0
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (19 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
` (47 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 24 +++++++++++++-----------
target/arm/a32.decode | 1 +
target/arm/t32.decode | 19 +++++++++++++++++++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 09310b1c3a..d19131d594 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7683,6 +7683,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
* Constant expanders for the decoders.
*/
+static int negate(DisasContext *s, int x)
+{
+ return -x;
+}
+
static int times_2(DisasContext *s, int x)
{
return x * 2;
@@ -8053,6 +8058,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a)
#undef DO_ANY
#undef DO_LOGIC
+static bool trans_ADR(DisasContext *s, arg_ri *a)
+{
+ store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm));
+ return true;
+}
+
/*
* Multiply and multiply accumulate
*/
@@ -10758,17 +10769,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
store_reg(s, rd, tmp);
} else {
- /* Add/sub 12-bit immediate. */
- if (insn & (1 << 23)) {
- imm = -imm;
- }
- tmp = add_reg_for_lit(s, rn, imm);
- if (rn == 13 && rd == 13) {
- /* ADD SP, SP, imm or SUB SP, SP, imm */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
+ /* Add/sub 12-bit immediate, in decodetree */
+ goto illegal_op;
}
}
} else {
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 32d1833037..baae62dea9 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -30,6 +30,7 @@
&rrrr rd rn rm ra
&rrr rd rn rm
&rr rd rm
+&ri rd imm
&r rm
&i imm
&msr_reg rn r mask
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index abd233180d..69e81ef71a 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -27,6 +27,7 @@
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
&rr !extern rd rm
+&ri !extern rd imm
&r !extern rm
&i !extern imm
&msr_reg !extern rn r mask
@@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
+# Data processing (plain binary immediate)
+
+%imm12_26_12_0 26:1 12:3 0:8
+%neg12_26_12_0 26:1 12:3 0:8 !function=negate
+@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \
+ &s_rri_rot imm=%imm12_26_12_0 rot=0 s=0
+
+{
+ ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \
+ &ri imm=%imm12_26_12_0
+ ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12
+}
+{
+ ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \
+ &ri imm=%neg12_26_12_0
+ SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
+}
+
# Multiply and multiply accumulate
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (20 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives Richard Henderson
` (46 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 793 ++++++++++++++++++-----------------------
target/arm/a32.decode | 120 +++++++
target/arm/t32.decode | 141 ++++++++
3 files changed, 611 insertions(+), 443 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d19131d594..73cb624ebd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1293,62 +1293,6 @@ static inline void gen_hlt(DisasContext *s, int imm)
gen_illegal_op(s);
}
-static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
- TCGv_i32 var)
-{
- int val, rm, shift, shiftop;
- TCGv_i32 offset;
-
- if (!(insn & (1 << 25))) {
- /* immediate */
- val = insn & 0xfff;
- if (!(insn & (1 << 23)))
- val = -val;
- if (val != 0)
- tcg_gen_addi_i32(var, var, val);
- } else {
- /* shift/register */
- rm = (insn) & 0xf;
- shift = (insn >> 7) & 0x1f;
- shiftop = (insn >> 5) & 3;
- offset = load_reg(s, rm);
- gen_arm_shift_im(offset, shiftop, shift, 0);
- if (!(insn & (1 << 23)))
- tcg_gen_sub_i32(var, var, offset);
- else
- tcg_gen_add_i32(var, var, offset);
- tcg_temp_free_i32(offset);
- }
-}
-
-static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
- int extra, TCGv_i32 var)
-{
- int val, rm;
- TCGv_i32 offset;
-
- if (insn & (1 << 22)) {
- /* immediate */
- val = (insn & 0xf) | ((insn >> 4) & 0xf0);
- if (!(insn & (1 << 23)))
- val = -val;
- val += extra;
- if (val != 0)
- tcg_gen_addi_i32(var, var, val);
- } else {
- /* register */
- if (extra)
- tcg_gen_addi_i32(var, var, extra);
- rm = (insn) & 0xf;
- offset = load_reg(s, rm);
- if (!(insn & (1 << 23)))
- tcg_gen_sub_i32(var, var, offset);
- else
- tcg_gen_add_i32(var, var, offset);
- tcg_temp_free_i32(offset);
- }
-}
-
static TCGv_ptr get_fpstatus_ptr(int neon)
{
TCGv_ptr statusptr = tcg_temp_new_ptr();
@@ -7693,6 +7637,11 @@ static int times_2(DisasContext *s, int x)
return x * 2;
}
+static int times_4(DisasContext *s, int x)
+{
+ return x * 4;
+}
+
/* Return only the rotation part of T32ExpandImm. */
static int t32_expandimm_rot(DisasContext *s, int x)
{
@@ -8606,6 +8555,341 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a)
return true;
}
+/*
+ * Load/store register index
+ */
+
+static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
+{
+ ISSInfo ret;
+
+ /* ISS not valid if writeback */
+ if (p & !w) {
+ ret = rd;
+ } else {
+ ret = ISSInvalid;
+ }
+ return ret;
+}
+
+static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
+{
+ TCGv_i32 addr = load_reg(s, a->rn);
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ if (a->p) {
+ TCGv_i32 ofs = load_reg(s, a->rm);
+ gen_arm_shift_im(ofs, a->shtype, a->shimm, 0);
+ if (a->u) {
+ tcg_gen_add_i32(addr, addr, ofs);
+ } else {
+ tcg_gen_sub_i32(addr, addr, ofs);
+ }
+ tcg_temp_free_i32(ofs);
+ }
+ return addr;
+}
+
+static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
+ TCGv_i32 addr, int address_offset)
+{
+ if (!a->p) {
+ TCGv_i32 ofs = load_reg(s, a->rm);
+ gen_arm_shift_im(ofs, a->shtype, a->shimm, 0);
+ if (a->u) {
+ tcg_gen_add_i32(addr, addr, ofs);
+ } else {
+ tcg_gen_sub_i32(addr, addr, ofs);
+ }
+ tcg_temp_free_i32(ofs);
+ } else if (!a->w) {
+ tcg_temp_free_i32(addr);
+ return;
+ }
+ tcg_gen_addi_i32(addr, addr, address_offset);
+ store_reg(s, a->rn, addr);
+}
+
+static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
+ TCGMemOp mop, int mem_idx)
+{
+ ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w);
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_rr_pre(s, a);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ disas_set_da_iss(s, mop, issinfo);
+
+ /*
+ * Perform base writeback before the loaded value to
+ * ensure correct behavior with overlapping index registers.
+ */
+ op_addr_rr_post(s, a, addr, 0);
+ store_reg_from_load(s, a->rt, tmp);
+ return true;
+}
+
+static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
+ TCGMemOp mop, int mem_idx)
+{
+ ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite;
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_rr_pre(s, a);
+
+ tmp = load_reg(s, a->rt);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ disas_set_da_iss(s, mop, issinfo);
+ tcg_temp_free_i32(tmp);
+
+ op_addr_rr_post(s, a, addr, 0);
+ return true;
+}
+
+static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
+{
+ int mem_idx = get_mem_index(s);
+ TCGv_i32 addr, tmp;
+
+ if (!ENABLE_ARCH_5TE || (a->rt & 1)) {
+ return false;
+ }
+ addr = op_addr_rr_pre(s, a);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ store_reg(s, a->rt, tmp);
+
+ tcg_gen_addi_i32(addr, addr, 4);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ store_reg(s, a->rt + 1, tmp);
+
+ /* LDRD w/ base writeback is undefined if the registers overlap. */
+ op_addr_rr_post(s, a, addr, -4);
+ return true;
+}
+
+static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
+{
+ int mem_idx = get_mem_index(s);
+ TCGv_i32 addr, tmp;
+
+ if (!ENABLE_ARCH_5TE || (a->rt & 1)) {
+ return false;
+ }
+ addr = op_addr_rr_pre(s, a);
+
+ tmp = load_reg(s, a->rt);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ tcg_temp_free_i32(tmp);
+
+ tcg_gen_addi_i32(addr, addr, 4);
+
+ tmp = load_reg(s, a->rt + 1);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ tcg_temp_free_i32(tmp);
+
+ op_addr_rr_post(s, a, addr, -4);
+ return true;
+}
+
+/*
+ * Load/store immediate index
+ */
+
+static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
+{
+ int ofs = a->imm;
+
+ if (!a->u) {
+ ofs = -ofs;
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ /*
+ * Stackcheck. Here we know 'addr' is the current SP;
+ * U is set if we're moving SP up, else down. It is
+ * UNKNOWN whether the limit check triggers when SP starts
+ * below the limit and ends up above it; we chose to do so.
+ */
+ if (!a->u) {
+ TCGv_i32 newsp = tcg_temp_new_i32();
+ tcg_gen_addi_i32(newsp, cpu_R[13], ofs);
+ gen_helper_v8m_stackcheck(cpu_env, newsp);
+ tcg_temp_free_i32(newsp);
+ } else {
+ gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]);
+ }
+ }
+
+ return add_reg_for_lit(s, a->rn, a->p ? ofs : 0);
+}
+
+static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a,
+ TCGv_i32 addr, int address_offset)
+{
+ if (!a->p) {
+ address_offset += (a->u ? a->imm : -a->imm);
+ } else if (!a->w) {
+ tcg_temp_free_i32(addr);
+ return;
+ }
+ tcg_gen_addi_i32(addr, addr, address_offset);
+ store_reg(s, a->rn, addr);
+}
+
+static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
+ TCGMemOp mop, int mem_idx)
+{
+ ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w);
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_ri_pre(s, a);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ disas_set_da_iss(s, mop, issinfo);
+
+ /*
+ * Perform base writeback before the loaded value to
+ * ensure coriect behavior with overlapping index registers.
+ */
+ op_addr_ri_post(s, a, addr, 0);
+ store_reg_from_load(s, a->rt, tmp);
+ return true;
+}
+
+static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
+ TCGMemOp mop, int mem_idx)
+{
+ ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite;
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_ri_pre(s, a);
+
+ tmp = load_reg(s, a->rt);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ disas_set_da_iss(s, mop, issinfo);
+ tcg_temp_free_i32(tmp);
+
+ op_addr_ri_post(s, a, addr, 0);
+ return true;
+}
+
+static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
+{
+ int mem_idx = get_mem_index(s);
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_ri_pre(s, a);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ store_reg(s, a->rt, tmp);
+
+ tcg_gen_addi_i32(addr, addr, 4);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ store_reg(s, rt2, tmp);
+
+ /* LDRD w/ base writeback is undefined if the registers overlap. */
+ op_addr_ri_post(s, a, addr, -4);
+ return true;
+}
+
+static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a)
+{
+ if (!ENABLE_ARCH_5TE || (a->rt & 1)) {
+ return false;
+ }
+ return op_ldrd_ri(s, a, a->rt + 1);
+}
+
+static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
+{
+ arg_ldst_ri b = {
+ .u = a->u, .w = a->w, .p = a->p,
+ .rn = a->rn, .rt = a->rt, .imm = a->imm
+ };
+ return op_ldrd_ri(s, &b, a->rt2);
+}
+
+static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
+{
+ int mem_idx = get_mem_index(s);
+ TCGv_i32 addr, tmp;
+
+ addr = op_addr_ri_pre(s, a);
+
+ tmp = load_reg(s, a->rt);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ tcg_temp_free_i32(tmp);
+
+ tcg_gen_addi_i32(addr, addr, 4);
+
+ tmp = load_reg(s, rt2);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ tcg_temp_free_i32(tmp);
+
+ op_addr_ri_post(s, a, addr, -4);
+ return true;
+}
+
+static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a)
+{
+ if (!ENABLE_ARCH_5TE || (a->rt & 1)) {
+ return false;
+ }
+ return op_strd_ri(s, a, a->rt + 1);
+}
+
+static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
+{
+ arg_ldst_ri b = {
+ .u = a->u, .w = a->w, .p = a->p,
+ .rn = a->rn, .rt = a->rt, .imm = a->imm
+ };
+ return op_strd_ri(s, &b, a->rt2);
+}
+
+#define DO_LDST(NAME, WHICH, MEMOP) \
+static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \
+{ \
+ return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \
+} \
+static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \
+{ \
+ return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \
+} \
+static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \
+{ \
+ return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \
+} \
+static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \
+{ \
+ return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \
+}
+
+DO_LDST(LDR, load, MO_UL)
+DO_LDST(LDRB, load, MO_UB)
+DO_LDST(LDRH, load, MO_UW)
+DO_LDST(LDRSB, load, MO_SB)
+DO_LDST(LDRSH, load, MO_SW)
+
+DO_LDST(STR, store, MO_UL)
+DO_LDST(STRB, store, MO_UB)
+DO_LDST(STRH, store, MO_UW)
+
+#undef DO_LDST
+
/*
* Legacy decoder.
*/
@@ -9060,100 +9344,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
}
} else {
- int address_offset;
- bool load = insn & (1 << 20);
- bool wbit = insn & (1 << 21);
- bool pbit = insn & (1 << 24);
- bool doubleword = false;
- ISSInfo issinfo;
-
- /* Misc load/store */
- rn = (insn >> 16) & 0xf;
- rd = (insn >> 12) & 0xf;
-
- /* ISS not valid if writeback */
- issinfo = (pbit & !wbit) ? rd : ISSInvalid;
-
- if (!load && (sh & 2)) {
- /* doubleword */
- ARCH(5TE);
- if (rd & 1) {
- /* UNPREDICTABLE; we choose to UNDEF */
- goto illegal_op;
- }
- load = (sh & 1) == 0;
- doubleword = true;
- }
-
- addr = load_reg(s, rn);
- if (pbit) {
- gen_add_datah_offset(s, insn, 0, addr);
- }
- address_offset = 0;
-
- if (doubleword) {
- if (!load) {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- tcg_gen_addi_i32(addr, addr, 4);
- tmp = load_reg(s, rd + 1);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- } else {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- store_reg(s, rd, tmp);
- tcg_gen_addi_i32(addr, addr, 4);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- rd++;
- }
- address_offset = -4;
- } else if (load) {
- /* load */
- tmp = tcg_temp_new_i32();
- switch (sh) {
- case 1:
- gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
- issinfo);
- break;
- case 2:
- gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
- issinfo);
- break;
- default:
- case 3:
- gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
- issinfo);
- break;
- }
- } else {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
- tcg_temp_free_i32(tmp);
- }
- /* Perform base writeback before the loaded value to
- ensure correct behavior with overlapping index registers.
- ldrd with base writeback is undefined if the
- destination and index registers overlap. */
- if (!pbit) {
- gen_add_datah_offset(s, insn, address_offset, addr);
- store_reg(s, rn, addr);
- } else if (wbit) {
- if (address_offset)
- tcg_gen_addi_i32(addr, addr, address_offset);
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- if (load) {
- /* Complete the load. */
- store_reg(s, rd, tmp);
- }
+ /* Extra load/store (register) instructions */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
}
break;
case 0x4:
@@ -9461,58 +9654,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
break;
}
do_ldst:
- /* Check for undefined extension instructions
- * per the ARM Bible IE:
- * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
- */
- sh = (0xf << 20) | (0xf << 4);
- if (op1 == 0x7 && ((insn & sh) == sh))
- {
- goto illegal_op;
- }
- /* load/store byte/word */
- rn = (insn >> 16) & 0xf;
- rd = (insn >> 12) & 0xf;
- tmp2 = load_reg(s, rn);
- if ((insn & 0x01200000) == 0x00200000) {
- /* ldrt/strt */
- i = get_a32_user_mem_index(s);
- } else {
- i = get_mem_index(s);
- }
- if (insn & (1 << 24))
- gen_add_data_offset(s, insn, tmp2);
- if (insn & (1 << 20)) {
- /* load */
- tmp = tcg_temp_new_i32();
- if (insn & (1 << 22)) {
- gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
- } else {
- gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
- }
- } else {
- /* store */
- tmp = load_reg(s, rd);
- if (insn & (1 << 22)) {
- gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
- } else {
- gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
- }
- tcg_temp_free_i32(tmp);
- }
- if (!(insn & (1 << 24))) {
- gen_add_data_offset(s, insn, tmp2);
- store_reg(s, rn, tmp2);
- } else if (insn & (1 << 21)) {
- store_reg(s, rn, tmp2);
- } else {
- tcg_temp_free_i32(tmp2);
- }
- if (insn & (1 << 20)) {
- /* Complete the load. */
- store_reg_from_load(s, rd, tmp);
- }
- break;
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
case 0x08:
case 0x09:
{
@@ -9814,75 +9957,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
s->condexec_mask = 0;
}
} else if (insn & 0x01200000) {
- /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
- * - load/store dual (post-indexed)
- * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
- * - load/store dual (literal and immediate)
- * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
- * - load/store dual (pre-indexed)
- */
- bool wback = extract32(insn, 21, 1);
-
- if (rn == 15 && (insn & (1 << 21))) {
- /* UNPREDICTABLE */
- goto illegal_op;
- }
-
- addr = add_reg_for_lit(s, rn, 0);
- offset = (insn & 0xff) * 4;
- if ((insn & (1 << 23)) == 0) {
- offset = -offset;
- }
-
- if (s->v8m_stackcheck && rn == 13 && wback) {
- /*
- * Here 'addr' is the current SP; if offset is +ve we're
- * moving SP up, else down. It is UNKNOWN whether the limit
- * check triggers when SP starts below the limit and ends
- * up above it; check whichever of the current and final
- * SP is lower, so QEMU will trigger in that situation.
- */
- if ((int32_t)offset < 0) {
- TCGv_i32 newsp = tcg_temp_new_i32();
-
- tcg_gen_addi_i32(newsp, addr, offset);
- gen_helper_v8m_stackcheck(cpu_env, newsp);
- tcg_temp_free_i32(newsp);
- } else {
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
- }
-
- if (insn & (1 << 24)) {
- tcg_gen_addi_i32(addr, addr, offset);
- offset = 0;
- }
- if (insn & (1 << 20)) {
- /* ldrd */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- store_reg(s, rs, tmp);
- tcg_gen_addi_i32(addr, addr, 4);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- store_reg(s, rd, tmp);
- } else {
- /* strd */
- tmp = load_reg(s, rs);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- tcg_gen_addi_i32(addr, addr, 4);
- tmp = load_reg(s, rd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- if (wback) {
- /* Base writeback. */
- tcg_gen_addi_i32(addr, addr, offset - 4);
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
+ /* load/store dual, in decodetree */
+ goto illegal_op;
} else if ((insn & (1 << 23)) == 0) {
/* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx
* - load/store exclusive word
@@ -10780,184 +10856,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
break;
- case 12: /* Load/store single data item. */
- {
- int postinc = 0;
- int writeback = 0;
- int memidx;
- ISSInfo issinfo;
-
+ case 12:
if ((insn & 0x01100000) == 0x01000000) {
if (disas_neon_ls_insn(s, insn)) {
goto illegal_op;
}
break;
}
- op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
- if (rs == 15) {
- if (!(insn & (1 << 20))) {
- goto illegal_op;
- }
- if (op != 2) {
- /* Byte or halfword load space with dest == r15 : memory hints.
- * Catch them early so we don't emit pointless addressing code.
- * This space is a mix of:
- * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
- * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
- * cores)
- * unallocated hints, which must be treated as NOPs
- * UNPREDICTABLE space, which we NOP or UNDEF depending on
- * which is easiest for the decoding logic
- * Some space which must UNDEF
- */
- int op1 = (insn >> 23) & 3;
- int op2 = (insn >> 6) & 0x3f;
- if (op & 2) {
- goto illegal_op;
- }
- if (rn == 15) {
- /* UNPREDICTABLE, unallocated hint or
- * PLD/PLDW/PLI (literal)
- */
- return;
- }
- if (op1 & 1) {
- return; /* PLD/PLDW/PLI or unallocated hint */
- }
- if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
- return; /* PLD/PLDW/PLI or unallocated hint */
- }
- /* UNDEF space, or an UNPREDICTABLE */
- goto illegal_op;
- }
- }
- memidx = get_mem_index(s);
- imm = insn & 0xfff;
- if (insn & (1 << 23)) {
- /* PC relative or Positive offset. */
- addr = add_reg_for_lit(s, rn, imm);
- } else if (rn == 15) {
- /* PC relative with negative offset. */
- addr = add_reg_for_lit(s, rn, -imm);
- } else {
- addr = load_reg(s, rn);
- imm = insn & 0xff;
- switch ((insn >> 8) & 0xf) {
- case 0x0: /* Shifted Register. */
- shift = (insn >> 4) & 0xf;
- if (shift > 3) {
- tcg_temp_free_i32(addr);
- goto illegal_op;
- }
- tmp = load_reg(s, rm);
- tcg_gen_shli_i32(tmp, tmp, shift);
- tcg_gen_add_i32(addr, addr, tmp);
- tcg_temp_free_i32(tmp);
- break;
- case 0xc: /* Negative offset. */
- tcg_gen_addi_i32(addr, addr, -imm);
- break;
- case 0xe: /* User privilege. */
- tcg_gen_addi_i32(addr, addr, imm);
- memidx = get_a32_user_mem_index(s);
- break;
- case 0x9: /* Post-decrement. */
- imm = -imm;
- /* Fall through. */
- case 0xb: /* Post-increment. */
- postinc = 1;
- writeback = 1;
- break;
- case 0xd: /* Pre-decrement. */
- imm = -imm;
- /* Fall through. */
- case 0xf: /* Pre-increment. */
- writeback = 1;
- break;
- default:
- tcg_temp_free_i32(addr);
- goto illegal_op;
- }
- }
-
- issinfo = writeback ? ISSInvalid : rs;
-
- if (s->v8m_stackcheck && rn == 13 && writeback) {
- /*
- * Stackcheck. Here we know 'addr' is the current SP;
- * if imm is +ve we're moving SP up, else down. It is
- * UNKNOWN whether the limit check triggers when SP starts
- * below the limit and ends up above it; we chose to do so.
- */
- if ((int32_t)imm < 0) {
- TCGv_i32 newsp = tcg_temp_new_i32();
-
- tcg_gen_addi_i32(newsp, addr, imm);
- gen_helper_v8m_stackcheck(cpu_env, newsp);
- tcg_temp_free_i32(newsp);
- } else {
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
- }
-
- if (writeback && !postinc) {
- tcg_gen_addi_i32(addr, addr, imm);
- }
-
- if (insn & (1 << 20)) {
- /* Load. */
- tmp = tcg_temp_new_i32();
- switch (op) {
- case 0:
- gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 4:
- gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 1:
- gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 5:
- gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 2:
- gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
- break;
- default:
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(addr);
- goto illegal_op;
- }
- store_reg_from_load(s, rs, tmp);
- } else {
- /* Store. */
- tmp = load_reg(s, rs);
- switch (op) {
- case 0:
- gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 1:
- gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
- break;
- case 2:
- gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
- break;
- default:
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(addr);
- goto illegal_op;
- }
- tcg_temp_free_i32(tmp);
- }
- if (postinc)
- tcg_gen_addi_i32(addr, addr, imm);
- if (writeback) {
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- }
- break;
+ /* Load/store single data item, in decodetree */
+ goto illegal_op;
default:
goto illegal_op;
}
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index baae62dea9..9789042ca0 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -37,6 +37,8 @@
&mrs_reg rd r
&msr_bank rn r sysm
&mrs_bank rd r sysm
+&ldst_rr p w u rn rt rm shimm shtype
+&ldst_ri p w u rn rt imm
# Data-processing (register)
@@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .... @i16
BKPT .... 0001 0010 .... .... .... 0111 .... @i16
HVC .... 0001 0100 .... .... .... 0111 .... @i16
SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i
+
+# Load/Store Dual, Half, Signed Byte (register)
+
+@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \
+ &ldst_rr p=1 shimm=0 shtype=0
+@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \
+ &ldst_rr p=0 w=0 shimm=0 shtype=0
+
+STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0
+STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w
+
+LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0
+LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w
+
+STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0
+STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w
+
+LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0
+LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w
+
+LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0
+LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w
+
+LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0
+LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w
+
+# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding,
+# and act as normal post-indexed (P=0, W=0).
+@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \
+ &ldst_rr p=0 w=0 shimm=0 shtype=0
+
+STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1
+LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1
+LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1
+LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1
+
+# Load/Store word and unsigned byte (register)
+
+@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
+ &ldst_rr p=1
+@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
+ &ldst_rr p=0 w=0
+
+STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0
+STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w
+STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0
+STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w
+
+LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0
+LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w
+LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0
+LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w
+
+@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
+ &ldst_rr p=0 w=0
+
+STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1
+STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1
+LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1
+LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1
+
+# Load/Store Dual, Half, Signed Byte (immediate)
+
+%imm8s_8_0 8:4 0:4
+@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \
+ &ldst_ri imm=%imm8s_8_0 p=1
+@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \
+ &ldst_ri imm=%imm8s_8_0 p=0 w=0
+
+STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0
+STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w
+
+LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0
+LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w
+
+STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0
+STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w
+
+LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0
+LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w
+
+LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0
+LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w
+
+LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0
+LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w
+
+# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding,
+# and act as normal post-indexed (P=0, W=0).
+@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \
+ &ldst_ri imm=%imm8s_8_0 p=0 w=0
+
+STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0w1
+LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0w1
+LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0w1
+LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0w1
+
+# Load/Store word and unsigned byte (immediate)
+
+@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p=1
+@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0
+
+STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p1w
+STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_pw0
+STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p1w
+STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_pw0
+
+LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p1w
+LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_pw0
+LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p1w
+LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_pw0
+
+@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0
+
+STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1
+STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1
+LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1
+LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 69e81ef71a..0d379ed0d9 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -34,6 +34,8 @@
&mrs_reg !extern rd r
&msr_bank !extern rn r sysm
&mrs_bank !extern rd r sysm
+&ldst_rr !extern p w u rn rt rm shimm shtype
+&ldst_ri !extern p w u rn rt imm
# Data-processing (register-shifted register)
@@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
HVC 1111 0111 1110 .... 1000 .... .... .... \
&i imm=%imm16_16_0
}
+
+# Load/store (register, immediate, literal)
+
+@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \
+ &ldst_rr p=1 w=0 u=1 shtype=0
+@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \
+ &ldst_ri w=1
+@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \
+ &ldst_ri p=1 w=0 u=0
+@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \
+ &ldst_ri p=1 w=0 u=1
+@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \
+ &ldst_ri p=1 w=0 u=1
+@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \
+ &ldst_ri p=1 w=0 rn=15
+
+STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr
+STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx
+STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg
+STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp
+STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos
+
+STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr
+STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx
+STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg
+STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp
+STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos
+
+STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr
+STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx
+STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg
+STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp
+STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos
+
+# Note that Load, unsigned (literal) overlaps all other load encodings.
+{
+ {
+ NOP 1111 1000 -001 1111 1111 ------------ # PLD
+ LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit
+ }
+ {
+ NOP 1111 1000 1001 ---- 1111 ------------ # PLD
+ LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos
+ }
+ LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx
+ {
+ NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD
+ LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg
+ }
+ LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp
+ {
+ NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD
+ LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr
+ }
+}
+{
+ {
+ NOP 1111 1000 -011 1111 1111 ------------ # PLD
+ LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit
+ }
+ {
+ NOP 1111 1000 1011 ---- 1111 ------------ # PLDW
+ LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos
+ }
+ LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx
+ {
+ NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW
+ LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg
+ }
+ LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp
+ {
+ NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW
+ LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr
+ }
+}
+{
+ LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit
+ LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos
+ LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx
+ LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg
+ LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp
+ LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr
+}
+# NOPs here are PLI.
+{
+ {
+ NOP 1111 1001 -001 1111 1111 ------------
+ LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit
+ }
+ {
+ NOP 1111 1001 1001 ---- 1111 ------------
+ LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos
+ }
+ LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx
+ {
+ NOP 1111 1001 0001 ---- 1111 1100 --------
+ LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg
+ }
+ LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp
+ {
+ NOP 1111 1001 0001 ---- 1111 000000 -- ----
+ LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr
+ }
+}
+# NOPs here are unallocated memory hints, treated as NOP.
+{
+ {
+ NOP 1111 1001 -011 1111 1111 ------------
+ LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit
+ }
+ {
+ NOP 1111 1001 1011 ---- 1111 ------------
+ LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos
+ }
+ LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx
+ {
+ NOP 1111 1001 0011 ---- 1111 1100 --------
+ LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg
+ }
+ LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp
+ {
+ NOP 1111 1001 0011 ---- 1111 000000 -- ----
+ LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr
+ }
+}
+
+%imm8x4 0:8 !function=times_4
+&ldst_ri2 p w u rn rt rt2 imm
+@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \
+ &ldst_ri2 imm=%imm8x4
+
+STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=1 p=0
+LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=1 p=0
+
+STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1
+LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
+
+STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
+LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (21 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
` (45 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 560 ++++++++++++++++++++++-------------------
target/arm/a32.decode | 48 ++++
target/arm/t32.decode | 46 ++++
3 files changed, 396 insertions(+), 258 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 73cb624ebd..74e54b7efb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8890,6 +8890,302 @@ DO_LDST(STRH, store, MO_UW)
#undef DO_LDST
+/*
+ * Synchronization primitives
+ */
+
+static bool op_swp(DisasContext *s, arg_SWP *a, TCGMemOp opc)
+{
+ TCGv_i32 addr, tmp;
+ TCGv taddr;
+
+ opc |= s->be_data;
+ addr = load_reg(s, a->rn);
+ taddr = gen_aa32_addr(s, addr, opc);
+ tcg_temp_free_i32(addr);
+
+ tmp = load_reg(s, a->rt2);
+ tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc);
+ tcg_temp_free(taddr);
+
+ store_reg(s, a->rt, tmp);
+ return true;
+}
+
+static bool trans_SWP(DisasContext *s, arg_SWP *a)
+{
+ return op_swp(s, a, MO_UL | MO_ALIGN);
+}
+
+static bool trans_SWPB(DisasContext *s, arg_SWP *a)
+{
+ return op_swp(s, a, MO_UB);
+}
+
+/*
+ * Load/Store Exclusive and Load-Acquire/Store-Release
+ */
+
+static bool op_strex(DisasContext *s, arg_STREX *a, TCGMemOp mop, bool rel)
+{
+ TCGv_i32 addr;
+
+ if (rel) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+
+ addr = tcg_temp_local_new_i32();
+ load_reg_var(s, addr, a->rn);
+ tcg_gen_addi_i32(addr, addr, a->imm);
+
+ gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop);
+ tcg_temp_free_i32(addr);
+ return true;
+}
+
+static bool trans_STREX(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ return op_strex(s, a, MO_32, false);
+}
+
+static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_6K || (a->rt & 1)) {
+ return false;
+ }
+ a->rt2 = a->rt + 1;
+ return op_strex(s, a, MO_64, false);
+}
+
+static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a)
+{
+ return op_strex(s, a, MO_64, false);
+}
+
+static bool trans_STREXB(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ return op_strex(s, a, MO_8, false);
+}
+
+static bool trans_STREXH(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ return op_strex(s, a, MO_16, false);
+}
+
+static bool trans_STLEX(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_strex(s, a, MO_32, true);
+}
+
+static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_8 || (a->rt & 1)) {
+ return false;
+ }
+ a->rt2 = a->rt + 1;
+ return op_strex(s, a, MO_64, true);
+}
+
+static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_strex(s, a, MO_64, true);
+}
+
+static bool trans_STLEXB(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_strex(s, a, MO_8, true);
+}
+
+static bool trans_STLEXH(DisasContext *s, arg_STREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_strex(s, a, MO_16, true);
+}
+
+static bool op_stl(DisasContext *s, arg_STL *a, TCGMemOp mop)
+{
+ TCGv_i32 addr, tmp;
+
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ addr = load_reg(s, a->rn);
+
+ tmp = load_reg(s, a->rt);
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
+ disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(addr);
+ return true;
+}
+
+static bool trans_STL(DisasContext *s, arg_STL *a)
+{
+ return op_stl(s, a, MO_UL);
+}
+
+static bool trans_STLB(DisasContext *s, arg_STL *a)
+{
+ return op_stl(s, a, MO_UB);
+}
+
+static bool trans_STLH(DisasContext *s, arg_STL *a)
+{
+ return op_stl(s, a, MO_UW);
+}
+
+static bool op_ldrex(DisasContext *s, arg_LDREX *a, TCGMemOp mop, bool acq)
+{
+ TCGv_i32 addr;
+
+ addr = tcg_temp_local_new_i32();
+ load_reg_var(s, addr, a->rn);
+ tcg_gen_addi_i32(addr, addr, a->imm);
+
+ gen_load_exclusive(s, a->rt, a->rt2, addr, mop);
+ tcg_temp_free_i32(addr);
+
+ if (acq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ return true;
+}
+
+static bool trans_LDREX(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_32, false);
+}
+
+static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_6K || (a->rt & 1)) {
+ return false;
+ }
+ a->rt2 = a->rt + 1;
+ return op_ldrex(s, a, MO_64, false);
+}
+
+static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a)
+{
+ return op_ldrex(s, a, MO_64, false);
+}
+
+static bool trans_LDREXB(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_8, false);
+}
+
+static bool trans_LDREXH(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_16, false);
+}
+
+static bool trans_LDAEX(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_32, true);
+}
+
+static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_8 || (a->rt & 1)) {
+ return false;
+ }
+ a->rt2 = a->rt + 1;
+ return op_ldrex(s, a, MO_64, true);
+}
+
+static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_64, true);
+}
+
+static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_8, true);
+}
+
+static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a)
+{
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ return op_ldrex(s, a, MO_16, true);
+}
+
+static bool op_lda(DisasContext *s, arg_LDA *a, TCGMemOp mop)
+{
+ TCGv_i32 addr, tmp;
+
+ if (!ENABLE_ARCH_8) {
+ return false;
+ }
+ addr = load_reg(s, a->rn);
+
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
+ disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);
+ tcg_temp_free_i32(addr);
+
+ store_reg(s, a->rt, tmp);
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ return true;
+}
+
+static bool trans_LDA(DisasContext *s, arg_LDA *a)
+{
+ return op_lda(s, a, MO_UL);
+}
+
+static bool trans_LDAB(DisasContext *s, arg_LDA *a)
+{
+ return op_lda(s, a, MO_UB);
+}
+
+static bool trans_LDAH(DisasContext *s, arg_LDA *a)
+{
+ return op_lda(s, a, MO_UW);
+}
+
/*
* Legacy decoder.
*/
@@ -9182,172 +9478,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0x0:
case 0x1:
/* multiplies, extra load/stores */
- sh = (insn >> 5) & 3;
- if (sh == 0) {
- if (op1 == 0x0) {
- /* Multiply and multiply accumulate. */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- } else {
- rn = (insn >> 16) & 0xf;
- rd = (insn >> 12) & 0xf;
- if (insn & (1 << 23)) {
- /* load/store exclusive */
- bool is_ld = extract32(insn, 20, 1);
- bool is_lasr = !extract32(insn, 8, 1);
- int op2 = (insn >> 8) & 3;
- op1 = (insn >> 21) & 0x3;
-
- switch (op2) {
- case 0: /* lda/stl */
- if (op1 == 1) {
- goto illegal_op;
- }
- ARCH(8);
- break;
- case 1: /* reserved */
- goto illegal_op;
- case 2: /* ldaex/stlex */
- ARCH(8);
- break;
- case 3: /* ldrex/strex */
- if (op1) {
- ARCH(6K);
- } else {
- ARCH(6);
- }
- break;
- }
-
- addr = tcg_temp_local_new_i32();
- load_reg_var(s, addr, rn);
-
- if (is_lasr && !is_ld) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
-
- if (op2 == 0) {
- if (is_ld) {
- tmp = tcg_temp_new_i32();
- switch (op1) {
- case 0: /* lda */
- gen_aa32_ld32u_iss(s, tmp, addr,
- get_mem_index(s),
- rd | ISSIsAcqRel);
- break;
- case 2: /* ldab */
- gen_aa32_ld8u_iss(s, tmp, addr,
- get_mem_index(s),
- rd | ISSIsAcqRel);
- break;
- case 3: /* ldah */
- gen_aa32_ld16u_iss(s, tmp, addr,
- get_mem_index(s),
- rd | ISSIsAcqRel);
- break;
- default:
- abort();
- }
- store_reg(s, rd, tmp);
- } else {
- rm = insn & 0xf;
- tmp = load_reg(s, rm);
- switch (op1) {
- case 0: /* stl */
- gen_aa32_st32_iss(s, tmp, addr,
- get_mem_index(s),
- rm | ISSIsAcqRel);
- break;
- case 2: /* stlb */
- gen_aa32_st8_iss(s, tmp, addr,
- get_mem_index(s),
- rm | ISSIsAcqRel);
- break;
- case 3: /* stlh */
- gen_aa32_st16_iss(s, tmp, addr,
- get_mem_index(s),
- rm | ISSIsAcqRel);
- break;
- default:
- abort();
- }
- tcg_temp_free_i32(tmp);
- }
- } else if (is_ld) {
- switch (op1) {
- case 0: /* ldrex */
- gen_load_exclusive(s, rd, 15, addr, 2);
- break;
- case 1: /* ldrexd */
- gen_load_exclusive(s, rd, rd + 1, addr, 3);
- break;
- case 2: /* ldrexb */
- gen_load_exclusive(s, rd, 15, addr, 0);
- break;
- case 3: /* ldrexh */
- gen_load_exclusive(s, rd, 15, addr, 1);
- break;
- default:
- abort();
- }
- } else {
- rm = insn & 0xf;
- switch (op1) {
- case 0: /* strex */
- gen_store_exclusive(s, rd, rm, 15, addr, 2);
- break;
- case 1: /* strexd */
- gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
- break;
- case 2: /* strexb */
- gen_store_exclusive(s, rd, rm, 15, addr, 0);
- break;
- case 3: /* strexh */
- gen_store_exclusive(s, rd, rm, 15, addr, 1);
- break;
- default:
- abort();
- }
- }
- tcg_temp_free_i32(addr);
-
- if (is_lasr && is_ld) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- } else if ((insn & 0x00300f00) == 0) {
- /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
- * - SWP, SWPB
- */
-
- TCGv taddr;
- TCGMemOp opc = s->be_data;
-
- rm = (insn) & 0xf;
-
- if (insn & (1 << 22)) {
- opc |= MO_UB;
- } else {
- opc |= MO_UL | MO_ALIGN;
- }
-
- addr = load_reg(s, rn);
- taddr = gen_aa32_addr(s, addr, opc);
- tcg_temp_free_i32(addr);
-
- tmp = load_reg(s, rm);
- tcg_gen_atomic_xchg_i32(tmp, taddr, tmp,
- get_mem_index(s), opc);
- tcg_temp_free(taddr);
- store_reg(s, rd, tmp);
- } else {
- goto illegal_op;
- }
- }
- } else {
- /* Extra load/store (register) instructions */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- }
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
break;
case 0x4:
case 0x5:
@@ -9994,15 +10126,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
goto illegal_op;
}
- addr = tcg_temp_local_new_i32();
- load_reg_var(s, addr, rn);
- tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
- if (insn & (1 << 20)) {
- gen_load_exclusive(s, rs, 15, addr, 2);
- } else {
- gen_store_exclusive(s, rd, rs, 15, addr, 2);
- }
- tcg_temp_free_i32(addr);
+ /* Load/store exclusive, in decodetree */
+ goto illegal_op;
} else if ((insn & (7 << 5)) == 0) {
/* Table Branch. */
if (rn == 15) {
@@ -10029,89 +10154,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_gen_addi_i32(tmp, tmp, s->pc_read);
store_reg(s, 15, tmp);
} else {
- bool is_lasr = false;
- bool is_ld = extract32(insn, 20, 1);
- int op2 = (insn >> 6) & 0x3;
- op = (insn >> 4) & 0x3;
- switch (op2) {
- case 0:
- goto illegal_op;
- case 1:
- /* Load/store exclusive byte/halfword/doubleword */
- if (op == 2) {
- goto illegal_op;
- }
- ARCH(7);
- break;
- case 2:
- /* Load-acquire/store-release */
- if (op == 3) {
- goto illegal_op;
- }
- /* Fall through */
- case 3:
- /* Load-acquire/store-release exclusive */
- ARCH(8);
- is_lasr = true;
- break;
- }
-
- if (is_lasr && !is_ld) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
-
- addr = tcg_temp_local_new_i32();
- load_reg_var(s, addr, rn);
- if (!(op2 & 1)) {
- if (is_ld) {
- tmp = tcg_temp_new_i32();
- switch (op) {
- case 0: /* ldab */
- gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- case 1: /* ldah */
- gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- case 2: /* lda */
- gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- default:
- abort();
- }
- store_reg(s, rs, tmp);
- } else {
- tmp = load_reg(s, rs);
- switch (op) {
- case 0: /* stlb */
- gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- case 1: /* stlh */
- gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- case 2: /* stl */
- gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
- rs | ISSIsAcqRel);
- break;
- default:
- abort();
- }
- tcg_temp_free_i32(tmp);
- }
- } else if (is_ld) {
- gen_load_exclusive(s, rs, rd, addr, op);
- } else {
- gen_store_exclusive(s, rm, rs, rd, addr, op);
- }
- tcg_temp_free_i32(addr);
-
- if (is_lasr && is_ld) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
+ /* Load/store exclusive, load-acq/store-rel, in decodetree */
+ goto illegal_op;
}
} else {
/* Load/store multiple, RFE, SRS. */
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 9789042ca0..1267cebaf4 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -39,6 +39,8 @@
&mrs_bank rd r sysm
&ldst_rr p w u rn rt rm shimm shtype
&ldst_ri p w u rn rt imm
+&strex rn rd rt rt2 imm
+&ldrex rn rt rt2 imm
# Data-processing (register)
@@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1
STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1
LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1
LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1
+
+# Synchronization primitives
+
+@swp ---- .... .... rn:4 rt:4 .... .... rt2:4
+
+SWP .... 0001 0000 .... .... 0000 1001 .... @swp
+SWPB .... 0001 0100 .... .... 0000 1001 .... @swp
+
+# Load/Store Exclusive and Load-Acquire/Store-Release
+#
+# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is even.
+
+@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \
+ &strex imm=0 rt2=15
+@ldrex ---- .... .... rn:4 rt:4 .... .... .... \
+ &ldrex imm=0 rt2=15
+@stl ---- .... .... rn:4 .... .... .... rt:4 \
+ &ldrex imm=0 rt2=15
+
+STREX .... 0001 1000 .... .... 1111 1001 .... @strex
+STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex
+STREXB .... 0001 1100 .... .... 1111 1001 .... @strex
+STREXH .... 0001 1110 .... .... 1111 1001 .... @strex
+
+STLEX .... 0001 1000 .... .... 1110 1001 .... @strex
+STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex
+STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex
+STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex
+
+STL .... 0001 1000 .... 1111 1100 1001 .... @stl
+STLB .... 0001 1100 .... 1111 1100 1001 .... @stl
+STLH .... 0001 1110 .... 1111 1100 1001 .... @stl
+
+LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex
+LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex
+LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex
+LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex
+
+LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex
+LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex
+LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex
+LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex
+
+LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex
+LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex
+LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 0d379ed0d9..62bcf60d57 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -36,6 +36,8 @@
&mrs_bank !extern rd r sysm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
+&strex !extern rn rd rt rt2 imm
+&ldrex !extern rn rt rt2 imm
# Data-processing (register-shifted register)
@@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
+
+# Load/Store Exclusive and Load-Acquire/Store-Release
+
+@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \
+ &strex rt2=15 imm=%imm8x4
+@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \
+ &strex rt2=15 imm=0
+@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \
+ &strex imm=0
+
+@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \
+ &ldrex rt2=15 imm=%imm8x4
+@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \
+ &ldrex rt2=15 imm=0
+@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \
+ &ldrex imm=0
+
+STREX 1110 1000 0100 .... .... .... .... .... @strex_i
+STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0
+STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0
+STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d
+
+STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0
+STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0
+STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0
+STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d
+
+STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0
+STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0
+STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0
+
+LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i
+LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0
+LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0
+LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d
+
+LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0
+LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0
+LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0
+LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d
+
+LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
+LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
+LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (22 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction Richard Henderson
` (44 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 201 +++++++++++++++++++++--------------------
target/arm/a32.decode | 20 ++++
target/arm/t32.decode | 19 ++++
3 files changed, 144 insertions(+), 96 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 74e54b7efb..bcc890c458 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9186,6 +9186,104 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a)
return op_lda(s, a, MO_UW);
}
+/*
+ * Media instructions
+ */
+
+static bool trans_USADA8(DisasContext *s, arg_USADA8 *a)
+{
+ TCGv_i32 t1, t2;
+
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ gen_helper_usad8(t1, t1, t2);
+ tcg_temp_free_i32(t2);
+ if (a->ra != 15) {
+ t2 = load_reg(s, a->ra);
+ tcg_gen_add_i32(t1, t1, t2);
+ tcg_temp_free_i32(t2);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u)
+{
+ TCGv_i32 tmp;
+ int width = a->widthm1 + 1;
+ int shift = a->lsb;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ tmp = load_reg(s, a->rn);
+ if (shift + width > 32) {
+ gen_illegal_op(s);
+ } else if (width < 32) {
+ if (u) {
+ tcg_gen_extract_i32(tmp, tmp, shift, width);
+ } else {
+ tcg_gen_sextract_i32(tmp, tmp, shift, width);
+ }
+ }
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_SBFX(DisasContext *s, arg_SBFX *a)
+{
+ return op_bfx(s, a, false);
+}
+
+static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
+{
+ return op_bfx(s, a, true);
+}
+
+static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
+{
+ TCGv_i32 tmp;
+ int msb = a->msb, lsb = a->lsb;
+ int width;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ if (msb < lsb) {
+ /* UNPREDICTABLE; we choose to UNDEF */
+ gen_illegal_op(s);
+ return true;
+ }
+
+ width = msb + 1 - lsb;
+ if (a->rn == 15) {
+ /* BFC */
+ tmp = tcg_const_i32(0);
+ } else {
+ /* BFI */
+ tmp = load_reg(s, a->rn);
+ }
+ if (width != 32) {
+ TCGv_i32 tmp2 = load_reg(s, a->rd);
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
+ tcg_temp_free_i32(tmp2);
+ }
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_UDF(DisasContext *s, arg_UDF *a)
+{
+ gen_illegal_op(s);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -9723,65 +9821,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
break;
case 3:
- op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
- switch (op1) {
- case 0: /* Unsigned sum of absolute differences. */
- ARCH(6);
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- gen_helper_usad8(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rd != 15) {
- tmp2 = load_reg(s, rd);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rn, tmp);
- break;
- case 0x20: case 0x24: case 0x28: case 0x2c:
- /* Bitfield insert/clear. */
- ARCH(6T2);
- shift = (insn >> 7) & 0x1f;
- i = (insn >> 16) & 0x1f;
- if (i < shift) {
- /* UNPREDICTABLE; we choose to UNDEF */
- goto illegal_op;
- }
- i = i + 1 - shift;
- if (rm == 15) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else {
- tmp = load_reg(s, rm);
- }
- if (i != 32) {
- tmp2 = load_reg(s, rd);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- break;
- case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
- case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
- ARCH(6T2);
- tmp = load_reg(s, rm);
- shift = (insn >> 7) & 0x1f;
- i = ((insn >> 16) & 0x1f) + 1;
- if (shift + i > 32)
- goto illegal_op;
- if (i < 32) {
- if (op1 & 0x20) {
- tcg_gen_extract_i32(tmp, tmp, shift, i);
- } else {
- tcg_gen_sextract_i32(tmp, tmp, shift, i);
- }
- }
- store_reg(s, rd, tmp);
- break;
- default:
- goto illegal_op;
- }
- break;
+ /* USAD, BFI, BFC, SBFX, UBFX */
+ /* Done by decodetree */
+ goto illegal_op;
}
break;
}
@@ -10430,10 +10472,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0: /* 32 x 32 -> 32 */
case 1: /* 16 x 16 -> 32 */
case 3: /* 32 * 16 -> 32msb */
+ case 7: /* Unsigned sum of absolute differences. */
/* in decodetree */
goto illegal_op;
- case 7: /* Unsigned sum of absolute differences. */
- break;
case 2: /* Dual multiply add. */
case 4: /* Dual multiply subtract. */
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
@@ -10487,15 +10528,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_gen_extrl_i64_i32(tmp, tmp64);
tcg_temp_free_i64(tmp64);
break;
- case 7: /* Unsigned sum of absolute differences. */
- gen_helper_usad8(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
}
store_reg(s, rd, tmp);
break;
@@ -10806,32 +10838,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rn);
}
switch (op) {
- case 2: /* Signed bitfield extract. */
- imm++;
- if (shift + imm > 32)
- goto illegal_op;
- if (imm < 32) {
- tcg_gen_sextract_i32(tmp, tmp, shift, imm);
- }
- break;
- case 6: /* Unsigned bitfield extract. */
- imm++;
- if (shift + imm > 32)
- goto illegal_op;
- if (imm < 32) {
- tcg_gen_extract_i32(tmp, tmp, shift, imm);
- }
- break;
- case 3: /* Bitfield insert/clear. */
- if (imm < shift)
- goto illegal_op;
- imm = imm + 1 - shift;
- if (imm != 32) {
- tmp2 = load_reg(s, rd);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm);
- tcg_temp_free_i32(tmp2);
- }
- break;
+ case 2: /* Signed bitfield extract, in decodetree */
+ case 6: /* Unsigned bitfield extract, in decodetree */
+ case 3: /* Bitfield insert/clear, in decodetree */
case 7:
goto illegal_op;
default: /* Saturate. */
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 1267cebaf4..7f51d04a91 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -41,6 +41,8 @@
&ldst_ri p w u rn rt imm
&strex rn rd rt rt2 imm
&ldrex rn rt rt2 imm
+&bfx rd rn lsb widthm1
+&bfi rd rn lsb msb
# Data-processing (register)
@@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex
LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex
LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex
LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex
+
+# Media instructions
+
+# usad8 is usada8 w/ ra=15
+USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4
+
+# ubfx and sbfx
+@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx
+
+SBFX .... 0111 101 ..... .... ..... 101 .... @bfx
+UBFX .... 0111 111 ..... .... ..... 101 .... @bfx
+
+# bfc is bfi w/ rn=15
+BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi
+
+# While we could get UDEF by not including this, add the pattern for
+# documentation and to conflict with any other typos in this file.
+UDF 1110 0111 1111 ---- ---- ---- 1111 ----
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 62bcf60d57..a4a69ad38f 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -38,6 +38,8 @@
&ldst_ri !extern p w u rn rt imm
&strex !extern rn rd rt rt2 imm
&ldrex !extern rn rt rt2 imm
+&bfx !extern rd rn lsb widthm1
+&bfi !extern rd rn lsb msb
# Data-processing (register-shifted register)
@@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
}
+# Saturate, bitfield
+
+@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \
+ &bfx lsb=%imm5_12_6
+@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \
+ &bfi lsb=%imm5_12_6
+
+SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx
+UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx
+
+# bfc is bfi w/ rn=15
+BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi
+
# Multiply and multiply accumulate
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm
SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm
SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
+# usad8 is usada8 w/ ra=15
+USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm
+
# Data-processing (two source registers)
QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
@@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
HVC 1111 0111 1110 .... 1000 .... .... .... \
&i imm=%imm16_16_0
+ UDF 1111 0111 1111 ---- 1010 ---- ---- ----
}
# Load/store (register, immediate, literal)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (23 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
` (43 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 229 ++++++++++++++++++++---------------------
target/arm/a32.decode | 44 ++++++++
target/arm/t32.decode | 44 ++++++++
3 files changed, 200 insertions(+), 117 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bcc890c458..8f2b5dcb02 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -696,99 +696,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
tcg_temp_free_i32(shift);
}
-#define PAS_OP(pfx) \
- switch (op2) { \
- case 0: gen_pas_helper(glue(pfx,add16)); break; \
- case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
- case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
- case 3: gen_pas_helper(glue(pfx,sub16)); break; \
- case 4: gen_pas_helper(glue(pfx,add8)); break; \
- case 7: gen_pas_helper(glue(pfx,sub8)); break; \
- }
-static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_ptr tmp;
-
- switch (op1) {
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
- case 1:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(s)
- tcg_temp_free_ptr(tmp);
- break;
- case 5:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(u)
- tcg_temp_free_ptr(tmp);
- break;
-#undef gen_pas_helper
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
- case 2:
- PAS_OP(q);
- break;
- case 3:
- PAS_OP(sh);
- break;
- case 6:
- PAS_OP(uq);
- break;
- case 7:
- PAS_OP(uh);
- break;
-#undef gen_pas_helper
- }
-}
-#undef PAS_OP
-
-/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
-#define PAS_OP(pfx) \
- switch (op1) { \
- case 0: gen_pas_helper(glue(pfx,add8)); break; \
- case 1: gen_pas_helper(glue(pfx,add16)); break; \
- case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
- case 4: gen_pas_helper(glue(pfx,sub8)); break; \
- case 5: gen_pas_helper(glue(pfx,sub16)); break; \
- case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
- }
-static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_ptr tmp;
-
- switch (op2) {
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
- case 0:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(s)
- tcg_temp_free_ptr(tmp);
- break;
- case 4:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(u)
- tcg_temp_free_ptr(tmp);
- break;
-#undef gen_pas_helper
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
- case 1:
- PAS_OP(q);
- break;
- case 2:
- PAS_OP(sh);
- break;
- case 5:
- PAS_OP(uq);
- break;
- case 6:
- PAS_OP(uh);
- break;
-#undef gen_pas_helper
- }
-}
-#undef PAS_OP
-
/*
* Generate a conditional based on ARM condition code cc.
* This is common between ARM and Aarch64 targets.
@@ -9284,6 +9191,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a)
return true;
}
+/*
+ * Parallel addition and subtraction
+ */
+
+static bool op_par_addsub(DisasContext *s, arg_rrr *a,
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0, t1;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+
+ gen(t0, t0, t1);
+
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ return true;
+}
+
+static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a,
+ void (*gen)(TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_ptr))
+{
+ TCGv_i32 t0, t1;
+ TCGv_ptr ge;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+
+ ge = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE));
+ gen(t0, t0, t1, ge);
+
+ tcg_temp_free_ptr(ge);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ return true;
+}
+
+#define DO_PAR_ADDSUB(NAME, helper) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+{ \
+ return op_par_addsub(s, a, helper); \
+}
+
+#define DO_PAR_ADDSUB_GE(NAME, helper) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+{ \
+ return op_par_addsub_ge(s, a, helper); \
+}
+
+DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16)
+DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx)
+DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx)
+DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16)
+DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8)
+DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8)
+
+DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16)
+DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx)
+DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx)
+DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16)
+DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8)
+DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8)
+
+DO_PAR_ADDSUB(QADD16, gen_helper_qadd16)
+DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx)
+DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx)
+DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16)
+DO_PAR_ADDSUB(QADD8, gen_helper_qadd8)
+DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8)
+
+DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16)
+DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx)
+DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx)
+DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16)
+DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8)
+DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8)
+
+DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16)
+DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx)
+DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx)
+DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16)
+DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8)
+DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8)
+
+DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16)
+DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx)
+DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx)
+DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16)
+DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8)
+DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8)
+
+#undef DO_PAR_ADDSUB
+#undef DO_PAR_ADDSUB_GE
+
/*
* Legacy decoder.
*/
@@ -9593,16 +9608,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
rs = (insn >> 8) & 0xf;
switch ((insn >> 23) & 3) {
case 0: /* Parallel add/subtract. */
- op1 = (insn >> 20) & 7;
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- sh = (insn >> 5) & 7;
- if ((op1 & 3) == 0 || sh == 5 || sh == 6)
- goto illegal_op;
- gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
+ /* Done by decodetree */
+ goto illegal_op;
case 1:
if ((insn & 0x00700020) == 0) {
/* Halfword pack. */
@@ -10396,20 +10403,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
store_reg(s, rd, tmp);
break;
- case 2: /* SIMD add/subtract. */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- op = (insn >> 20) & 7;
- shift = (insn >> 4) & 7;
- if ((op & 3) == 3 || (shift & 3) == 3)
- goto illegal_op;
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
+ case 2: /* SIMD add/subtract, in decodetree */
+ goto illegal_op;
case 3: /* Other data processing. */
op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
if (op < 4) {
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 7f51d04a91..2e0f74044f 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi
# While we could get UDEF by not including this, add the pattern for
# documentation and to conflict with any other typos in this file.
UDF 1110 0111 1111 ---- ---- ---- 1111 ----
+
+# Parallel addition and subtraction
+
+SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm
+SASX .... 0110 0001 .... .... 1111 0011 .... @rndm
+SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm
+SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm
+SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm
+SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm
+
+QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm
+QASX .... 0110 0010 .... .... 1111 0011 .... @rndm
+QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm
+QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm
+QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm
+QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm
+
+SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm
+SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm
+SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm
+SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm
+SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm
+SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm
+
+UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm
+UASX .... 0110 0101 .... .... 1111 0011 .... @rndm
+USAX .... 0110 0101 .... .... 1111 0101 .... @rndm
+USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm
+UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm
+USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm
+
+UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm
+UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm
+UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm
+UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm
+UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm
+UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm
+
+UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm
+UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm
+UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm
+UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm
+UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm
+UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index a4a69ad38f..99673929c0 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d
LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
+
+# Parallel addition and subtraction
+
+SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm
+QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm
+SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm
+UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm
+UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm
+UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm
+
+SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm
+QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm
+SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm
+UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm
+UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm
+UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm
+
+SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm
+QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm
+SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm
+UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm
+UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm
+UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm
+
+SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm
+QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm
+SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm
+USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm
+UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm
+UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm
+
+SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm
+QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm
+SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm
+USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm
+UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm
+UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm
+
+SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm
+QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm
+SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm
+USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm
+UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm
+UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (24 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
` (42 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 554 +++++++++++++++++------------------------
target/arm/a32.decode | 32 +++
target/arm/t32.decode | 37 ++-
3 files changed, 302 insertions(+), 321 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f2b5dcb02..11e74135fd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -364,7 +364,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
}
/* Byteswap each halfword. */
-static void gen_rev16(TCGv_i32 var)
+static void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
@@ -372,17 +372,17 @@ static void gen_rev16(TCGv_i32 var)
tcg_gen_and_i32(tmp, tmp, mask);
tcg_gen_and_i32(var, var, mask);
tcg_gen_shli_i32(var, var, 8);
- tcg_gen_or_i32(var, var, tmp);
+ tcg_gen_or_i32(dest, var, tmp);
tcg_temp_free_i32(mask);
tcg_temp_free_i32(tmp);
}
/* Byteswap low halfword and sign extend. */
-static void gen_revsh(TCGv_i32 var)
+static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
{
tcg_gen_ext16u_i32(var, var);
tcg_gen_bswap16_i32(var, var);
- tcg_gen_ext16s_i32(var, var);
+ tcg_gen_ext16s_i32(dest, var);
}
/* Return (b << 32) + a. Mark inputs as dead */
@@ -467,7 +467,7 @@ static void gen_swap_half(TCGv_i32 var)
t0 = (t0 + t1) ^ tmp;
*/
-static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
+static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_xor_i32(tmp, t0, t1);
@@ -475,9 +475,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
tcg_gen_andi_i32(t0, t0, ~0x8000);
tcg_gen_andi_i32(t1, t1, ~0x8000);
tcg_gen_add_i32(t0, t0, t1);
- tcg_gen_xor_i32(t0, t0, tmp);
+ tcg_gen_xor_i32(dest, t0, tmp);
tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(t1);
}
/* Set N and Z flags from var. */
@@ -6390,7 +6389,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
break;
case NEON_2RM_VREV16:
- gen_rev16(tmp);
+ gen_rev16(tmp, tmp);
break;
case NEON_2RM_VCLS:
switch (size) {
@@ -9299,16 +9298,229 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8)
#undef DO_PAR_ADDSUB
#undef DO_PAR_ADDSUB_GE
+/*
+ * Packing, unpacking, saturation, and reversal
+ */
+
+static bool trans_PKH(DisasContext *s, arg_PKH *a)
+{
+ TCGv_i32 tn, tm;
+ int shift = a->imm;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ tn = load_reg(s, a->rn);
+ tm = load_reg(s, a->rm);
+ if (a->tb) {
+ /* PKHTB */
+ if (shift == 0) {
+ shift = 31;
+ }
+ tcg_gen_sari_i32(tm, tm, shift);
+ tcg_gen_deposit_i32(tn, tn, tm, 0, 16);
+ } else {
+ /* PKHBT */
+ tcg_gen_shli_i32(tm, tm, shift);
+ tcg_gen_deposit_i32(tn, tm, tn, 0, 16);
+ }
+ tcg_temp_free_i32(tm);
+ store_reg(s, a->rd, tn);
+ return true;
+}
+
+static bool op_sat(DisasContext *s, arg_sat *a,
+ void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 tmp, satimm;
+ int shift = a->imm;
+
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+
+ tmp = load_reg(s, a->rn);
+ if (a->sh) {
+ tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31);
+ } else {
+ tcg_gen_shli_i32(tmp, tmp, shift);
+ }
+
+ satimm = tcg_const_i32(a->satimm);
+ gen(tmp, cpu_env, tmp, satimm);
+ tcg_temp_free_i32(satimm);
+
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_SSAT(DisasContext *s, arg_sat *a)
+{
+ return op_sat(s, a, gen_helper_ssat);
+}
+
+static bool trans_USAT(DisasContext *s, arg_sat *a)
+{
+ return op_sat(s, a, gen_helper_usat);
+}
+
+static bool trans_SSAT16(DisasContext *s, arg_sat *a)
+{
+ if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
+ return false;
+ }
+ return op_sat(s, a, gen_helper_ssat16);
+}
+
+static bool trans_USAT16(DisasContext *s, arg_sat *a)
+{
+ if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
+ return false;
+ }
+ return op_sat(s, a, gen_helper_usat16);
+}
+
+static bool op_xta(DisasContext *s, arg_rrr_rot *a,
+ void (*gen_extract)(TCGv_i32, TCGv_i32),
+ void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+
+ tmp = load_reg(s, a->rm);
+ /*
+ * TODO: In many cases we could do a shift instead of a rotate.
+ * Combined with a simple extend, that becomes an extract.
+ */
+ if (a->rot != 0) {
+ tcg_gen_rotri_i32(tmp, tmp, a->rot * 8);
+ }
+ gen_extract(tmp, tmp);
+
+ if (a->rn != 15) {
+ TCGv_i32 tmp2 = load_reg(s, a->rn);
+ gen_add(tmp, tmp, tmp2);
+ tcg_temp_free_i32(tmp2);
+ }
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a)
+{
+ return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32);
+}
+
+static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a)
+{
+ return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32);
+}
+
+static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a)
+{
+ if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
+ return false;
+ }
+ return op_xta(s, a, gen_helper_sxtb16, gen_add16);
+}
+
+static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a)
+{
+ return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32);
+}
+
+static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a)
+{
+ return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32);
+}
+
+static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a)
+{
+ if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
+ return false;
+ }
+ return op_xta(s, a, gen_helper_uxtb16, gen_add16);
+}
+
+static bool trans_SEL(DisasContext *s, arg_rrr *a)
+{
+ TCGv_i32 t1, t2, t3;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ t3 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE));
+ gen_helper_sel_flags(t1, t3, t1, t2);
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool op_rr(DisasContext *s, arg_rr *a,
+ void (*gen)(TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 tmp;
+
+ tmp = load_reg(s, a->rm);
+ gen(tmp, tmp);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_REV(DisasContext *s, arg_rr *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ return op_rr(s, a, tcg_gen_bswap32_i32);
+}
+
+static bool trans_REV16(DisasContext *s, arg_rr *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ return op_rr(s, a, gen_rev16);
+}
+
+static bool trans_REVSH(DisasContext *s, arg_rr *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ return op_rr(s, a, gen_revsh);
+}
+
+static bool trans_RBIT(DisasContext *s, arg_rr *a)
+{
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+ return op_rr(s, a, gen_helper_rbit);
+}
+
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
+ unsigned int cond, val, op1, i, rm, rs, rn, rd;
TCGv_i32 tmp;
TCGv_i32 tmp2;
- TCGv_i32 tmp3;
TCGv_i32 addr;
TCGv_i64 tmp64;
@@ -9611,116 +9823,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* Done by decodetree */
goto illegal_op;
case 1:
- if ((insn & 0x00700020) == 0) {
- /* Halfword pack. */
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- shift = (insn >> 7) & 0x1f;
- if (insn & (1 << 6)) {
- /* pkhtb */
- if (shift == 0)
- shift = 31;
- tcg_gen_sari_i32(tmp2, tmp2, shift);
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
- tcg_gen_ext16u_i32(tmp2, tmp2);
- } else {
- /* pkhbt */
- if (shift)
- tcg_gen_shli_i32(tmp2, tmp2, shift);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
- }
- tcg_gen_or_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else if ((insn & 0x00200020) == 0x00200000) {
- /* [us]sat */
- tmp = load_reg(s, rm);
- shift = (insn >> 7) & 0x1f;
- if (insn & (1 << 6)) {
- if (shift == 0)
- shift = 31;
- tcg_gen_sari_i32(tmp, tmp, shift);
- } else {
- tcg_gen_shli_i32(tmp, tmp, shift);
- }
- sh = (insn >> 16) & 0x1f;
- tmp2 = tcg_const_i32(sh);
- if (insn & (1 << 22))
- gen_helper_usat(tmp, cpu_env, tmp, tmp2);
- else
- gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else if ((insn & 0x00300fe0) == 0x00200f20) {
- /* [us]sat16 */
- tmp = load_reg(s, rm);
- sh = (insn >> 16) & 0x1f;
- tmp2 = tcg_const_i32(sh);
- if (insn & (1 << 22))
- gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
- else
- gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else if ((insn & 0x00700fe0) == 0x00000fa0) {
- /* Select bytes. */
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- tmp3 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
- gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
- tcg_temp_free_i32(tmp3);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else if ((insn & 0x000003e0) == 0x00000060) {
- tmp = load_reg(s, rm);
- shift = (insn >> 10) & 3;
- /* ??? In many cases it's not necessary to do a
- rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
- op1 = (insn >> 20) & 7;
- switch (op1) {
- case 0: gen_sxtb16(tmp); break;
- case 2: gen_sxtb(tmp); break;
- case 3: gen_sxth(tmp); break;
- case 4: gen_uxtb16(tmp); break;
- case 6: gen_uxtb(tmp); break;
- case 7: gen_uxth(tmp); break;
- default: goto illegal_op;
- }
- if (rn != 15) {
- tmp2 = load_reg(s, rn);
- if ((op1 & 3) == 0) {
- gen_add16(tmp, tmp2);
- } else {
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- }
- store_reg(s, rd, tmp);
- } else if ((insn & 0x003f0f60) == 0x003f0f20) {
- /* rev */
- tmp = load_reg(s, rm);
- if (insn & (1 << 22)) {
- if (insn & (1 << 7)) {
- gen_revsh(tmp);
- } else {
- ARCH(6T2);
- gen_helper_rbit(tmp, tmp);
- }
- } else {
- if (insn & (1 << 7))
- gen_rev16(tmp);
- else
- tcg_gen_bswap32_i32(tmp, tmp);
- }
- store_reg(s, rd, tmp);
- } else {
- goto illegal_op;
- }
- break;
+ /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */
+ /* Done by decodetree */
+ goto illegal_op;
case 2: /* Multiplies (Type 3). */
switch ((insn >> 20) & 0x7) {
case 5:
@@ -10053,11 +10158,10 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t imm, shift, offset;
+ uint32_t imm, offset;
uint32_t rd, rn, rm, rs;
TCGv_i32 tmp;
TCGv_i32 tmp2;
- TCGv_i32 tmp3;
TCGv_i32 addr;
TCGv_i64 tmp64;
int op;
@@ -10313,155 +10417,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
break;
case 5:
-
- op = (insn >> 21) & 0xf;
- if (op == 6) {
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- /* Halfword pack. */
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
- if (insn & (1 << 5)) {
- /* pkhtb */
- if (shift == 0)
- shift = 31;
- tcg_gen_sari_i32(tmp2, tmp2, shift);
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
- tcg_gen_ext16u_i32(tmp2, tmp2);
- } else {
- /* pkhbt */
- if (shift)
- tcg_gen_shli_i32(tmp2, tmp2, shift);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
- }
- tcg_gen_or_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else {
- /* Data processing register constant shift. */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- }
- break;
+ /* All in decodetree */
+ goto illegal_op;
case 13: /* Misc data processing. */
op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
if (op < 4 && (insn & 0xf000) != 0xf000)
goto illegal_op;
switch (op) {
case 0: /* Register controlled shift, in decodetree */
- goto illegal_op;
- case 1: /* Sign/zero extend. */
- op = (insn >> 20) & 7;
- switch (op) {
- case 0: /* SXTAH, SXTH */
- case 1: /* UXTAH, UXTH */
- case 4: /* SXTAB, SXTB */
- case 5: /* UXTAB, UXTB */
- break;
- case 2: /* SXTAB16, SXTB16 */
- case 3: /* UXTAB16, UXTB16 */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- break;
- default:
- goto illegal_op;
- }
- if (rn != 15) {
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- }
- tmp = load_reg(s, rm);
- shift = (insn >> 4) & 3;
- /* ??? In many cases it's not necessary to do a
- rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
- op = (insn >> 20) & 7;
- switch (op) {
- case 0: gen_sxth(tmp); break;
- case 1: gen_uxth(tmp); break;
- case 2: gen_sxtb16(tmp); break;
- case 3: gen_uxtb16(tmp); break;
- case 4: gen_sxtb(tmp); break;
- case 5: gen_uxtb(tmp); break;
- default:
- g_assert_not_reached();
- }
- if (rn != 15) {
- tmp2 = load_reg(s, rn);
- if ((op >> 1) == 1) {
- gen_add16(tmp, tmp2);
- } else {
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- }
- store_reg(s, rd, tmp);
- break;
+ case 1: /* Sign/zero extend, in decodetree */
case 2: /* SIMD add/subtract, in decodetree */
+ case 3: /* Other data processing, in decodetree */
goto illegal_op;
- case 3: /* Other data processing. */
- op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
- if (op < 4) {
- /* Saturating add/subtract. */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- } else {
- switch (op) {
- case 0x0a: /* rbit */
- case 0x08: /* rev */
- case 0x09: /* rev16 */
- case 0x0b: /* revsh */
- break;
- case 0x10: /* sel */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- break;
- case 0x18: /* clz, in decodetree */
- case 0x20: /* crc32/crc32c, in decodetree */
- case 0x21:
- case 0x22:
- case 0x28:
- case 0x29:
- case 0x2a:
- goto illegal_op;
- default:
- goto illegal_op;
- }
- tmp = load_reg(s, rn);
- switch (op) {
- case 0x0a: /* rbit */
- gen_helper_rbit(tmp, tmp);
- break;
- case 0x08: /* rev */
- tcg_gen_bswap32_i32(tmp, tmp);
- break;
- case 0x09: /* rev16 */
- gen_rev16(tmp);
- break;
- case 0x0b: /* revsh */
- gen_revsh(tmp);
- break;
- case 0x10: /* sel */
- tmp2 = load_reg(s, rm);
- tmp3 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
- gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
- tcg_temp_free_i32(tmp3);
- tcg_temp_free_i32(tmp2);
- break;
- default:
- g_assert_not_reached();
- }
- }
- store_reg(s, rd, tmp);
- break;
case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
switch ((insn >> 20) & 7) {
case 0: /* 32 x 32 -> 32 */
@@ -10820,61 +10787,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
* - Data-processing (plain binary immediate)
*/
if (insn & (1 << 24)) {
- if (insn & (1 << 20))
- goto illegal_op;
- /* Bitfield/Saturate. */
- op = (insn >> 21) & 7;
- imm = insn & 0x1f;
- shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
- if (rn == 15) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else {
- tmp = load_reg(s, rn);
- }
- switch (op) {
- case 2: /* Signed bitfield extract, in decodetree */
- case 6: /* Unsigned bitfield extract, in decodetree */
- case 3: /* Bitfield insert/clear, in decodetree */
- case 7:
- goto illegal_op;
- default: /* Saturate. */
- if (shift) {
- if (op & 1)
- tcg_gen_sari_i32(tmp, tmp, shift);
- else
- tcg_gen_shli_i32(tmp, tmp, shift);
- }
- tmp2 = tcg_const_i32(imm);
- if (op & 4) {
- /* Unsigned. */
- if ((op & 1) && shift == 0) {
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto illegal_op;
- }
- gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
- } else {
- gen_helper_usat(tmp, cpu_env, tmp, tmp2);
- }
- } else {
- /* Signed. */
- if ((op & 1) && shift == 0) {
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto illegal_op;
- }
- gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
- } else {
- gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
- }
- }
- tcg_temp_free_i32(tmp2);
- break;
- }
- store_reg(s, rd, tmp);
+ /* Bitfield/Saturate, in decodetree */
+ goto illegal_op;
} else {
imm = ((insn & 0x04000000) >> 15)
| ((insn & 0x7000) >> 4) | (insn & 0xff);
@@ -11568,8 +11482,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rn);
switch (op1) {
case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
- case 1: gen_rev16(tmp); break;
- case 3: gen_revsh(tmp); break;
+ case 1: gen_rev16(tmp, tmp); break;
+ case 3: gen_revsh(tmp, tmp); break;
default:
g_assert_not_reached();
}
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 2e0f74044f..725e627796 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -28,6 +28,7 @@
&s_rri_rot s rn rd imm rot
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
+&rrr_rot rd rn rm rot
&rrr rd rn rm
&rr rd rm
&ri rd imm
@@ -43,6 +44,8 @@
&ldrex rn rt rt2 imm
&bfx rd rn lsb widthm1
&bfi rd rn lsb msb
+&sat rd rn satimm imm sh
+&pkh rd rn rm imm tb
# Data-processing (register)
@@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm
UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm
UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm
UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm
+
+# Packing, unpacking, saturation, and reversal
+
+PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh
+
+@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat
+@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \
+ &sat imm=0 sh=0
+
+SSAT .... 0110 101. .... .... .... ..01 .... @sat
+USAT .... 0110 111. .... .... .... ..01 .... @sat
+
+SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16
+USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16
+
+@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot
+
+SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot
+SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot
+SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot
+UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot
+UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot
+UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot
+
+SEL .... 0110 1000 .... .... 1111 1011 .... @rndm
+REV .... 0110 1011 1111 .... 1111 0011 .... @rdm
+REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm
+REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm
+RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 99673929c0..ea147e5348 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -25,6 +25,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
+&rrr_rot !extern rd rn rm rot
&rrr !extern rd rn rm
&rr !extern rd rm
&ri !extern rd imm
@@ -40,6 +41,8 @@
&ldrex !extern rn rt rt2 imm
&bfx !extern rd rn lsb widthm1
&bfi !extern rd rn lsb msb
+&sat !extern rd rn satimm imm sh
+&pkh !extern rd rn rm imm tb
# Data-processing (register-shifted register)
@@ -74,7 +77,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
TEQ_rrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi
EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi
}
-# PKHBT, PKHTB at opc1 = 0110
+PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \
+ &pkh imm=%imm5_12_6
{
CMN_rrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
@@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
# Saturate, bitfield
+@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \
+ &sat imm=%imm5_12_6
+@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \
+ &sat sh=0 imm=0
+
+{
+ SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16
+ SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat
+}
+{
+ USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16
+ USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat
+}
+
@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \
&bfx lsb=%imm5_12_6
@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \
@@ -224,8 +242,14 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
+SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm
+
# Ignore Rn, as allowed by constrained unpredictable.
# This matches the behaviour of the legacy decoder.
+REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm
+REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm
+RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm
+REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm
CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
# Branches and miscellaneous control
@@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm
USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm
UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm
UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm
+
+# Register extends
+
+@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot
+
+SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot
+UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot
+SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot
+UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot
+SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot
+UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (25 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT Richard Henderson
` (41 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 471 ++++++++++++++++++-----------------------
target/arm/a32.decode | 22 ++
target/arm/t32.decode | 18 ++
3 files changed, 248 insertions(+), 263 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 11e74135fd..5bdec27265 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9512,17 +9512,218 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a)
return op_rr(s, a, gen_helper_rbit);
}
+/*
+ * Signed multiply, signed and unsigned divide
+ */
+
+static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
+{
+ TCGv_i32 t1, t2;
+
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ if (m_swap) {
+ gen_swap_half(t2);
+ }
+ gen_smul_dual(t1, t2);
+
+ if (sub) {
+ /* This subtraction cannot overflow. */
+ tcg_gen_sub_i32(t1, t1, t2);
+ } else {
+ /*
+ * This addition cannot overflow 32 bits; however it may
+ * overflow considered as a signed operation, in which case
+ * we must set the Q flag.
+ */
+ gen_helper_add_setq(t1, cpu_env, t1, t2);
+ }
+ tcg_temp_free_i32(t2);
+
+ if (a->ra != 15) {
+ t2 = load_reg(s, a->ra);
+ gen_helper_add_setq(t1, cpu_env, t1, t2);
+ tcg_temp_free_i32(t2);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool trans_SMLAD(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlad(s, a, false, false);
+}
+
+static bool trans_SMLADX(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlad(s, a, true, false);
+}
+
+static bool trans_SMLSD(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlad(s, a, false, true);
+}
+
+static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlad(s, a, true, true);
+}
+
+static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
+{
+ TCGv_i32 t1, t2;
+ TCGv_i64 l1, l2;
+
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ if (m_swap) {
+ gen_swap_half(t2);
+ }
+ gen_smul_dual(t1, t2);
+
+ l1 = tcg_temp_new_i64();
+ l2 = tcg_temp_new_i64();
+ tcg_gen_ext_i32_i64(l1, t1);
+ tcg_gen_ext_i32_i64(l2, t2);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ if (sub) {
+ tcg_gen_sub_i64(l1, l1, l2);
+ } else {
+ tcg_gen_add_i64(l1, l1, l2);
+ }
+ tcg_temp_free_i64(l2);
+
+ gen_addq(s, l1, a->ra, a->rd);
+ gen_storeq_reg(s, a->ra, a->rd, l1);
+ tcg_temp_free_i64(l1);
+ return true;
+}
+
+static bool trans_SMLALD(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlald(s, a, false, false);
+}
+
+static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlald(s, a, true, false);
+}
+
+static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlald(s, a, false, true);
+}
+
+static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a)
+{
+ return op_smlald(s, a, true, true);
+}
+
+static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub)
+{
+ TCGv_i32 t1, t2;
+ TCGv_i64 tmp64;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ tmp64 = gen_muls_i64_i32(t1, t2);
+
+ if (a->ra != 15) {
+ t1 = load_reg(s, a->ra);
+ if (sub) {
+ tmp64 = gen_subq_msw(tmp64, t1);
+ } else {
+ tmp64 = gen_addq_msw(tmp64, t1);
+ }
+ }
+ if (round) {
+ tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
+ }
+ t1 = tcg_temp_new_i32();
+ tcg_gen_extrh_i64_i32(t1, tmp64);
+ tcg_temp_free_i64(tmp64);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool trans_SMMLA(DisasContext *s, arg_rrrr *a)
+{
+ return op_smmla(s, a, false, false);
+}
+
+static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a)
+{
+ return op_smmla(s, a, true, false);
+}
+
+static bool trans_SMMLS(DisasContext *s, arg_rrrr *a)
+{
+ return op_smmla(s, a, false, true);
+}
+
+static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a)
+{
+ return op_smmla(s, a, true, true);
+}
+
+static bool op_div(DisasContext *s, arg_rrr *a, bool u)
+{
+ TCGv_i32 t1, t2;
+
+ if (s->thumb
+ ? !dc_isar_feature(thumb_div, s)
+ : !dc_isar_feature(arm_div, s)) {
+ return false;
+ }
+
+ t1 = load_reg(s, a->rn);
+ t2 = load_reg(s, a->rm);
+ if (u) {
+ gen_helper_udiv(t1, t1, t2);
+ } else {
+ gen_helper_sdiv(t1, t1, t2);
+ }
+ tcg_temp_free_i32(t2);
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+static bool trans_SDIV(DisasContext *s, arg_rrr *a)
+{
+ return op_div(s, a, false);
+}
+
+static bool trans_UDIV(DisasContext *s, arg_rrr *a)
+{
+ return op_div(s, a, true);
+}
+
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, val, op1, i, rm, rs, rn, rd;
+ unsigned int cond, val, op1, i, rn, rd;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
- TCGv_i64 tmp64;
/* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception.
@@ -9802,144 +10003,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
switch(op1) {
case 0x0:
case 0x1:
- /* multiplies, extra load/stores */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- break;
case 0x4:
case 0x5:
- goto do_ldst;
case 0x6:
case 0x7:
- if (insn & (1 << 4)) {
- ARCH(6);
- /* Armv6 Media instructions. */
- rm = insn & 0xf;
- rn = (insn >> 16) & 0xf;
- rd = (insn >> 12) & 0xf;
- rs = (insn >> 8) & 0xf;
- switch ((insn >> 23) & 3) {
- case 0: /* Parallel add/subtract. */
- /* Done by decodetree */
- goto illegal_op;
- case 1:
- /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */
- /* Done by decodetree */
- goto illegal_op;
- case 2: /* Multiplies (Type 3). */
- switch ((insn >> 20) & 0x7) {
- case 5:
- if (((insn >> 6) ^ (insn >> 7)) & 1) {
- /* op2 not 00x or 11x : UNDEF */
- goto illegal_op;
- }
- /* Signed multiply most significant [accumulate].
- (SMMUL, SMMLA, SMMLS) */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
-
- if (rd != 15) {
- tmp = load_reg(s, rd);
- if (insn & (1 << 6)) {
- tmp64 = gen_subq_msw(tmp64, tmp);
- } else {
- tmp64 = gen_addq_msw(tmp64, tmp);
- }
- }
- if (insn & (1 << 5)) {
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
- }
- tcg_gen_shri_i64(tmp64, tmp64, 32);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- store_reg(s, rn, tmp);
- break;
- case 0:
- case 4:
- /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
- if (insn & (1 << 7)) {
- goto illegal_op;
- }
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- if (insn & (1 << 5))
- gen_swap_half(tmp2);
- gen_smul_dual(tmp, tmp2);
- if (insn & (1 << 22)) {
- /* smlald, smlsld */
- TCGv_i64 tmp64_2;
-
- tmp64 = tcg_temp_new_i64();
- tmp64_2 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_gen_ext_i32_i64(tmp64_2, tmp2);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- if (insn & (1 << 6)) {
- tcg_gen_sub_i64(tmp64, tmp64, tmp64_2);
- } else {
- tcg_gen_add_i64(tmp64, tmp64, tmp64_2);
- }
- tcg_temp_free_i64(tmp64_2);
- gen_addq(s, tmp64, rd, rn);
- gen_storeq_reg(s, rd, rn, tmp64);
- tcg_temp_free_i64(tmp64);
- } else {
- /* smuad, smusd, smlad, smlsd */
- if (insn & (1 << 6)) {
- /* This subtraction cannot overflow. */
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- } else {
- /* This addition cannot overflow 32 bits;
- * however it may overflow considered as a
- * signed operation, in which case we must set
- * the Q flag.
- */
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp2);
- if (rd != 15)
- {
- tmp2 = load_reg(s, rd);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rn, tmp);
- }
- break;
- case 1:
- case 3:
- /* SDIV, UDIV */
- if (!dc_isar_feature(arm_div, s)) {
- goto illegal_op;
- }
- if (((insn >> 5) & 7) || (rd != 15)) {
- goto illegal_op;
- }
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- if (insn & (1 << 21)) {
- gen_helper_udiv(tmp, tmp, tmp2);
- } else {
- gen_helper_sdiv(tmp, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp2);
- store_reg(s, rn, tmp);
- break;
- default:
- goto illegal_op;
- }
- break;
- case 3:
- /* USAD, BFI, BFC, SBFX, UBFX */
- /* Done by decodetree */
- goto illegal_op;
- }
- break;
- }
- do_ldst:
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
case 0x08:
@@ -10163,7 +10230,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
- TCGv_i64 tmp64;
int op;
/*
@@ -10429,132 +10495,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 2: /* SIMD add/subtract, in decodetree */
case 3: /* Other data processing, in decodetree */
goto illegal_op;
- case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
- switch ((insn >> 20) & 7) {
- case 0: /* 32 x 32 -> 32 */
- case 1: /* 16 x 16 -> 32 */
- case 3: /* 32 * 16 -> 32msb */
- case 7: /* Unsigned sum of absolute differences. */
- /* in decodetree */
- goto illegal_op;
- case 2: /* Dual multiply add. */
- case 4: /* Dual multiply subtract. */
- case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- break;
- }
- op = (insn >> 4) & 0xf;
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- switch ((insn >> 20) & 7) {
- case 2: /* Dual multiply add. */
- case 4: /* Dual multiply subtract. */
- if (op)
- gen_swap_half(tmp2);
- gen_smul_dual(tmp, tmp2);
- if (insn & (1 << 22)) {
- /* This subtraction cannot overflow. */
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- } else {
- /* This addition cannot overflow 32 bits;
- * however it may overflow considered as a signed
- * operation, in which case we must set the Q flag.
- */
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp2);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
- case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- if (rs != 15) {
- tmp = load_reg(s, rs);
- if (insn & (1 << 20)) {
- tmp64 = gen_addq_msw(tmp64, tmp);
- } else {
- tmp64 = gen_subq_msw(tmp64, tmp);
- }
- }
- if (insn & (1 << 4)) {
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
- }
- tcg_gen_shri_i64(tmp64, tmp64, 32);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- break;
- }
- store_reg(s, rd, tmp);
- break;
- case 6: case 7: /* 64-bit multiply, Divide. */
- op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- if ((op & 0x50) == 0x10) {
- /* sdiv, udiv */
- if (!dc_isar_feature(thumb_div, s)) {
- goto illegal_op;
- }
- if (op & 0x20)
- gen_helper_udiv(tmp, tmp, tmp2);
- else
- gen_helper_sdiv(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- } else if ((op & 0xe) == 0xc) {
- /* Dual multiply accumulate long. */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto illegal_op;
- }
- if (op & 1)
- gen_swap_half(tmp2);
- gen_smul_dual(tmp, tmp2);
- if (op & 0x10) {
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- } else {
- tcg_gen_add_i32(tmp, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp2);
- /* BUGFIX */
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
- gen_addq(s, tmp64, rs, rd);
- gen_storeq_reg(s, rs, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- } else {
- if (op & 0x20) {
- /* Unsigned 64-bit multiply */
- tmp64 = gen_mulu_i64_i32(tmp, tmp2);
- } else {
- if (op & 8) {
- /* smlalxy, in decodetree */
- goto illegal_op;
- } else {
- /* Signed 64-bit multiply */
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- }
- }
- if (op & 4) {
- /* umaal, in decodetree */
- goto illegal_op;
- } else if (op & 0x40) {
- /* 64-bit accumulate. */
- gen_addq(s, tmp64, rs, rd);
- }
- gen_storeq_reg(s, rs, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- }
- break;
+ case 4: case 5:
+ /* 32-bit multiply. Sum of absolute differences, in decodetree */
+ goto illegal_op;
+ case 6: case 7: /* 64-bit multiply, Divide, in decodetree */
+ goto illegal_op;
}
break;
case 6: case 7: case 14: case 15:
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 725e627796..c5af685585 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 .... @rdm
REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm
REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm
RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm
+
+# Signed multiply, signed and unsigned divide
+
+@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr
+
+SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn
+SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn
+SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn
+SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn
+
+SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn
+UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn
+
+SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn
+SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn
+SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn
+SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn
+
+SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn
+SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn
+SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn
+SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index ea147e5348..68203e3704 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
# usad8 is usada8 w/ ra=15
USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm
+SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm
+SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm
+SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm
+SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm
+
+SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm
+SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm
+SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm
+SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm
+
+SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm
+SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm
+SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm
+SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm
+
+SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm
+UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm
+
# Data-processing (two source registers)
QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (26 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM Richard Henderson
` (40 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 89 ++++++++++++++++--------------------------
target/arm/a32.decode | 6 +++
target/arm/t32.decode | 9 +++++
3 files changed, 48 insertions(+), 56 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5bdec27265..ee97a0ccdd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7919,6 +7919,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
return true;
}
+static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ tmp = tcg_const_i32(a->imm);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ tmp = load_reg(s, a->rd);
+ tcg_gen_ext16u_i32(tmp, tmp);
+ tcg_gen_ori_i32(tmp, tmp, a->imm << 16);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
/*
* Multiply and multiply accumulate
*/
@@ -9720,7 +9748,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a)
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, val, op1, i, rn, rd;
+ unsigned int cond, val, op1, i, rn;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
@@ -9966,26 +9994,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* fall back to legacy decoder */
if ((insn & 0x0f900000) == 0x03000000) {
- if ((insn & (1 << 21)) == 0) {
- ARCH(6T2);
- rd = (insn >> 12) & 0xf;
- val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
- if ((insn & (1 << 22)) == 0) {
- /* MOVW */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
- } else {
- /* MOVT */
- tmp = load_reg(s, rd);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_ori_i32(tmp, tmp, val << 16);
- }
- store_reg(s, rd, tmp);
- } else {
- /* MSR (immediate) and hints */
- /* All done in decodetree. Illegal ops already signalled. */
- g_assert_not_reached();
- }
+ /* All done in decodetree. Illegal ops reach here. */
+ goto illegal_op;
} else if ((insn & 0x0f900000) == 0x01000000
&& (insn & 0x00000090) != 0x00000090) {
/* miscellaneous instructions */
@@ -10725,42 +10735,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/*
* 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
* - Data-processing (modified immediate, plain binary immediate)
+ * All in decodetree.
*/
- if (insn & (1 << 25)) {
- /*
- * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx
- * - Data-processing (plain binary immediate)
- */
- if (insn & (1 << 24)) {
- /* Bitfield/Saturate, in decodetree */
- goto illegal_op;
- } else {
- imm = ((insn & 0x04000000) >> 15)
- | ((insn & 0x7000) >> 4) | (insn & 0xff);
- if (insn & (1 << 22)) {
- /* 16-bit immediate. */
- imm |= (insn >> 4) & 0xf000;
- if (insn & (1 << 23)) {
- /* movt */
- tmp = load_reg(s, rd);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_ori_i32(tmp, tmp, imm << 16);
- } else {
- /* movw */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, imm);
- }
- store_reg(s, rd, tmp);
- } else {
- /* Add/sub 12-bit immediate, in decodetree */
- goto illegal_op;
- }
- }
- } else {
- /* Data-processing (modified immediate) */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- }
+ goto illegal_op;
}
break;
case 12:
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index c5af685585..02d7e5b202 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -73,6 +73,12 @@ MOV_rrri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
MVN_rrri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
+%imm16 16:4 0:12
+@mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16
+
+MOVW .... 0011 0000 .... .... ............ @mov16
+MOVT .... 0011 0100 .... .... ............ @mov16
+
# Data-processing (register-shifted register)
@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 68203e3704..fdcfb60cc5 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
}
+# Move Wide
+
+%imm16_26_16_12_0 16:4 26:1 12:3 0:8
+@mov16 .... .... .... .... .... rd:4 .... .... \
+ &ri imm=%imm16_26_16_12_0
+
+MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16
+MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16
+
# Saturate, bitfield
@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (27 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
` (39 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
While unifying all of these paths, remove the constrained unpredictable
test for "wback && registers<n> == 1" from the T2 encoding that isn't
constrained unpredictable for the A1 encoding. The A1 behaviour is
allowed for the T2 behaviour.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 388 ++++++++++++++++++++---------------------
target/arm/a32.decode | 6 +
target/arm/t32.decode | 10 ++
3 files changed, 206 insertions(+), 198 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ee97a0ccdd..33daf70d5d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9742,6 +9742,192 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a)
return op_div(s, a, true);
}
+/*
+ * Block data transfer
+ */
+
+static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int n)
+{
+ TCGv_i32 addr = load_reg(s, a->rn);
+
+ if (a->b) {
+ if (a->i) {
+ /* pre increment */
+ tcg_gen_addi_i32(addr, addr, 4);
+ } else {
+ /* pre decrement */
+ tcg_gen_addi_i32(addr, addr, -(n * 4));
+ }
+ } else if (!a->i && n != 1) {
+ /* post decrement */
+ tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ /*
+ * If the writeback is incrementing SP rather than
+ * decrementing it, and the initial SP is below the
+ * stack limit but the final written-back SP would
+ * be above, then then we must not perform any memory
+ * accesses, but it is IMPDEF whether we generate
+ * an exception. We choose to do so in this case.
+ * At this point 'addr' is the lowest address, so
+ * either the original SP (if incrementing) or our
+ * final SP (if decrementing), so that's what we check.
+ */
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ return addr;
+}
+
+static void op_addr_block_post(DisasContext *s, arg_ldst_block *a,
+ TCGv_i32 addr, int n)
+{
+ if (a->w) {
+ /* write back */
+ if (!a->b) {
+ if (a->i) {
+ /* post increment */
+ tcg_gen_addi_i32(addr, addr, 4);
+ } else {
+ /* post decrement */
+ tcg_gen_addi_i32(addr, addr, -(n * 4));
+ }
+ } else if (!a->i && n != 1) {
+ /* pre decrement */
+ tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
+ }
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+}
+
+static bool trans_STM(DisasContext *s, arg_ldst_block *a)
+{
+ int i, j, n, list, mem_idx;
+ TCGv_i32 addr, tmp, tmp2;
+ bool user = a->u;
+
+ if (user) {
+ /* STM (user) */
+ if (IS_USER(s)) {
+ /* Only usable in supervisor mode. */
+ return false;
+ }
+ }
+
+ /* compute total size */
+ list = a->list;
+ n = ctpop16(list);
+ mem_idx = get_mem_index(s);
+
+ addr = op_addr_block_pre(s, a, n);
+ for (i = j = 0; i < 16; i++) {
+ if (((list >> i) & 1) == 0) {
+ continue;
+ }
+ if (user && i != 15) {
+ tmp = tcg_temp_new_i32();
+ tmp2 = tcg_const_i32(i);
+ gen_helper_get_user_reg(tmp, cpu_env, tmp2);
+ tcg_temp_free_i32(tmp2);
+ } else {
+ tmp = load_reg(s, i);
+ }
+ gen_aa32_st32(s, tmp, addr, mem_idx);
+ tcg_temp_free_i32(tmp);
+ /* No need to add after the last transfer. */
+ if (++j != n) {
+ tcg_gen_addi_i32(addr, addr, 4);
+ }
+ }
+
+ op_addr_block_post(s, a, addr, n);
+ return true;
+}
+
+static bool trans_LDM(DisasContext *s, arg_ldst_block *a)
+{
+ int i, j, n, mem_idx, loaded_base;
+ int list = a->list;
+ bool user = a->u;
+ bool exc_return = false;
+ TCGv_i32 addr, tmp, tmp2, loaded_var;
+
+ if (user) {
+ /* LDM (user), LDM (exception return) */
+ if (IS_USER(s)) {
+ /* Only usable in supervisor mode. */
+ return false;
+ }
+ if (extract32(a->list, 15, 1)) {
+ exc_return = true;
+ user = false;
+ } else {
+ /* LDM (User) does not allow W set. */
+ if (a->w) {
+ return false;
+ }
+ }
+ }
+
+ /* compute total size */
+ loaded_base = 0;
+ loaded_var = NULL;
+ n = ctpop16(list);
+ mem_idx = get_mem_index(s);
+
+ addr = op_addr_block_pre(s, a, n);
+ for (i = j = 0; i < 16; i++) {
+ if (((list >> i) & 1) == 0) {
+ continue;
+ }
+ tmp = tcg_temp_new_i32();
+ gen_aa32_ld32u(s, tmp, addr, mem_idx);
+ if (user) {
+ tmp2 = tcg_const_i32(i);
+ gen_helper_set_user_reg(cpu_env, tmp2, tmp);
+ tcg_temp_free_i32(tmp2);
+ tcg_temp_free_i32(tmp);
+ } else if (i == a->rn) {
+ loaded_var = tmp;
+ loaded_base = 1;
+ } else if (i == 15 && exc_return) {
+ store_pc_exc_ret(s, tmp);
+ } else {
+ store_reg_from_load(s, i, tmp);
+ }
+ /* No need to add after the last transfer. */
+ if (++j != n) {
+ tcg_gen_addi_i32(addr, addr, 4);
+ }
+ }
+
+ op_addr_block_post(s, a, addr, n);
+
+ if (loaded_base) {
+ store_reg(s, a->rn, loaded_var);
+ }
+
+ if (exc_return) {
+ /* Restore CPSR from SPSR. */
+ tmp = load_cpu_field(spsr);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_cpsr_write_eret(cpu_env, tmp);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ tcg_temp_free_i32(tmp);
+ /* Must exit loop to check un-masked IRQs */
+ s->base.is_jmp = DISAS_EXIT;
+ }
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10017,139 +10203,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0x5:
case 0x6:
case 0x7:
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
case 0x08:
case 0x09:
- {
- int j, n, loaded_base;
- bool exc_return = false;
- bool is_load = extract32(insn, 20, 1);
- bool user = false;
- TCGv_i32 loaded_var;
- /* load/store multiple words */
- /* XXX: store correct base if write back */
- if (insn & (1 << 22)) {
- /* LDM (user), LDM (exception return) and STM (user) */
- if (IS_USER(s))
- goto illegal_op; /* only usable in supervisor mode */
-
- if (is_load && extract32(insn, 15, 1)) {
- exc_return = true;
- } else {
- user = true;
- }
- }
- rn = (insn >> 16) & 0xf;
- addr = load_reg(s, rn);
-
- /* compute total size */
- loaded_base = 0;
- loaded_var = NULL;
- n = 0;
- for (i = 0; i < 16; i++) {
- if (insn & (1 << i))
- n++;
- }
- /* XXX: test invalid n == 0 case ? */
- if (insn & (1 << 23)) {
- if (insn & (1 << 24)) {
- /* pre increment */
- tcg_gen_addi_i32(addr, addr, 4);
- } else {
- /* post increment */
- }
- } else {
- if (insn & (1 << 24)) {
- /* pre decrement */
- tcg_gen_addi_i32(addr, addr, -(n * 4));
- } else {
- /* post decrement */
- if (n != 1)
- tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
- }
- }
- j = 0;
- for (i = 0; i < 16; i++) {
- if (insn & (1 << i)) {
- if (is_load) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- if (user) {
- tmp2 = tcg_const_i32(i);
- gen_helper_set_user_reg(cpu_env, tmp2, tmp);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- } else if (i == rn) {
- loaded_var = tmp;
- loaded_base = 1;
- } else if (i == 15 && exc_return) {
- store_pc_exc_ret(s, tmp);
- } else {
- store_reg_from_load(s, i, tmp);
- }
- } else {
- /* store */
- if (user && i != 15) {
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_const_i32(i);
- gen_helper_get_user_reg(tmp, cpu_env, tmp2);
- tcg_temp_free_i32(tmp2);
- } else {
- tmp = load_reg(s, i);
- }
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- j++;
- /* no need to add after the last transfer */
- if (j != n)
- tcg_gen_addi_i32(addr, addr, 4);
- }
- }
- if (insn & (1 << 21)) {
- /* write back */
- if (insn & (1 << 23)) {
- if (insn & (1 << 24)) {
- /* pre increment */
- } else {
- /* post increment */
- tcg_gen_addi_i32(addr, addr, 4);
- }
- } else {
- if (insn & (1 << 24)) {
- /* pre decrement */
- if (n != 1)
- tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
- } else {
- /* post decrement */
- tcg_gen_addi_i32(addr, addr, -(n * 4));
- }
- }
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- if (loaded_base) {
- store_reg(s, rn, loaded_var);
- }
- if (exc_return) {
- /* Restore CPSR from SPSR. */
- tmp = load_cpu_field(spsr);
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_cpsr_write_eret(cpu_env, tmp);
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- }
- tcg_temp_free_i32(tmp);
- /* Must exit loop to check un-masked IRQs */
- s->base.is_jmp = DISAS_EXIT;
- }
- }
- break;
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
case 0xa:
case 0xb:
{
@@ -10422,73 +10479,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
insn & (1 << 21));
}
} else {
- int i, loaded_base = 0;
- TCGv_i32 loaded_var;
- bool wback = extract32(insn, 21, 1);
- /* Load/store multiple. */
- addr = load_reg(s, rn);
- offset = 0;
- for (i = 0; i < 16; i++) {
- if (insn & (1 << i))
- offset += 4;
- }
-
- if (insn & (1 << 24)) {
- tcg_gen_addi_i32(addr, addr, -offset);
- }
-
- if (s->v8m_stackcheck && rn == 13 && wback) {
- /*
- * If the writeback is incrementing SP rather than
- * decrementing it, and the initial SP is below the
- * stack limit but the final written-back SP would
- * be above, then then we must not perform any memory
- * accesses, but it is IMPDEF whether we generate
- * an exception. We choose to do so in this case.
- * At this point 'addr' is the lowest address, so
- * either the original SP (if incrementing) or our
- * final SP (if decrementing), so that's what we check.
- */
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
-
- loaded_var = NULL;
- for (i = 0; i < 16; i++) {
- if ((insn & (1 << i)) == 0)
- continue;
- if (insn & (1 << 20)) {
- /* Load. */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- if (i == rn) {
- loaded_var = tmp;
- loaded_base = 1;
- } else {
- store_reg_from_load(s, i, tmp);
- }
- } else {
- /* Store. */
- tmp = load_reg(s, i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_addi_i32(addr, addr, 4);
- }
- if (loaded_base) {
- store_reg(s, rn, loaded_var);
- }
- if (wback) {
- /* Base register writeback. */
- if (insn & (1 << 24)) {
- tcg_gen_addi_i32(addr, addr, -offset);
- }
- /* Fault if writeback register is in register list. */
- if (insn & (1 << rn))
- goto illegal_op;
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
+ /* Load/store multiple, in decodetree */
+ goto illegal_op;
}
}
break;
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 02d7e5b202..96c47aaf2a 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -40,6 +40,7 @@
&mrs_bank rd r sysm
&ldst_rr p w u rn rt rm shimm shtype
&ldst_ri p w u rn rt imm
+&ldst_block rn i b u w list
&strex rn rd rt rt2 imm
&ldrex rn rt rt2 imm
&bfx rd rn lsb widthm1
@@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn
SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn
SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn
SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn
+
+# Block data transfer
+
+STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block
+LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index fdcfb60cc5..3ab82c0962 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -37,6 +37,7 @@
&mrs_bank !extern rd r sysm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
+&ldst_block !extern rn i b u w list
&strex !extern rn rd rt rt2 imm
&ldrex !extern rn rt rt2 imm
&bfx !extern rd rn lsb widthm1
@@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot
UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot
SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot
UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot
+
+# Load/store multiple
+
+@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block u=0
+
+STM 1110 1000 10.0 .... ................ @ldstm i=1 b=0
+STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1
+LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0
+LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (28 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC Richard Henderson
` (38 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 134 +++++++++++++++--------------------
target/arm/a32-uncond.decode | 8 +++
target/arm/a32.decode | 8 +++
target/arm/t32.decode | 79 +++++++++++++--------
4 files changed, 122 insertions(+), 107 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 33daf70d5d..3f14e5c7f3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7582,6 +7582,14 @@ static int t32_expandimm_imm(DisasContext *s, int x)
return imm;
}
+static int t32_branch24(DisasContext *s, int x)
+{
+ /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */
+ x ^= !(x < 0) * (3 << 21);
+ /* Append the final zero. */
+ return x << 1;
+}
+
/*
* Include the generated decoders.
* Note that the T32 decoder reuses some of the trans_* functions
@@ -9928,13 +9936,56 @@ static bool trans_LDM(DisasContext *s, arg_ldst_block *a)
return true;
}
+/*
+ * Branch, branch with link
+ */
+
+static bool trans_B(DisasContext *s, arg_i *a)
+{
+ gen_jmp(s, s->pc_read + a->imm);
+ return true;
+}
+
+static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
+{
+ /* This has cond from encoding, required to be outside IT block. */
+ if (a->cond >= 0xe) {
+ return false;
+ }
+ if (s->condexec_mask) {
+ gen_illegal_op(s);
+ return true;
+ }
+ arm_skip_unless(s, a->cond);
+ gen_jmp(s, s->pc_read + a->imm);
+ return true;
+}
+
+static bool trans_BL(DisasContext *s, arg_i *a)
+{
+ tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb);
+ gen_jmp(s, s->pc_read + a->imm);
+ return true;
+}
+
+static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
+{
+ /* For A32, ARCH(5) is checked near the start of the uncond block. */
+ if (s->thumb && (a->imm & 2)) {
+ return false;
+ }
+ tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb);
+ gen_bx_im(s, (s->pc_read & ~3) + a->imm + !s->thumb);
+ return true;
+}
+
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, val, op1, i, rn;
+ unsigned int cond, op1, i, rn;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
@@ -10102,21 +10153,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
gen_rfe(s, tmp, tmp2);
return;
- } else if ((insn & 0x0e000000) == 0x0a000000) {
- /* branch link and change to thumb (blx <offset>) */
- int32_t offset;
-
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, s->pc);
- store_reg(s, 14, tmp);
- /* Sign-extend the 24-bit offset */
- offset = (((int32_t)insn) << 8) >> 8;
- val = s->pc_read;
- /* offset * 4 + bit24 * 2 + (thumb bit) */
- val += (offset << 2) | ((insn >> 23) & 2) | 1;
- /* protected by ARCH(5); above, near the start of uncond block */
- gen_bx_im(s, val);
- return;
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10205,24 +10241,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0x7:
case 0x08:
case 0x09:
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
case 0xa:
case 0xb:
- {
- int32_t offset;
-
- /* branch (and link) */
- if (insn & (1 << 24)) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, s->pc);
- store_reg(s, 14, tmp);
- }
- offset = sextract32(insn << 2, 0, 26);
- val = s->pc_read + offset;
- gen_jmp(s, val);
- }
- break;
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
case 0xc:
case 0xd:
case 0xe:
@@ -10594,32 +10616,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
if (insn & (1 << 15)) {
/* Branches, misc control. */
if (insn & 0x5000) {
- /* Unconditional branch. */
- /* signextend(hw1[10:0]) -> offset[:12]. */
- offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
- /* hw1[10:0] -> offset[11:1]. */
- offset |= (insn & 0x7ff) << 1;
- /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
- offset[24:22] already have the same value because of the
- sign extension above. */
- offset ^= ((~insn) & (1 << 13)) << 10;
- offset ^= ((~insn) & (1 << 11)) << 11;
-
- if (insn & (1 << 14)) {
- /* Branch and link. */
- tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
- }
-
- offset += s->pc_read;
- if (insn & (1 << 12)) {
- /* b/bl */
- gen_jmp(s, offset);
- } else {
- /* blx */
- offset &= ~(uint32_t)2;
- /* thumb2 bx, no need to check */
- gen_bx_im(s, offset);
- }
+ /* Unconditional branch, in decodetree */
+ goto illegal_op;
} else if (((insn >> 23) & 7) == 7) {
/* Misc control */
if (insn & (1 << 13))
@@ -10704,24 +10702,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
} else {
- /* Conditional branch. */
- op = (insn >> 22) & 0xf;
- /* Generate a conditional jump to next instruction. */
- arm_skip_unless(s, op);
-
- /* offset[11:1] = insn[10:0] */
- offset = (insn & 0x7ff) << 1;
- /* offset[17:12] = insn[21:16]. */
- offset |= (insn & 0x003f0000) >> 4;
- /* offset[31:20] = insn[26]. */
- offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
- /* offset[18] = insn[13]. */
- offset |= (insn & (1 << 13)) << 5;
- /* offset[19] = insn[11]. */
- offset |= (insn & (1 << 11)) << 8;
-
- /* jump to the offset */
- gen_jmp(s, s->pc_read + offset);
+ /* Conditional branch, in decodetree */
+ goto illegal_op;
}
} else {
/*
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 8dee26d3b6..573ac2cf8e 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -21,3 +21,11 @@
# All insns that have 0xf in insn[31:28] are decoded here.
# All of those that have a COND field in insn[31:28] are in a32.decode
#
+
+&i !extern imm
+
+# Branch with Link and Exchange
+
+%imm24h 0:s24 24:1 !function=times_2
+
+BLX_i 1111 101 . ........................ &i imm=%imm24h
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 96c47aaf2a..f0f0f50c4e 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn
STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block
LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block
+
+# Branch, branch with link
+
+%imm26 0:s24 !function=times_4
+@branch ---- .... ........................ &i imm=%imm26
+
+B .... 1010 ........................ @branch
+BL .... 1011 ........................ @branch
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 3ab82c0962..ab7d7ba100 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -285,46 +285,54 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
%msr_sysm 4:1 8:4
%mrs_sysm 4:1 16:4
%imm16_16_0 16:4 0:12
+%imm21 26:s1 11:1 13:1 16:6 0:11 !function=times_2
+&ci cond imm
{
+ # Group insn[25:23] = 111, which is cond=111x for the branch below,
+ # or unconditional, which would be illegal for the branch.
{
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
+ # Hints
+ {
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
- # TODO: Implement SEV, SEVL; may help SMP performance.
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
- # The canonical nop ends in 0000 0000, but the whole rest
- # of the space is "reserved hint, behaves as nop".
- NOP 1111 0011 1010 1111 1000 0000 ---- ----
- }
- # Note that the v7m insn overlaps both the normal and banked insn.
- {
- MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
+ # The canonical nop ends in 0000 0000, but the whole rest
+ # of the space is "reserved hint, behaves as nop".
+ NOP 1111 0011 1010 1111 1000 0000 ---- ----
+ }
+ # Note that the v7m insn overlaps both the normal and banked insn.
+ {
+ MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
&mrs_bank sysm=%mrs_sysm
- MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
- MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
- }
- {
- MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
+ MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
+ MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
+ }
+ {
+ MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
&msr_bank sysm=%msr_sysm
- MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
- MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
- }
- BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
- {
- # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
- # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
- ERET 1111 0011 1101 1110 1000 1111 0000 0000
- SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
+ MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
+ MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
+ }
+ BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
+ {
+ # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
+ # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
+ ERET 1111 0011 1101 1110 1000 1111 0000 0000
+ SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
&s_rri_rot rot=0 s=1 rd=15 rn=14
- }
- SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
- HVC 1111 0111 1110 .... 1000 .... .... .... \
+ }
+ SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
+ HVC 1111 0111 1110 .... 1000 .... .... .... \
&i imm=%imm16_16_0
- UDF 1111 0111 1111 ---- 1010 ---- ---- ----
+ UDF 1111 0111 1111 ---- 1010 ---- ---- ----
+ }
+ B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21
}
# Load/store (register, immediate, literal)
@@ -573,3 +581,12 @@ STM 1110 1000 10.0 .... ................ @ldstm i=1 b=0
STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1
LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0
LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1
+
+# Branches
+
+%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24
+@branch24 ................................ &i imm=%imm24
+
+B 1111 0. .......... 10.1 ............ @branch24
+BL 1111 0. .......... 11.1 ............ @branch24
+BLX_i 1111 0. .......... 11.0 ............ @branch24
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (29 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS Richard Henderson
` (37 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 19 +++++++++++++------
target/arm/a32.decode | 4 ++++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3f14e5c7f3..7ea118a795 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9979,6 +9979,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+/*
+ * Supervisor call
+ */
+
+static bool trans_SVC(DisasContext *s, arg_SVC *a)
+{
+ gen_set_pc_im(s, s->pc);
+ s->svc_imm = a->imm;
+ s->base.is_jmp = DISAS_SWI;
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10243,6 +10255,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0x09:
case 0xa:
case 0xb:
+ case 0xf:
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
case 0xc:
@@ -10258,12 +10271,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
goto illegal_op;
}
break;
- case 0xf:
- /* swi */
- gen_set_pc_im(s, s->pc);
- s->svc_imm = extract32(insn, 0, 24);
- s->base.is_jmp = DISAS_SWI;
- break;
default:
illegal_op:
gen_illegal_op(s);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index f0f0f50c4e..c2fb28f235 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -528,3 +528,7 @@ LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block
B .... 1010 ........................ @branch
BL .... 1011 ........................ @branch
+
+# Supervisor call
+
+SVC ---- 1111 imm:24 &i
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (30 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
` (36 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 150 ++++++++++++++---------------------
target/arm/a32-uncond.decode | 8 ++
target/arm/t32.decode | 12 +++
3 files changed, 81 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7ea118a795..b43b344f96 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9991,16 +9991,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
return true;
}
+/*
+ * Unconditional system instructions
+ */
+
+static bool trans_RFE(DisasContext *s, arg_RFE *a)
+{
+ int32_t offset;
+ TCGv_i32 addr, t1, t2;
+
+ if (IS_USER(s) || !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ addr = load_reg(s, a->rn);
+
+ switch (a->pu) {
+ case 0: offset = -4; break; /* DA */
+ case 1: offset = 0; break; /* IA */
+ case 2: offset = -8; break; /* DB */
+ case 3: offset = 4; break; /* IB */
+ default:
+ g_assert_not_reached();
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+
+ /* Load PC into tmp and CPSR into tmp2. */
+ t1 = tcg_temp_new_i32();
+ gen_aa32_ld32u(s, t1, addr, get_mem_index(s));
+ tcg_gen_addi_i32(addr, addr, 4);
+ t2 = tcg_temp_new_i32();
+ gen_aa32_ld32u(s, t2, addr, get_mem_index(s));
+
+ if (a->w) {
+ /* Base writeback. */
+ switch (a->pu) {
+ case 0: offset = -8; break;
+ case 1: offset = 4; break;
+ case 2: offset = -4; break;
+ case 3: offset = 0; break;
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+ gen_rfe(s, t1, t2);
+ return true;
+}
+
+static bool trans_SRS(DisasContext *s, arg_SRS *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ gen_srs(s, a->mode, a->pu, a->w);
+ return true;
+}
+
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, op1, i, rn;
- TCGv_i32 tmp;
- TCGv_i32 tmp2;
- TCGv_i32 addr;
+ unsigned int cond, op1;
/* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception.
@@ -10119,52 +10174,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
default:
goto illegal_op;
}
- } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
- /* srs */
- ARCH(6);
- gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21));
- return;
- } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
- /* rfe */
- int32_t offset;
- if (IS_USER(s))
- goto illegal_op;
- ARCH(6);
- rn = (insn >> 16) & 0xf;
- addr = load_reg(s, rn);
- i = (insn >> 23) & 3;
- switch (i) {
- case 0: offset = -4; break; /* DA */
- case 1: offset = 0; break; /* IA */
- case 2: offset = -8; break; /* DB */
- case 3: offset = 4; break; /* IB */
- default: abort();
- }
- if (offset)
- tcg_gen_addi_i32(addr, addr, offset);
- /* Load PC into tmp and CPSR into tmp2. */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- tcg_gen_addi_i32(addr, addr, 4);
- tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
- if (insn & (1 << 21)) {
- /* Base writeback. */
- switch (i) {
- case 0: offset = -8; break;
- case 1: offset = 4; break;
- case 2: offset = -4; break;
- case 3: offset = 0; break;
- default: abort();
- }
- if (offset)
- tcg_gen_addi_i32(addr, addr, offset);
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- gen_rfe(s, tmp, tmp2);
- return;
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10324,7 +10333,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
uint32_t imm, offset;
uint32_t rd, rn, rm, rs;
TCGv_i32 tmp;
- TCGv_i32 tmp2;
TCGv_i32 addr;
int op;
@@ -10473,44 +10481,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
} else {
- /* Load/store multiple, RFE, SRS. */
- if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
- /* RFE, SRS: not available in user mode or on M profile */
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- if (insn & (1 << 20)) {
- /* rfe */
- addr = load_reg(s, rn);
- if ((insn & (1 << 24)) == 0)
- tcg_gen_addi_i32(addr, addr, -8);
- /* Load PC into tmp and CPSR into tmp2. */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- tcg_gen_addi_i32(addr, addr, 4);
- tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
- if (insn & (1 << 21)) {
- /* Base writeback. */
- if (insn & (1 << 24)) {
- tcg_gen_addi_i32(addr, addr, 4);
- } else {
- tcg_gen_addi_i32(addr, addr, -4);
- }
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- gen_rfe(s, tmp, tmp2);
- } else {
- /* srs */
- gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2,
- insn & (1 << 21));
- }
- } else {
- /* Load/store multiple, in decodetree */
- goto illegal_op;
- }
+ /* Load/store multiple, RFE, SRS, in decodetree */
+ goto illegal_op;
}
break;
case 5:
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 573ac2cf8e..3b961233e5 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -29,3 +29,11 @@
%imm24h 0:s24 24:1 !function=times_2
BLX_i 1111 101 . ........................ &i imm=%imm24h
+
+# System Instructions
+
+&rfe rn w pu
+&srs mode w pu
+
+RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
+SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index ab7d7ba100..26b51c3bb2 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -582,6 +582,18 @@ STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1
LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0
LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1
+&rfe !extern rn w pu
+@rfe .... .... .. w:1 . rn:4 ................ &rfe
+
+RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=2
+RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1
+
+&srs !extern mode w pu
+@srs .... .... .. w:1 . .... ........... mode:5 &srs
+
+SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2
+SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1
+
# Branches
%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (31 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) Richard Henderson
` (35 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 122 +++++++++++++++--------------------
target/arm/a32-uncond.decode | 10 +++
target/arm/t32.decode | 10 +++
3 files changed, 73 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b43b344f96..797e8f7344 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10049,6 +10049,58 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a)
return true;
}
+/*
+ * Clear-Exclusive, Barriers
+ */
+
+static bool trans_CLREX(DisasContext *s, arg_CLREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ gen_clrex(s);
+ return true;
+}
+
+static bool trans_DSB(DisasContext *s, arg_DSB *a)
+{
+ if (!s->thumb && !ENABLE_ARCH_7) {
+ return false;
+ }
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_DMB(DisasContext *s, arg_DMB *a)
+{
+ return trans_DSB(s, NULL);
+}
+
+static bool trans_ISB(DisasContext *s, arg_ISB *a)
+{
+ /*
+ * We need to break the TB after this insn to execute
+ * self-modifying code correctly and also to take
+ * any pending interrupts immediately.
+ */
+ gen_goto_tb(s, 0, s->pc & ~1);
+ return true;
+}
+
+static bool trans_SB(DisasContext *s, arg_SB *a)
+{
+ if (!dc_isar_feature(aa32_sb, s)) {
+ return false;
+ }
+ /*
+ * TODO: There is no speculation barrier opcode
+ * for TCG; MB and end the TB instead.
+ */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ gen_goto_tb(s, 0, s->pc & ~1);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10142,38 +10194,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
s->base.is_jmp = DISAS_UPDATE;
}
return;
- } else if ((insn & 0x0fffff00) == 0x057ff000) {
- switch ((insn >> 4) & 0xf) {
- case 1: /* clrex */
- ARCH(6K);
- gen_clrex(s);
- return;
- case 4: /* dsb */
- case 5: /* dmb */
- ARCH(7);
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- return;
- case 6: /* isb */
- /* We need to break the TB after this insn to execute
- * self-modifying code correctly and also to take
- * any pending interrupts immediately.
- */
- gen_goto_tb(s, 0, s->pc & ~1);
- return;
- case 7: /* sb */
- if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
- goto illegal_op;
- }
- /*
- * TODO: There is no speculation barrier opcode
- * for TCG; MB and end the TB instead.
- */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_goto_tb(s, 0, s->pc & ~1);
- return;
- default:
- goto illegal_op;
- }
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10636,43 +10656,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
gen_set_psr_im(s, offset, 0, imm);
}
break;
- case 3: /* Special control operations. */
- if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
- !arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- op = (insn >> 4) & 0xf;
- switch (op) {
- case 2: /* clrex */
- gen_clrex(s);
- break;
- case 4: /* dsb */
- case 5: /* dmb */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- break;
- case 6: /* isb */
- /* We need to break the TB after this insn
- * to execute self-modifying code correctly
- * and also to take any pending interrupts
- * immediately.
- */
- gen_goto_tb(s, 0, s->pc & ~1);
- break;
- case 7: /* sb */
- if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
- goto illegal_op;
- }
- /*
- * TODO: There is no speculation barrier opcode
- * for TCG; MB and end the TB instead.
- */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_goto_tb(s, 0, s->pc & ~1);
- break;
- default:
- goto illegal_op;
- }
- break;
+ case 3: /* Special control operations, in decodetree */
case 4: /* bxj, in decodetree */
case 5: /* eret, in decodetree */
case 6: /* MRS, in decodetree */
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 3b961233e5..b077958cec 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -22,6 +22,7 @@
# All of those that have a COND field in insn[31:28] are in a32.decode
#
+&empty !extern
&i !extern imm
# Branch with Link and Exchange
@@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h
RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
+
+# Clear-Exclusive, Barriers
+
+# QEMU does not require the option field for the barriers.
+CLREX 1111 0101 0111 1111 1111 0000 0001 1111
+DSB 1111 0101 0111 1111 1111 0000 0100 ----
+DMB 1111 0101 0111 1111 1111 0000 0101 ----
+ISB 1111 0101 0111 1111 1111 0000 0110 ----
+SB 1111 0101 0111 1111 1111 0000 0111 0000
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 26b51c3bb2..9fe1500fe0 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -306,6 +306,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
# of the space is "reserved hint, behaves as nop".
NOP 1111 0011 1010 1111 1000 0000 ---- ----
}
+
+ # Miscelaneous control
+ {
+ CLREX 1111 0011 1011 1111 1000 1111 0010 1111
+ DSB 1111 0011 1011 1111 1000 1111 0100 ----
+ DMB 1111 0011 1011 1111 1000 1111 0101 ----
+ ISB 1111 0011 1011 1111 1000 1111 0110 ----
+ SB 1111 0011 1011 1111 1000 1111 0111 0000
+ }
+
# Note that the v7m insn overlaps both the normal and banked insn.
{
MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (32 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
@ 2019-07-26 17:49 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND Richard Henderson
` (34 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:49 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 87 +++++++++++++++---------------------
target/arm/a32-uncond.decode | 3 ++
target/arm/t32.decode | 3 ++
3 files changed, 42 insertions(+), 51 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 797e8f7344..8dbe189df7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10049,6 +10049,40 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a)
return true;
}
+static bool trans_CPS(DisasContext *s, arg_CPS *a)
+{
+ uint32_t mask, val;
+
+ if (IS_USER(s)) {
+ /* Implemented as NOP in user mode. */
+ return true;
+ }
+
+ mask = val = 0;
+ if (a->imod & 2) {
+ if (a->A) {
+ mask |= CPSR_A;
+ }
+ if (a->I) {
+ mask |= CPSR_I;
+ }
+ if (a->F) {
+ mask |= CPSR_F;
+ }
+ if (a->imod & 1) {
+ val |= mask;
+ }
+ }
+ if (a->M) {
+ mask |= CPSR_M;
+ val |= a->mode;
+ }
+ if (mask) {
+ gen_set_psr_im(s, mask, 0, val);
+ }
+ return true;
+}
+
/*
* Clear-Exclusive, Barriers
*/
@@ -10220,31 +10254,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5TE);
} else if ((insn & 0x0f000010) == 0x0e000010) {
/* Additional coprocessor register transfer. */
- } else if ((insn & 0x0ff10020) == 0x01000000) {
- uint32_t mask;
- uint32_t val;
- /* cps (privileged) */
- if (IS_USER(s))
- return;
- mask = val = 0;
- if (insn & (1 << 19)) {
- if (insn & (1 << 8))
- mask |= CPSR_A;
- if (insn & (1 << 7))
- mask |= CPSR_I;
- if (insn & (1 << 6))
- mask |= CPSR_F;
- if (insn & (1 << 18))
- val |= mask;
- }
- if (insn & (1 << 17)) {
- mask |= CPSR_M;
- val |= (insn & 0x1f);
- }
- if (mask) {
- gen_set_psr_im(s, mask, 0, val);
- }
- return;
}
goto illegal_op;
}
@@ -10350,7 +10359,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t imm, offset;
uint32_t rd, rn, rm, rs;
TCGv_i32 tmp;
TCGv_i32 addr;
@@ -10631,31 +10639,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0: /* msr cpsr, in decodetree */
case 1: /* msr spsr, in decodetree */
goto illegal_op;
- case 2: /* cps, nop-hint. */
- /* nop hints in decodetree */
- /* Implemented as NOP in user mode. */
- if (IS_USER(s))
- break;
- offset = 0;
- imm = 0;
- if (insn & (1 << 10)) {
- if (insn & (1 << 7))
- offset |= CPSR_A;
- if (insn & (1 << 6))
- offset |= CPSR_I;
- if (insn & (1 << 5))
- offset |= CPSR_F;
- if (insn & (1 << 9))
- imm = CPSR_A | CPSR_I | CPSR_F;
- }
- if (insn & (1 << 8)) {
- offset |= 0x1f;
- imm |= (insn & 0x1f);
- }
- if (offset) {
- gen_set_psr_im(s, offset, 0, imm);
- }
- break;
+ case 2: /* cps, nop-hint, in decodetree */
+ goto illegal_op;
case 3: /* Special control operations, in decodetree */
case 4: /* bxj, in decodetree */
case 5: /* eret, in decodetree */
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index b077958cec..eb1c55b330 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h
&rfe rn w pu
&srs mode w pu
+&cps mode imod M A I F
RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
+CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \
+ &cps
# Clear-Exclusive, Barriers
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 9fe1500fe0..f8d8660466 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -44,6 +44,7 @@
&bfi !extern rd rn lsb msb
&sat !extern rd rn satimm imm sh
&pkh !extern rd rn rm imm tb
+&cps !extern mode imod M A I F
# Data-processing (register-shifted register)
@@ -340,6 +341,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
HVC 1111 0111 1110 .... 1000 .... .... .... \
&i imm=%imm16_16_0
+ CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
+ &cps
UDF 1111 0111 1111 ---- 1010 ---- ---- ----
}
B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (33 preceding siblings ...)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW Richard Henderson
` (33 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 22 +++++++++++++---------
target/arm/a32-uncond.decode | 4 ++++
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8dbe189df7..1d07caa62a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10135,6 +10135,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a)
return true;
}
+static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ if (a->E != (s->be_data == MO_BE)) {
+ gen_helper_setend(cpu_env);
+ s->base.is_jmp = DISAS_UPDATE;
+ }
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10220,15 +10232,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
return; /* v7MP: Unallocated memory hint: must NOP */
}
- if ((insn & 0x0ffffdff) == 0x01010000) {
- ARCH(6);
- /* setend */
- if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
- s->base.is_jmp = DISAS_UPDATE;
- }
- return;
- } else if ((insn & 0x0e000f00) == 0x0c000100) {
+ if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
if (extract32(s->c15_cpar, 1, 1)) {
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index eb1c55b330..d5ed48f0fd 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -24,6 +24,7 @@
&empty !extern
&i !extern imm
+&setend E
# Branch with Link and Exchange
@@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ----
DMB 1111 0101 0111 1111 1111 0000 0101 ----
ISB 1111 0101 0111 1111 1111 0000 0110 ----
SB 1111 0101 0111 1111 1111 0000 0111 0000
+
+# Set Endianness
+SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (34 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint Richard Henderson
` (32 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 37 +++++++++++++++++++-----------------
target/arm/a32-uncond.decode | 10 ++++++++++
2 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1d07caa62a..5366741d7b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10147,6 +10147,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
return true;
}
+/*
+ * Preload instructions
+ * All are nops, contingent on the appropriate arch level.
+ */
+
+static bool trans_PLD(DisasContext *s, arg_PLD *a)
+{
+ return ENABLE_ARCH_5TE;
+}
+
+static bool trans_PLDW(DisasContext *s, arg_PLD *a)
+{
+ return arm_dc_feature(s, ARM_FEATURE_V7MP);
+}
+
+static bool trans_PLI(DisasContext *s, arg_PLD *a)
+{
+ return ENABLE_ARCH_7;
+}
+
/*
* Legacy decoder.
*/
@@ -10207,23 +10227,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
return;
}
- if (((insn & 0x0f30f000) == 0x0510f000) ||
- ((insn & 0x0f30f010) == 0x0710f000)) {
- if ((insn & (1 << 22)) == 0) {
- /* PLDW; v7MP */
- if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
- goto illegal_op;
- }
- }
- /* Otherwise PLD; v5TE+ */
- ARCH(5TE);
- return;
- }
- if (((insn & 0x0f70f000) == 0x0450f000) ||
- ((insn & 0x0f70f010) == 0x0650f000)) {
- ARCH(7);
- return; /* PLI; V7 */
- }
if (((insn & 0x0f700000) == 0x04100000) ||
((insn & 0x0f700010) == 0x06100000)) {
if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index d5ed48f0fd..aed381cb8e 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000
# Set Endianness
SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend
+
+# Preload instructions
+
+PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te
+PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp
+PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7
+
+PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te
+PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp
+PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (35 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch Richard Henderson
` (31 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 8 --------
target/arm/a32-uncond.decode | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5366741d7b..87cbadc6cb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10227,14 +10227,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
return;
}
- if (((insn & 0x0f700000) == 0x04100000) ||
- ((insn & 0x0f700010) == 0x06100000)) {
- if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
- goto illegal_op;
- }
- return; /* v7MP: Unallocated memory hint: must NOP */
- }
-
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index aed381cb8e..afa95bf7aa 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7
PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te
PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp
PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
+
+# Unallocated memory hints
+#
+# Since these are v7MP nops, and PLDW is v7MP and implemented as nop,
+# (ab)use the PLDW helper.
+
+PLDW 1111 0100 -001 ---- ---- ---- ---- ----
+PLDW 1111 0110 -001 ---- ---- ---- ---0 ----
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (36 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 39/67] target/arm: Convert SG Richard Henderson
` (30 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 62 +++++++++++++++++++++++-------------------
target/arm/t32.decode | 8 +++++-
2 files changed, 41 insertions(+), 29 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 87cbadc6cb..9c6623fb6b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9979,6 +9979,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
+{
+ TCGv_i32 addr, tmp;
+
+ tmp = load_reg(s, a->rm);
+ if (half) {
+ tcg_gen_add_i32(tmp, tmp, tmp);
+ }
+ addr = load_reg(s, a->rn);
+ tcg_gen_add_i32(addr, addr, tmp);
+
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ half ? MO_UW | s->be_data : MO_UB);
+ tcg_temp_free_i32(addr);
+
+ tcg_gen_add_i32(tmp, tmp, tmp);
+ tcg_gen_addi_i32(tmp, tmp, s->pc_read);
+ store_reg(s, 15, tmp);
+ return true;
+}
+
+static bool trans_TBB(DisasContext *s, arg_tbranch *a)
+{
+ return op_tbranch(s, a, false);
+}
+
+static bool trans_TBH(DisasContext *s, arg_tbranch *a)
+{
+ return op_tbranch(s, a, true);
+}
+
/*
* Supervisor call
*/
@@ -10358,9 +10389,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t rd, rn, rm, rs;
- TCGv_i32 tmp;
- TCGv_i32 addr;
+ uint32_t rd, rn, rs;
int op;
/*
@@ -10406,7 +10435,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;
- rm = insn & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
@@ -10479,30 +10507,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Load/store exclusive, in decodetree */
goto illegal_op;
} else if ((insn & (7 << 5)) == 0) {
- /* Table Branch. */
- if (rn == 15) {
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc_read);
- } else {
- addr = load_reg(s, rn);
- }
- tmp = load_reg(s, rm);
- tcg_gen_add_i32(addr, addr, tmp);
- if (insn & (1 << 4)) {
- /* tbh */
- tcg_gen_add_i32(addr, addr, tmp);
- tcg_temp_free_i32(tmp);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
- } else { /* tbb */
- tcg_temp_free_i32(tmp);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
- }
- tcg_temp_free_i32(addr);
- tcg_gen_shli_i32(tmp, tmp, 1);
- tcg_gen_addi_i32(tmp, tmp, s->pc_read);
- store_reg(s, 15, tmp);
+ /* Table Branch, in decodetree */
+ goto illegal_op;
} else {
/* Load/store exclusive, load-acq/store-rel, in decodetree */
goto illegal_op;
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index f8d8660466..17e6dae688 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -487,7 +487,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
-# Load/Store Exclusive and Load-Acquire/Store-Release
+# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch
@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \
&strex rt2=15 imm=%imm8x4
@@ -531,6 +531,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
+&tbranch rn rm
+@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch
+
+TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch
+TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch
+
# Parallel addition and subtraction
SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 39/67] target/arm: Convert SG
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (37 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 40/67] target/arm: Convert TT Richard Henderson
` (29 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 51 ++++++++++++++++++++++++------------------
target/arm/t32.decode | 5 ++++-
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9c6623fb6b..df515e9341 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8497,6 +8497,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a)
return true;
}
+static bool trans_SG(DisasContext *s, arg_SG *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ /*
+ * SG (v8M only)
+ * The bulk of the behaviour for this instruction is implemented
+ * in v7m_handle_execute_nsc(), which deals with the insn when
+ * it is executed by a CPU in non-secure state from memory
+ * which is Secure & NonSecure-Callable.
+ * Here we only need to handle the remaining cases:
+ * * in NS memory (including the "security extension not
+ * implemented" case) : NOP
+ * * in S memory but CPU already secure (clear IT bits)
+ * We know that the attribute for the memory this insn is
+ * in must match the current CPU state, because otherwise
+ * get_phys_addr_pmsav8 would have generated an exception.
+ */
+ if (s->v8m_secure) {
+ /* Like the IT insn, we don't need to generate any code */
+ s->condexec_cond = 0;
+ s->condexec_mask = 0;
+ }
+ return true;
+}
+
/*
* Load/store register index
*/
@@ -10445,28 +10473,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
* - load/store doubleword, load/store exclusive, ldacq/strel,
* table branch, TT.
*/
- if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
- arm_dc_feature(s, ARM_FEATURE_V8)) {
- /* 0b1110_1001_0111_1111_1110_1001_0111_111
- * - SG (v8M only)
- * The bulk of the behaviour for this instruction is implemented
- * in v7m_handle_execute_nsc(), which deals with the insn when
- * it is executed by a CPU in non-secure state from memory
- * which is Secure & NonSecure-Callable.
- * Here we only need to handle the remaining cases:
- * * in NS memory (including the "security extension not
- * implemented" case) : NOP
- * * in S memory but CPU already secure (clear IT bits)
- * We know that the attribute for the memory this insn is
- * in must match the current CPU state, because otherwise
- * get_phys_addr_pmsav8 would have generated an exception.
- */
- if (s->v8m_secure) {
- /* Like the IT insn, we don't need to generate any code */
- s->condexec_cond = 0;
- s->condexec_mask = 0;
- }
- } else if (insn & 0x01200000) {
+ if (insn & 0x01200000) {
/* load/store dual, in decodetree */
goto illegal_op;
} else if ((insn & (1 << 23)) == 0) {
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 17e6dae688..c0b962479b 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -485,7 +485,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1
LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
-LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
+{
+ SG 1110 1001 0111 1111 1110 1001 01111111
+ LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
+}
# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 40/67] target/arm: Convert TT
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (38 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 39/67] target/arm: Convert SG Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn Richard Henderson
` (28 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 88 ++++++++++++++----------------------------
target/arm/t32.decode | 5 ++-
2 files changed, 32 insertions(+), 61 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index df515e9341..a750a2c092 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8525,6 +8525,31 @@ static bool trans_SG(DisasContext *s, arg_SG *a)
return true;
}
+static bool trans_TT(DisasContext *s, arg_TT *a)
+{
+ TCGv_i32 addr, tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ if (a->rd == 13 || a->rd == 15 || a->rn == 15) {
+ /* We UNDEF for these UNPREDICTABLE cases */
+ return false;
+ }
+ if (a->A && !s->v8m_secure) {
+ gen_illegal_op(s);
+ return true;
+ }
+
+ addr = load_reg(s, a->rn);
+ tmp = tcg_const_i32((a->A << 1) | a->T);
+ gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
+ tcg_temp_free_i32(addr);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
/*
* Load/store register index
*/
@@ -10417,7 +10442,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t rd, rn, rs;
+ uint32_t rn;
int op;
/*
@@ -10461,70 +10486,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* fall back to legacy decoder */
rn = (insn >> 16) & 0xf;
- rs = (insn >> 12) & 0xf;
- rd = (insn >> 8) & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
abort();
case 4:
- if (insn & (1 << 22)) {
- /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx
- * - load/store doubleword, load/store exclusive, ldacq/strel,
- * table branch, TT.
- */
- if (insn & 0x01200000) {
- /* load/store dual, in decodetree */
- goto illegal_op;
- } else if ((insn & (1 << 23)) == 0) {
- /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx
- * - load/store exclusive word
- * - TT (v8M only)
- */
- if (rs == 15) {
- if (!(insn & (1 << 20)) &&
- arm_dc_feature(s, ARM_FEATURE_M) &&
- arm_dc_feature(s, ARM_FEATURE_V8)) {
- /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx
- * - TT (v8M only)
- */
- bool alt = insn & (1 << 7);
- TCGv_i32 addr, op, ttresp;
-
- if ((insn & 0x3f) || rd == 13 || rd == 15 || rn == 15) {
- /* we UNDEF for these UNPREDICTABLE cases */
- goto illegal_op;
- }
-
- if (alt && !s->v8m_secure) {
- goto illegal_op;
- }
-
- addr = load_reg(s, rn);
- op = tcg_const_i32(extract32(insn, 6, 2));
- ttresp = tcg_temp_new_i32();
- gen_helper_v7m_tt(ttresp, cpu_env, addr, op);
- tcg_temp_free_i32(addr);
- tcg_temp_free_i32(op);
- store_reg(s, rd, ttresp);
- break;
- }
- goto illegal_op;
- }
- /* Load/store exclusive, in decodetree */
- goto illegal_op;
- } else if ((insn & (7 << 5)) == 0) {
- /* Table Branch, in decodetree */
- goto illegal_op;
- } else {
- /* Load/store exclusive, load-acq/store-rel, in decodetree */
- goto illegal_op;
- }
- } else {
- /* Load/store multiple, RFE, SRS, in decodetree */
- goto illegal_op;
- }
- break;
+ /* All in decodetree */
+ goto illegal_op;
case 5:
/* All in decodetree */
goto illegal_op;
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index c0b962479b..90db05dab6 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -506,7 +506,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \
&ldrex imm=0
-STREX 1110 1000 0100 .... .... .... .... .... @strex_i
+{
+ TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000
+ STREX 1110 1000 0100 .... .... .... .... .... @strex_i
+}
STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0
STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0
STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (39 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 40/67] target/arm: Convert TT Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn Richard Henderson
` (27 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 78 ++----------------------------------------
1 file changed, 3 insertions(+), 75 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a750a2c092..836b3752f7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10442,9 +10442,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t rn;
- int op;
-
/*
* ARMv6-M supports a limited subset of Thumb2 instructions.
* Other Thumb1 architectures allow only 32-bit
@@ -10485,34 +10482,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
/* fall back to legacy decoder */
- rn = (insn >> 16) & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
abort();
- case 4:
- /* All in decodetree */
- goto illegal_op;
- case 5:
- /* All in decodetree */
- goto illegal_op;
- case 13: /* Misc data processing. */
- op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
- if (op < 4 && (insn & 0xf000) != 0xf000)
- goto illegal_op;
- switch (op) {
- case 0: /* Register controlled shift, in decodetree */
- case 1: /* Sign/zero extend, in decodetree */
- case 2: /* SIMD add/subtract, in decodetree */
- case 3: /* Other data processing, in decodetree */
- goto illegal_op;
- case 4: case 5:
- /* 32-bit multiply. Sum of absolute differences, in decodetree */
- goto illegal_op;
- case 6: case 7: /* 64-bit multiply, Divide, in decodetree */
- goto illegal_op;
- }
- break;
case 6: case 7: case 14: case 15:
/* Coprocessor. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
@@ -10541,6 +10514,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
+ uint32_t rn = (insn >> 16) & 0xf;
TCGv_i32 fptr = load_reg(s, rn);
if (extract32(insn, 20, 1)) {
@@ -10599,49 +10573,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
break;
- case 8: case 9: case 10: case 11:
- if (insn & (1 << 15)) {
- /* Branches, misc control. */
- if (insn & 0x5000) {
- /* Unconditional branch, in decodetree */
- goto illegal_op;
- } else if (((insn >> 23) & 7) == 7) {
- /* Misc control */
- if (insn & (1 << 13))
- goto illegal_op;
-
- if (insn & (1 << 26)) {
- /* hvc, smc, in decodetree */
- goto illegal_op;
- } else {
- op = (insn >> 20) & 7;
- switch (op) {
- case 0: /* msr cpsr, in decodetree */
- case 1: /* msr spsr, in decodetree */
- goto illegal_op;
- case 2: /* cps, nop-hint, in decodetree */
- goto illegal_op;
- case 3: /* Special control operations, in decodetree */
- case 4: /* bxj, in decodetree */
- case 5: /* eret, in decodetree */
- case 6: /* MRS, in decodetree */
- case 7: /* MSR, in decodetree */
- goto illegal_op;
- }
- }
- } else {
- /* Conditional branch, in decodetree */
- goto illegal_op;
- }
- } else {
- /*
- * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
- * - Data-processing (modified immediate, plain binary immediate)
- * All in decodetree.
- */
- goto illegal_op;
- }
- break;
case 12:
if ((insn & 0x01100000) == 0x01000000) {
if (disas_neon_ls_insn(s, insn)) {
@@ -10649,14 +10580,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
break;
}
- /* Load/store single data item, in decodetree */
goto illegal_op;
default:
- goto illegal_op;
+ illegal_op:
+ gen_illegal_op(s);
}
- return;
-illegal_op:
- gen_illegal_op(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (40 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree Richard Henderson
` (26 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 69 ++++++++++--------------------------------
1 file changed, 16 insertions(+), 53 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 836b3752f7..65a74a963b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10257,7 +10257,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a)
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, op1;
+ unsigned int cond = insn >> 28;
/* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception.
@@ -10267,7 +10267,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
default_exception_el(s));
return;
}
- cond = insn >> 28;
if (cond == 0xf) {
/* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
@@ -10332,11 +10331,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
goto illegal_op;
}
return;
- } else if ((insn & 0x0fe00000) == 0x0c400000) {
- /* Coprocessor double register transfer. */
- ARCH(5TE);
- } else if ((insn & 0x0f000010) == 0x0e000010) {
- /* Additional coprocessor register transfer. */
}
goto illegal_op;
}
@@ -10348,55 +10342,24 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
/* fall back to legacy decoder */
- if ((insn & 0x0f900000) == 0x03000000) {
- /* All done in decodetree. Illegal ops reach here. */
- goto illegal_op;
- } else if ((insn & 0x0f900000) == 0x01000000
- && (insn & 0x00000090) != 0x00000090) {
- /* miscellaneous instructions */
- /* All done in decodetree. Illegal ops reach here. */
- goto illegal_op;
- } else if (((insn & 0x0e000000) == 0 &&
- (insn & 0x00000090) != 0x90) ||
- ((insn & 0x0e000000) == (1 << 25))) {
- /* Data-processing (reg, reg-shift-reg, imm). */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- } else {
- /* other instructions */
- op1 = (insn >> 24) & 0xf;
- switch(op1) {
- case 0x0:
- case 0x1:
- case 0x4:
- case 0x5:
- case 0x6:
- case 0x7:
- case 0x08:
- case 0x09:
- case 0xa:
- case 0xb:
- case 0xf:
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- case 0xc:
- case 0xd:
- case 0xe:
- if (((insn >> 8) & 0xe) == 10) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- } else if (disas_coproc_insn(s, insn)) {
- /* Coprocessor. */
+ switch ((insn >> 24) & 0xf) {
+ case 0xc:
+ case 0xd:
+ case 0xe:
+ if (((insn >> 8) & 0xe) == 10) {
+ /* VFP. */
+ if (disas_vfp_insn(s, insn)) {
goto illegal_op;
}
- break;
- default:
- illegal_op:
- gen_illegal_op(s);
- break;
+ } else if (disas_coproc_insn(s, insn)) {
+ /* Coprocessor. */
+ goto illegal_op;
}
+ break;
+ default:
+ illegal_op:
+ gen_illegal_op(s);
+ break;
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (41 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
` (25 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 6 ++++++
target/arm/Makefile.objs | 6 ++++++
target/arm/t16.decode | 20 ++++++++++++++++++++
3 files changed, 32 insertions(+)
create mode 100644 target/arm/t16.decode
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 65a74a963b..db93b12608 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7608,6 +7608,7 @@ static int t32_branch24(DisasContext *s, int x)
#include "decode-a32.inc.c"
#include "decode-a32-uncond.inc.c"
#include "decode-t32.inc.c"
+#include "decode-t16.inc.c"
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic pop
@@ -10559,6 +10560,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
TCGv_i32 tmp2;
TCGv_i32 addr;
+ if (disas_t16(s, insn)) {
+ return;
+ }
+ /* fall back to legacy decoder */
+
switch (insn >> 12) {
case 0: case 1:
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 7806b4dac0..cf26c16f5f 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
+target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
+ $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
+ "GEN", $(TARGET_DIR)$@)
+
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
target/arm/translate.o: target/arm/decode-vfp.inc.c
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
target/arm/translate.o: target/arm/decode-a32.inc.c
target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
target/arm/translate.o: target/arm/decode-t32.inc.c
+target/arm/translate.o: target/arm/decode-t16.inc.c
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
new file mode 100644
index 0000000000..e954f61fe4
--- /dev/null
+++ b/target/arm/t16.decode
@@ -0,0 +1,20 @@
+# Thumb1 instructions
+#
+# Copyright (c) 2019 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (42 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) Richard Henderson
` (24 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 152 ++---------------------------------------
target/arm/t16.decode | 36 ++++++++++
2 files changed, 43 insertions(+), 145 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index db93b12608..17a0eea425 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -486,13 +486,6 @@ static inline void gen_logic_CC(TCGv_i32 var)
tcg_gen_mov_i32(cpu_ZF, var);
}
-/* T0 += T1 + CF. */
-static void gen_adc(TCGv_i32 t0, TCGv_i32 t1)
-{
- tcg_gen_add_i32(t0, t0, t1);
- tcg_gen_add_i32(t0, t0, cpu_CF);
-}
-
/* dest = T0 + T1 + CF. */
static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
{
@@ -7590,6 +7583,11 @@ static int t32_branch24(DisasContext *s, int x)
return x << 1;
}
+static int t16_setflags(DisasContext *s, int x)
+{
+ return s->condexec_mask == 0;
+}
+
/*
* Include the generated decoders.
* Note that the T32 decoder reuses some of the trans_* functions
@@ -10751,145 +10749,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/*
* 0b0100_00xx_xxxx_xxxx
- * - Data-processing (two low registers)
+ * - Data-processing (two low registers), in decodetree
*/
- rd = insn & 7;
- rm = (insn >> 3) & 7;
- op = (insn >> 6) & 0xf;
- if (op == 2 || op == 3 || op == 4 || op == 7) {
- /* the shift/rotate ops want the operands backwards */
- val = rm;
- rm = rd;
- rd = val;
- val = 1;
- } else {
- val = 0;
- }
-
- if (op == 9) { /* neg */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else if (op != 0xf) { /* mvn doesn't read its first operand */
- tmp = load_reg(s, rd);
- } else {
- tmp = NULL;
- }
-
- tmp2 = load_reg(s, rm);
- switch (op) {
- case 0x0: /* and */
- tcg_gen_and_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0x1: /* eor */
- tcg_gen_xor_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0x2: /* lsl */
- if (s->condexec_mask) {
- gen_shl(tmp2, tmp2, tmp);
- } else {
- gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x3: /* lsr */
- if (s->condexec_mask) {
- gen_shr(tmp2, tmp2, tmp);
- } else {
- gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x4: /* asr */
- if (s->condexec_mask) {
- gen_sar(tmp2, tmp2, tmp);
- } else {
- gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x5: /* adc */
- if (s->condexec_mask) {
- gen_adc(tmp, tmp2);
- } else {
- gen_adc_CC(tmp, tmp, tmp2);
- }
- break;
- case 0x6: /* sbc */
- if (s->condexec_mask) {
- gen_sub_carry(tmp, tmp, tmp2);
- } else {
- gen_sbc_CC(tmp, tmp, tmp2);
- }
- break;
- case 0x7: /* ror */
- if (s->condexec_mask) {
- tcg_gen_andi_i32(tmp, tmp, 0x1f);
- tcg_gen_rotr_i32(tmp2, tmp2, tmp);
- } else {
- gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x8: /* tst */
- tcg_gen_and_i32(tmp, tmp, tmp2);
- gen_logic_CC(tmp);
- rd = 16;
- break;
- case 0x9: /* neg */
- if (s->condexec_mask)
- tcg_gen_neg_i32(tmp, tmp2);
- else
- gen_sub_CC(tmp, tmp, tmp2);
- break;
- case 0xa: /* cmp */
- gen_sub_CC(tmp, tmp, tmp2);
- rd = 16;
- break;
- case 0xb: /* cmn */
- gen_add_CC(tmp, tmp, tmp2);
- rd = 16;
- break;
- case 0xc: /* orr */
- tcg_gen_or_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xd: /* mul */
- tcg_gen_mul_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xe: /* bic */
- tcg_gen_andc_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xf: /* mvn */
- tcg_gen_not_i32(tmp2, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp2);
- val = 1;
- rm = rd;
- break;
- }
- if (rd != 16) {
- if (val) {
- store_reg(s, rm, tmp2);
- if (op != 0xf)
- tcg_temp_free_i32(tmp);
- } else {
- store_reg(s, rd, tmp);
- tcg_temp_free_i32(tmp2);
- }
- } else {
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- }
- break;
+ goto illegal_op;
case 5:
/* load/store register offset. */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index e954f61fe4..9833fc97e7 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -18,3 +18,39 @@
#
# This file is processed by scripts/decodetree.py
#
+
+&s_rrr_shi !extern s rd rn rm shim shty
+&s_rrr_shr !extern s rn rd rm rs shty
+&s_rri_rot !extern s rn rd imm rot
+&s_rrrr !extern s rd rn rm ra
+
+# Set S if the instruction is outside of an IT block.
+%s !function=t16_setflags
+
+# Data-processing (two low registers)
+
+%reg_0 0:3
+
+@lll_noshr ...... .... rm:3 rd:3 \
+ &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
+@xll_noshr ...... .... rm:3 rn:3 \
+ &s_rrr_shi s=1 rd=0 shim=0 shty=0
+@lxl_shr ...... .... rs:3 rd:3 \
+ &s_rrr_shr %s rm=%reg_0 rn=0
+
+AND_rrri 010000 0000 ... ... @lll_noshr
+EOR_rrri 010000 0001 ... ... @lll_noshr
+MOV_rrrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
+MOV_rrrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
+MOV_rrrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
+ADC_rrri 010000 0101 ... ... @lll_noshr
+SBC_rrri 010000 0110 ... ... @lll_noshr
+MOV_rrrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
+TST_rrri 010000 1000 ... ... @xll_noshr
+RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
+CMP_rrri 010000 1010 ... ... @xll_noshr
+CMN_rrri 010000 1011 ... ... @xll_noshr
+ORR_rrri 010000 1100 ... ... @lll_noshr
+MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
+BIC_rrri 010000 1110 ... ... @lll_noshr
+MVN_rrri 010000 1111 ... ... @lll_noshr
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (43 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
` (23 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 51 ++----------------------------------------
target/arm/t16.decode | 15 +++++++++++++
2 files changed, 17 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 17a0eea425..7b87621315 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10754,55 +10754,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
case 5:
- /* load/store register offset. */
- rd = insn & 7;
- rn = (insn >> 3) & 7;
- rm = (insn >> 6) & 7;
- op = (insn >> 9) & 7;
- addr = load_reg(s, rn);
- tmp = load_reg(s, rm);
- tcg_gen_add_i32(addr, addr, tmp);
- tcg_temp_free_i32(tmp);
-
- if (op < 3) { /* store */
- tmp = load_reg(s, rd);
- } else {
- tmp = tcg_temp_new_i32();
- }
-
- switch (op) {
- case 0: /* str */
- gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 1: /* strh */
- gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 2: /* strb */
- gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 3: /* ldrsb */
- gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 4: /* ldr */
- gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 5: /* ldrh */
- gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 6: /* ldrb */
- gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- case 7: /* ldrsh */
- gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- break;
- }
- if (op >= 3) { /* load */
- store_reg(s, rd, tmp);
- } else {
- tcg_temp_free_i32(tmp);
- }
- tcg_temp_free_i32(addr);
- break;
+ /* load/store register offset, in decodetree */
+ goto illegal_op;
case 6:
/* load/store word immediate offset */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 9833fc97e7..567c5005d6 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
+&ldst_rr !extern p w u rn rt rm shimm shtype
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_noshr
MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
BIC_rrri 010000 1110 ... ... @lll_noshr
MVN_rrri 010000 1111 ... ... @lll_noshr
+
+# Load/store (register offset)
+
+@ldst_rr ....... rm:3 rn:3 rt:3 \
+ &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
+
+STR_rr 0101 000 ... ... ... @ldst_rr
+STRH_rr 0101 001 ... ... ... @ldst_rr
+STRB_rr 0101 010 ... ... ... @ldst_rr
+LDRSB_rr 0101 011 ... ... ... @ldst_rr
+LDR_rr 0101 100 ... ... ... @ldst_rr
+LDRH_rr 0101 101 ... ... ... @ldst_rr
+LDRB_rr 0101 110 ... ... ... @ldst_rr
+LDRSH_rr 0101 111 ... ... ... @ldst_rr
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (44 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
` (22 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 94 +++---------------------------------------
target/arm/t16.decode | 33 +++++++++++++++
2 files changed, 38 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7b87621315..28f274ca7c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10753,97 +10753,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
*/
goto illegal_op;
- case 5:
- /* load/store register offset, in decodetree */
+ case 5: /* load/store register offset, in decodetree */
+ case 6: /* load/store word immediate offset, in decodetree */
+ case 7: /* load/store byte immediate offset, in decodetree */
+ case 8: /* load/store halfword immediate offset, in decodetree */
+ case 9: /* load/store from stack, in decodetree */
goto illegal_op;
- case 6:
- /* load/store word immediate offset */
- rd = insn & 7;
- rn = (insn >> 3) & 7;
- addr = load_reg(s, rn);
- val = (insn >> 4) & 0x7c;
- tcg_gen_addi_i32(addr, addr, val);
-
- if (insn & (1 << 11)) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- store_reg(s, rd, tmp);
- } else {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- tcg_temp_free_i32(addr);
- break;
-
- case 7:
- /* load/store byte immediate offset */
- rd = insn & 7;
- rn = (insn >> 3) & 7;
- addr = load_reg(s, rn);
- val = (insn >> 6) & 0x1f;
- tcg_gen_addi_i32(addr, addr, val);
-
- if (insn & (1 << 11)) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- store_reg(s, rd, tmp);
- } else {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- tcg_temp_free_i32(tmp);
- }
- tcg_temp_free_i32(addr);
- break;
-
- case 8:
- /* load/store halfword immediate offset */
- rd = insn & 7;
- rn = (insn >> 3) & 7;
- addr = load_reg(s, rn);
- val = (insn >> 5) & 0x3e;
- tcg_gen_addi_i32(addr, addr, val);
-
- if (insn & (1 << 11)) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- store_reg(s, rd, tmp);
- } else {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- tcg_temp_free_i32(tmp);
- }
- tcg_temp_free_i32(addr);
- break;
-
- case 9:
- /* load/store from stack */
- rd = (insn >> 8) & 7;
- addr = load_reg(s, 13);
- val = (insn & 0xff) * 4;
- tcg_gen_addi_i32(addr, addr, val);
-
- if (insn & (1 << 11)) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- store_reg(s, rd, tmp);
- } else {
- /* store */
- tmp = load_reg(s, rd);
- gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
- tcg_temp_free_i32(tmp);
- }
- tcg_temp_free_i32(addr);
- break;
-
case 10:
/*
* 0b1010_xxxx_xxxx_xxxx
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 567c5005d6..797e4e7068 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -24,6 +24,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&ldst_rr !extern p w u rn rt rm shimm shtype
+&ldst_ri !extern p w u rn rt imm
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr
LDRH_rr 0101 101 ... ... ... @ldst_rr
LDRB_rr 0101 110 ... ... ... @ldst_rr
LDRSH_rr 0101 111 ... ... ... @ldst_rr
+
+# Load/store word/byte (immediate offset)
+
+%imm5_6x4 6:5 !function=times_4
+
+@ldst_ri_1 ..... imm:5 rn:3 rt:3 \
+ &ldst_ri p=1 w=0 u=1
+@ldst_ri_4 ..... ..... rn:3 rt:3 \
+ &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
+
+STR_ri 01100 ..... ... ... @ldst_ri_4
+LDR_ri 01101 ..... ... ... @ldst_ri_4
+STRB_ri 01110 ..... ... ... @ldst_ri_1
+LDRB_ri 01111 ..... ... ... @ldst_ri_1
+
+# Load/store halfword (immediate offset)
+
+%imm5_6x2 6:5 !function=times_2
+@ldst_ri_2 ..... ..... rn:3 rt:3 \
+ &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
+
+STRH_ri 10000 ..... ... ... @ldst_ri_2
+LDRH_ri 10001 ..... ... ... @ldst_ri_2
+
+# Load/store (SP-relative)
+
+%imm8_0x4 0:8 !function=times_4
+@ldst_spec_i ..... rt:3 ........ \
+ &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
+
+STR_ri 10010 ... ........ @ldst_spec_i rn=13
+LDR_ri 10011 ... ........ @ldst_spec_i rn=13
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (45 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple Richard Henderson
` (21 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 12 +-----------
target/arm/t16.decode | 7 +++++++
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 28f274ca7c..525276ed13 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10758,19 +10758,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 7: /* load/store byte immediate offset, in decodetree */
case 8: /* load/store halfword immediate offset, in decodetree */
case 9: /* load/store from stack, in decodetree */
+ case 10: /* add PC/SP (immediate), in decodetree */
goto illegal_op;
- case 10:
- /*
- * 0b1010_xxxx_xxxx_xxxx
- * - Add PC/SP (immediate)
- */
- rd = (insn >> 8) & 7;
- val = (insn & 0xff) * 4;
- tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
- store_reg(s, rd, tmp);
- break;
-
case 11:
/* misc */
op = (insn >> 8) & 0xf;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 797e4e7068..568656ecd6 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
+&ri !extern rd imm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
@@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2
STR_ri 10010 ... ........ @ldst_spec_i rn=13
LDR_ri 10011 ... ........ @ldst_spec_i rn=13
+
+# Add PC/SP (immediate)
+
+ADR 10100 rd:3 ........ imm=%imm8_0x4
+ADD_rri 10101 rd:3 ........ \
+ &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (46 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
` (20 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 47 +++++++-----------------------------------
target/arm/t16.decode | 8 +++++++
2 files changed, 16 insertions(+), 39 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 525276ed13..f551fde3db 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9988,6 +9988,13 @@ static bool trans_LDM(DisasContext *s, arg_ldst_block *a)
return true;
}
+static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
+{
+ /* Writeback is conditional on the base register not being loaded. */
+ a->w = !(a->list & (1 << a->rn));
+ return trans_LDM(s, a);
+}
+
/*
* Branch, branch with link
*/
@@ -10759,6 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 8: /* load/store halfword immediate offset, in decodetree */
case 9: /* load/store from stack, in decodetree */
case 10: /* add PC/SP (immediate), in decodetree */
+ case 12: /* load/store multiple, in decodetree */
goto illegal_op;
case 11:
@@ -10984,45 +10992,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
}
break;
- case 12:
- {
- /* load/store multiple */
- TCGv_i32 loaded_var = NULL;
- rn = (insn >> 8) & 0x7;
- addr = load_reg(s, rn);
- for (i = 0; i < 8; i++) {
- if (insn & (1 << i)) {
- if (insn & (1 << 11)) {
- /* load */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- if (i == rn) {
- loaded_var = tmp;
- } else {
- store_reg(s, i, tmp);
- }
- } else {
- /* store */
- tmp = load_reg(s, i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- /* advance to the next address */
- tcg_gen_addi_i32(addr, addr, 4);
- }
- }
- if ((insn & (1 << rn)) == 0) {
- /* base reg not in list: base register writeback */
- store_reg(s, rn, addr);
- } else {
- /* base reg in list: if load, complete it now */
- if (insn & (1 << 11)) {
- store_reg(s, rn, loaded_var);
- }
- tcg_temp_free_i32(addr);
- }
- break;
- }
case 13:
/* conditional branch or swi */
cond = (insn >> 8) & 0xf;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 568656ecd6..67476b30dc 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -26,6 +26,7 @@
&ri !extern rd imm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
+&ldst_block !extern rn i b u w list
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_spec_i rn=13
ADR 10100 rd:3 ........ imm=%imm8_0x4
ADD_rri 10101 rd:3 ........ \
&s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
+
+# Load/store multiple
+
+@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
+
+STM 11000 ... ........ @ldstm
+LDM_t16 11001 ... ........ @ldstm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (47 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate Richard Henderson
` (19 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 26 ++------------------------
target/arm/t16.decode | 16 ++++++++++++++++
2 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f551fde3db..692891dbe0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10580,31 +10580,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
* 0b0001_1xxx_xxxx_xxxx
* - Add, subtract (three low registers)
* - Add, subtract (two low registers and immediate)
+ * In decodetree.
*/
- rn = (insn >> 3) & 7;
- tmp = load_reg(s, rn);
- if (insn & (1 << 10)) {
- /* immediate */
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
- } else {
- /* reg */
- rm = (insn >> 6) & 7;
- tmp2 = load_reg(s, rm);
- }
- if (insn & (1 << 9)) {
- if (s->condexec_mask)
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- else
- gen_sub_CC(tmp, tmp, tmp2);
- } else {
- if (s->condexec_mask)
- tcg_gen_add_i32(tmp, tmp, tmp2);
- else
- gen_add_CC(tmp, tmp, tmp2);
- }
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
+ goto illegal_op;
} else {
/* shift immediate */
rm = (insn >> 3) & 7;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 67476b30dc..965fb1bf6e 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \
STM 11000 ... ........ @ldstm
LDM_t16 11001 ... ........ @ldstm
+
+# Add/subtract (three low registers)
+
+@addsub_3 ....... rm:3 rn:3 rd:3 \
+ &s_rrr_shi %s shim=0 shty=0
+
+ADD_rrri 0001100 ... ... ... @addsub_3
+SUB_rrri 0001101 ... ... ... @addsub_3
+
+# Add/subtract (two low registers and immediate)
+
+@addsub_2i ....... imm:3 rn:3 rd:3 \
+ &s_rri_rot %s rot=0
+
+ADD_rri 0001 110 ... ... ... @addsub_2i
+SUB_rri 0001 111 ... ... ... @addsub_2i
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (48 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange Richard Henderson
` (18 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 44 ++----------------------------------------
target/arm/t16.decode | 11 +++++++++++
2 files changed, 13 insertions(+), 42 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 692891dbe0..9bdcb91537 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10594,48 +10594,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
store_reg(s, rd, tmp);
}
break;
- case 2: case 3:
- /*
- * 0b001x_xxxx_xxxx_xxxx
- * - Add, subtract, compare, move (one low register and immediate)
- */
- op = (insn >> 11) & 3;
- rd = (insn >> 8) & 0x7;
- if (op == 0) { /* mov */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, insn & 0xff);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
- } else {
- tmp = load_reg(s, rd);
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, insn & 0xff);
- switch (op) {
- case 1: /* cmp */
- gen_sub_CC(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- break;
- case 2: /* add */
- if (s->condexec_mask)
- tcg_gen_add_i32(tmp, tmp, tmp2);
- else
- gen_add_CC(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
- case 3: /* sub */
- if (s->condexec_mask)
- tcg_gen_sub_i32(tmp, tmp, tmp2);
- else
- gen_sub_CC(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
- }
- }
- break;
+ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
+ goto illegal_op;
case 4:
if (insn & (1 << 11)) {
rd = (insn >> 8) & 7;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 965fb1bf6e..edb67a3896 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3
ADD_rri 0001 110 ... ... ... @addsub_2i
SUB_rri 0001 111 ... ... ... @addsub_2i
+
+# Add, subtract, compare, move (one low register and immediate)
+
+%reg_8 8:3
+@arith_1i ..... rd:3 imm:8 \
+ &s_rri_rot rot=0 rn=%reg_8
+
+MOV_rri 00100 ... ........ @arith_1i %s
+CMP_rri 00101 ... ........ @arith_1i s=1
+ADD_rri 00110 ... ........ @arith_1i %s
+SUB_rri 00111 ... ........ @arith_1i %s
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (49 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
` (17 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 64 +++++++++++++++---------------------------
target/arm/t16.decode | 10 +++++++
2 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9bdcb91537..e2183eb543 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8406,7 +8406,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a)
if (!ENABLE_ARCH_4T) {
return false;
}
- gen_bx(s, load_reg(s, a->rm));
+ gen_bx_excret(s, load_reg(s, a->rm));
return true;
}
@@ -8433,6 +8433,26 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a)
return true;
}
+static bool trans_BXNS(DisasContext *s, arg_BXNS *a)
+{
+ if (!s->v8m_secure || IS_USER_ONLY) {
+ gen_illegal_op(s);
+ } else {
+ gen_bxns(s, a->rm);
+ }
+ return true;
+}
+
+static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a)
+{
+ if (!s->v8m_secure || IS_USER_ONLY) {
+ gen_illegal_op(s);
+ } else {
+ gen_blxns(s, a->rm);
+ }
+ return true;
+}
+
static bool trans_CLZ(DisasContext *s, arg_CLZ *a)
{
TCGv_i32 tmp;
@@ -10645,49 +10665,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
}
break;
case 3:
- {
/* 0b0100_0111_xxxx_xxxx
* - branch [and link] exchange thumb register
+ * In decodetree
*/
- bool link = insn & (1 << 7);
-
- if (insn & 3) {
- goto undef;
- }
- if (link) {
- ARCH(5);
- }
- if ((insn & 4)) {
- /* BXNS/BLXNS: only exists for v8M with the
- * security extensions, and always UNDEF if NonSecure.
- * We don't implement these in the user-only mode
- * either (in theory you can use them from Secure User
- * mode but they are too tied in to system emulation.)
- */
- if (!s->v8m_secure || IS_USER_ONLY) {
- goto undef;
- }
- if (link) {
- gen_blxns(s, rm);
- } else {
- gen_bxns(s, rm);
- }
- break;
- }
- /* BLX/BX */
- tmp = load_reg(s, rm);
- if (link) {
- val = (uint32_t)s->pc | 1;
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, val);
- store_reg(s, 14, tmp2);
- gen_bx(s, tmp);
- } else {
- /* Only BX works as exception-return, not BLX */
- gen_bx_excret(s, tmp);
- }
- break;
- }
+ goto illegal_op;
}
break;
}
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index edb67a3896..4701f72357 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -24,6 +24,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&ri !extern rd imm
+&r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list
@@ -144,3 +145,12 @@ MOV_rri 00100 ... ........ @arith_1i %s
CMP_rri 00101 ... ........ @arith_1i s=1
ADD_rri 00110 ... ........ @arith_1i %s
SUB_rri 00111 ... ........ @arith_1i %s
+
+# Branch and exchange
+
+@branchr .... .... . rm:4 ... &r
+
+BX 0100 0111 0 .... 000 @branchr
+BLX_r 0100 0111 1 .... 000 @branchr
+BXNS 0100 0111 0 .... 100 @branchr
+BLXNS 0100 0111 1 .... 100 @branchr
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (50 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
` (16 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 49 ++----------------------------------------
target/arm/t16.decode | 10 +++++++++
2 files changed, 12 insertions(+), 47 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e2183eb543..23f5f982f5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10628,55 +10628,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
store_reg(s, rd, tmp);
break;
}
- if (insn & (1 << 10)) {
- /* 0b0100_01xx_xxxx_xxxx
- * - data processing extended, branch and exchange
- */
- rd = (insn & 7) | ((insn >> 4) & 8);
- rm = (insn >> 3) & 0xf;
- op = (insn >> 8) & 3;
- switch (op) {
- case 0: /* add */
- tmp = load_reg(s, rd);
- tmp2 = load_reg(s, rm);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rd == 13) {
- /* ADD SP, SP, reg */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
- break;
- case 1: /* cmp */
- tmp = load_reg(s, rd);
- tmp2 = load_reg(s, rm);
- gen_sub_CC(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- break;
- case 2: /* mov/cpy */
- tmp = load_reg(s, rm);
- if (rd == 13) {
- /* MOV SP, reg */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
- break;
- case 3:
- /* 0b0100_0111_xxxx_xxxx
- * - branch [and link] exchange thumb register
- * In decodetree
- */
- goto illegal_op;
- }
- break;
- }
/*
- * 0b0100_00xx_xxxx_xxxx
- * - Data-processing (two low registers), in decodetree
+ * - Data-processing (two low registers), in decodetree
+ * - data processing extended, branch and exchange, in decodetree
*/
goto illegal_op;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 4701f72357..69d3894ba7 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -146,6 +146,16 @@ CMP_rri 00101 ... ........ @arith_1i s=1
ADD_rri 00110 ... ........ @arith_1i %s
SUB_rri 00111 ... ........ @arith_1i %s
+# Add, compare, move (two high registers)
+
+%reg_0_7 7:1 0:3
+@addsub_2h .... .... . rm:4 ... \
+ &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
+
+ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
+CMP_rrri 0100 0101 . .... ... @addsub_2h s=1
+MOV_rrri 0100 0110 . .... ... @addsub_2h s=0
+
# Branch and exchange
@branchr .... .... . rm:4 ... &r
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (51 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract Richard Henderson
` (15 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 15 ++-------------
target/arm/t16.decode | 9 +++++++++
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 23f5f982f5..8dd88419fe 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10648,19 +10648,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/* misc */
op = (insn >> 8) & 0xf;
switch (op) {
- case 0:
- /*
- * 0b1011_0000_xxxx_xxxx
- * - ADD (SP plus immediate)
- * - SUB (SP minus immediate)
- */
- tmp = load_reg(s, 13);
- val = (insn & 0x7f) * 4;
- if (insn & (1 << 7))
- val = -(int32_t)val;
- tcg_gen_addi_i32(tmp, tmp, val);
- store_sp_checked(s, tmp);
- break;
+ case 0: /* add/sub (sp, immediate), in decodetree */
+ goto illegal_op;
case 2: /* sign/zero extend. */
ARCH(6);
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 69d3894ba7..ddf12ada11 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
CMP_rrri 0100 0101 . .... ... @addsub_2h s=1
MOV_rrri 0100 0110 . .... ... @addsub_2h s=0
+# Adjust SP (immediate)
+
+%imm7_0x4 0:7 !function=times_4
+@addsub_sp_i .... .... . ....... \
+ &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
+
+ADD_rri 1011 0000 0 ....... @addsub_sp_i
+SUB_rri 1011 0000 1 ....... @addsub_sp_i
+
# Branch and exchange
@branchr .... .... . rm:4 ... &r
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (52 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state Richard Henderson
` (14 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 14 +-------------
target/arm/t16.decode | 10 ++++++++++
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8dd88419fe..9c8e11bd3a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10649,21 +10649,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
op = (insn >> 8) & 0xf;
switch (op) {
case 0: /* add/sub (sp, immediate), in decodetree */
+ case 2: /* sign/zero extend, in decodetree */
goto illegal_op;
- case 2: /* sign/zero extend. */
- ARCH(6);
- rd = insn & 7;
- rm = (insn >> 3) & 7;
- tmp = load_reg(s, rm);
- switch ((insn >> 6) & 3) {
- case 0: gen_sxth(tmp); break;
- case 1: gen_sxtb(tmp); break;
- case 2: gen_uxth(tmp); break;
- case 3: gen_uxtb(tmp); break;
- }
- store_reg(s, rd, tmp);
- break;
case 4: case 5: case 0xc: case 0xd:
/*
* 0b1011_x10x_xxxx_xxxx
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index ddf12ada11..1b47e804bf 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
+&rrr_rot !extern rd rn rm rot
&ri !extern rd imm
&r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype
@@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr
BLX_r 0100 0111 1 .... 000 @branchr
BXNS 0100 0111 0 .... 100 @branchr
BLXNS 0100 0111 1 .... 100 @branchr
+
+# Extend
+
+@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
+
+SXTAH 1011 0010 00 ... ... @extend
+SXTAB 1011 0010 01 ... ... @extend
+UXTAH 1011 0010 10 ... ... @extend
+UXTAB 1011 0010 11 ... ... @extend
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (53 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes Richard Henderson
` (13 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 85 ++++++++++++++++++++----------------------
target/arm/t16.decode | 12 ++++++
2 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9c8e11bd3a..8f2adbbc7d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7531,6 +7531,11 @@ static int negate(DisasContext *s, int x)
return -x;
}
+static int plus_2(DisasContext *s, int x)
+{
+ return x + 2;
+}
+
static int times_2(DisasContext *s, int x)
{
return x * 2;
@@ -10163,6 +10168,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
{
uint32_t mask, val;
+ if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
if (IS_USER(s)) {
/* Implemented as NOP in user mode. */
return true;
@@ -10193,6 +10201,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
return true;
}
+static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a)
+{
+ TCGv_i32 tmp, addr;
+
+ if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) {
+ return false;
+ }
+ if (IS_USER(s)) {
+ /* Implemented as NOP in user mode. */
+ return true;
+ }
+
+ tmp = tcg_const_i32(a->im);
+ /* FAULTMASK */
+ if (a->F) {
+ addr = tcg_const_i32(19);
+ gen_helper_v7m_msr(cpu_env, addr, tmp);
+ tcg_temp_free_i32(addr);
+ }
+ /* PRIMASK */
+ if (a->I) {
+ addr = tcg_const_i32(16);
+ gen_helper_v7m_msr(cpu_env, addr, tmp);
+ tcg_temp_free_i32(addr);
+ }
+ tcg_temp_free_i32(tmp);
+ gen_lookup_tb(s);
+ return true;
+}
+
/*
* Clear-Exclusive, Barriers
*/
@@ -10793,51 +10831,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
break;
}
- case 6:
- switch ((insn >> 5) & 7) {
- case 2:
- /* setend */
- ARCH(6);
- if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
- s->base.is_jmp = DISAS_UPDATE;
- }
- break;
- case 3:
- /* cps */
- ARCH(6);
- if (IS_USER(s)) {
- break;
- }
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- tmp = tcg_const_i32((insn & (1 << 4)) != 0);
- /* FAULTMASK */
- if (insn & 1) {
- addr = tcg_const_i32(19);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
- tcg_temp_free_i32(addr);
- }
- /* PRIMASK */
- if (insn & 2) {
- addr = tcg_const_i32(16);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
- tcg_temp_free_i32(addr);
- }
- tcg_temp_free_i32(tmp);
- gen_lookup_tb(s);
- } else {
- if (insn & (1 << 4)) {
- shift = CPSR_A | CPSR_I | CPSR_F;
- } else {
- shift = 0;
- }
- gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
- }
- break;
- default:
- goto undef;
- }
- break;
+ case 6: /* setend, cps; in decodetree */
+ goto illegal_op;
default:
goto undef;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 1b47e804bf..f43ea6ce20 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -29,6 +29,8 @@
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list
+&setend !extern E
+&cps !extern mode imod M A I F
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend
SXTAB 1011 0010 01 ... ... @extend
UXTAH 1011 0010 10 ... ... @extend
UXTAB 1011 0010 11 ... ... @extend
+
+# Change processor state
+
+%imod 4:1 !function=plus_2
+
+SETEND 1011 0110 010 1 E:1 000 &setend
+{
+ CPS_v6m 1011 0110 011 im:1 00 I:1 F:1
+ CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (54 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints Richard Henderson
` (12 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 18 +++---------------
target/arm/t16.decode | 9 +++++++++
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f2adbbc7d..c9386ceefb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10616,7 +10616,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, op, rm, rn, rd, shift, cond;
+ uint32_t val, op, rm, rd, shift, cond;
int32_t offset;
int i;
TCGv_i32 tmp;
@@ -10815,20 +10815,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
break;
}
- /* Otherwise this is rev */
- ARCH(6);
- rn = (insn >> 3) & 0x7;
- rd = insn & 0x7;
- tmp = load_reg(s, rn);
- switch (op1) {
- case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
- case 1: gen_rev16(tmp, tmp); break;
- case 3: gen_revsh(tmp, tmp); break;
- default:
- g_assert_not_reached();
- }
- store_reg(s, rd, tmp);
- break;
+ /* Otherwise this is rev, in decodetree */
+ goto illegal_op;
}
case 6: /* setend, cps; in decodetree */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index f43ea6ce20..8864f89a81 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -24,6 +24,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&rrr_rot !extern rd rn rm rot
+&rr !extern rd rm
&ri !extern rd imm
&r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype
@@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend
CPS_v6m 1011 0110 011 im:1 00 I:1 F:1
CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
}
+
+# Reverse bytes
+
+@rdm .... .... .. rm:3 rd:3 &rr
+
+REV 1011 1010 00 ... ... @rdm
+REV16 1011 1010 01 ... ... @rdm
+REVSH 1011 1010 11 ... ... @rdm
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (55 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop Richard Henderson
` (11 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 3 +--
target/arm/t16.decode | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c9386ceefb..55404414a2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10779,8 +10779,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 15: /* IT, nop-hint. */
if ((insn & 0xf) == 0) {
- gen_nop_hint(s, (insn >> 4) & 0xf);
- break;
+ goto illegal_op; /* nop hint, in decodetree */
}
/*
* IT (If-Then)
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 8864f89a81..90a4b71a45 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -19,6 +19,7 @@
# This file is processed by scripts/decodetree.py
#
+&empty !extern
&s_rrr_shi !extern s rd rn rm shim shty
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
@@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend
REV 1011 1010 00 ... ... @rdm
REV16 1011 1010 01 ... ... @rdm
REVSH 1011 1010 11 ... ... @rdm
+
+# Hints
+
+{
+ YIELD 1011 1111 0001 0000
+ WFE 1011 1111 0010 0000
+ WFI 1011 1111 0011 0000
+
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1011 1111 0100 0000
+ # SEVL 1011 1111 0101 0000
+
+ # The canonical nop has the second nibble as 0000, but the whole of the
+ # rest of the space is a reserved hint, behaves as nop.
+ NOP 1011 1111 ---- 0000
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (56 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
` (10 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 83 ++++++------------------------------------
target/arm/t16.decode | 10 +++++
2 files changed, 22 insertions(+), 71 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 55404414a2..5d0d0779c8 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7593,6 +7593,16 @@ static int t16_setflags(DisasContext *s, int x)
return s->condexec_mask == 0;
}
+static int t16_push_list(DisasContext *s, int x)
+{
+ return (x & 0xff) | (x & 0x100) << (14 - 8);
+}
+
+static int t16_pop_list(DisasContext *s, int x)
+{
+ return (x & 0xff) | (x & 0x100) << (15 - 8);
+}
+
/*
* Include the generated decoders.
* Note that the T32 decoder reuses some of the trans_* functions
@@ -10618,7 +10628,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
uint32_t val, op, rm, rd, shift, cond;
int32_t offset;
- int i;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
@@ -10691,76 +10700,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
case 4: case 5: case 0xc: case 0xd:
- /*
- * 0b1011_x10x_xxxx_xxxx
- * - push/pop
- */
- addr = load_reg(s, 13);
- if (insn & (1 << 8))
- offset = 4;
- else
- offset = 0;
- for (i = 0; i < 8; i++) {
- if (insn & (1 << i))
- offset += 4;
- }
- if ((insn & (1 << 11)) == 0) {
- tcg_gen_addi_i32(addr, addr, -offset);
- }
-
- if (s->v8m_stackcheck) {
- /*
- * Here 'addr' is the lower of "old SP" and "new SP";
- * if this is a pop that starts below the limit and ends
- * above it, it is UNKNOWN whether the limit check triggers;
- * we choose to trigger.
- */
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
-
- for (i = 0; i < 8; i++) {
- if (insn & (1 << i)) {
- if (insn & (1 << 11)) {
- /* pop */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- store_reg(s, i, tmp);
- } else {
- /* push */
- tmp = load_reg(s, i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- /* advance to the next address. */
- tcg_gen_addi_i32(addr, addr, 4);
- }
- }
- tmp = NULL;
- if (insn & (1 << 8)) {
- if (insn & (1 << 11)) {
- /* pop pc */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- /* don't set the pc until the rest of the instruction
- has completed */
- } else {
- /* push lr */
- tmp = load_reg(s, 14);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_addi_i32(addr, addr, 4);
- }
- if ((insn & (1 << 11)) == 0) {
- tcg_gen_addi_i32(addr, addr, -offset);
- }
- /* write back the new stack pointer */
- store_reg(s, 13, addr);
- /* set the new PC value */
- if ((insn & 0x0900) == 0x0900) {
- store_reg_from_load(s, 15, tmp);
- }
- break;
+ /* push/pop, in decodetree */
+ goto illegal_op;
case 1: case 3: case 9: case 11: /* czb */
rm = insn & 7;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 90a4b71a45..10cdca1fbb 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm
# rest of the space is a reserved hint, behaves as nop.
NOP 1011 1111 ---- 0000
}
+
+# Push and Pop
+
+%push_list 0:9 !function=t16_push_list
+%pop_list 0:9 !function=t16_pop_list
+
+STM 1011 010 ......... \
+ &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
+LDM 1011 110 ......... \
+ &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (57 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
` (9 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 26 +++-----------------------
target/arm/t16.decode | 12 ++++++++++++
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5d0d0779c8..97c472c8f7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10626,7 +10626,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, op, rm, rd, shift, cond;
+ uint32_t val, op, rm, rd, shift;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10767,28 +10767,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
}
break;
- case 13:
- /* conditional branch or swi */
- cond = (insn >> 8) & 0xf;
- if (cond == 0xe)
- goto undef;
-
- if (cond == 0xf) {
- /* swi */
- gen_set_pc_im(s, s->pc);
- s->svc_imm = extract32(insn, 0, 8);
- s->base.is_jmp = DISAS_SWI;
- break;
- }
- /* generate a conditional jump to next instruction */
- arm_skip_unless(s, cond);
-
- /* jump to the offset */
- val = s->pc_read;
- offset = ((int32_t)insn << 24) >> 24;
- val += offset << 1;
- gen_jmp(s, val);
- break;
+ case 13: /* conditional branch or swi, in decodetree */
+ goto illegal_op;
case 14:
if (insn & (1 << 11)) {
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 10cdca1fbb..f4091c812d 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -28,11 +28,13 @@
&rr !extern rd rm
&ri !extern rd imm
&r !extern rm
+&i !extern imm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list
&setend !extern E
&cps !extern mode imod M A I F
+&ci !extern cond imm
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -231,3 +233,13 @@ STM 1011 010 ......... \
&ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
LDM 1011 110 ......... \
&ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
+
+# Conditional branches, Supervisor call
+
+%imm8_0x2 0:s8 !function=times_2
+
+{
+ UDF 1101 1110 ---- ----
+ SVC 1101 1111 imm:8 &i
+ B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (58 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate Richard Henderson
` (8 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 111 ++++++++++++-----------------------------
target/arm/t16.decode | 31 ++++++++----
2 files changed, 54 insertions(+), 88 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 97c472c8f7..f3a946d8c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10104,6 +10104,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch *a)
return op_tbranch(s, a, true);
}
+static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
+{
+ TCGv_i32 tmp = load_reg(s, a->rn);
+
+ arm_gen_condlabel(s);
+ tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
+ tmp, 0, s->condlabel);
+ tcg_temp_free_i32(tmp);
+ gen_jmp(s, s->pc_read + a->imm);
+ return true;
+}
+
/*
* Supervisor call
*/
@@ -10325,6 +10337,25 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a)
return ENABLE_ARCH_7;
}
+/*
+ * If-then
+ */
+
+static bool trans_IT(DisasContext *s, arg_IT *a)
+{
+ /*
+ * No actual code generated for this insn, just setup state.
+ *
+ * Combinations of firstcond and mask which set up an 0b1111
+ * condition are UNPREDICTABLE; we take the CONSTRAINED
+ * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,
+ * i.e. both meaning "execute always".
+ */
+ s->condexec_cond = a->cond;
+ s->condexec_mask = a->imm;
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10688,85 +10719,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 8: /* load/store halfword immediate offset, in decodetree */
case 9: /* load/store from stack, in decodetree */
case 10: /* add PC/SP (immediate), in decodetree */
+ case 11: /* misc, in decodetree */
case 12: /* load/store multiple, in decodetree */
- goto illegal_op;
-
- case 11:
- /* misc */
- op = (insn >> 8) & 0xf;
- switch (op) {
- case 0: /* add/sub (sp, immediate), in decodetree */
- case 2: /* sign/zero extend, in decodetree */
- goto illegal_op;
-
- case 4: case 5: case 0xc: case 0xd:
- /* push/pop, in decodetree */
- goto illegal_op;
-
- case 1: case 3: case 9: case 11: /* czb */
- rm = insn & 7;
- tmp = load_reg(s, rm);
- arm_gen_condlabel(s);
- if (insn & (1 << 11))
- tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
- else
- tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
- tcg_temp_free_i32(tmp);
- offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
- val = s->pc_read;
- val += offset;
- gen_jmp(s, val);
- break;
-
- case 15: /* IT, nop-hint. */
- if ((insn & 0xf) == 0) {
- goto illegal_op; /* nop hint, in decodetree */
- }
- /*
- * IT (If-Then)
- *
- * Combinations of firstcond and mask which set up an 0b1111
- * condition are UNPREDICTABLE; we take the CONSTRAINED
- * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,
- * i.e. both meaning "execute always".
- */
- s->condexec_cond = (insn >> 4) & 0xe;
- s->condexec_mask = insn & 0x1f;
- /* No actual code generated for this insn, just setup state. */
- break;
-
- case 0xe: /* bkpt */
- {
- int imm8 = extract32(insn, 0, 8);
- ARCH(5);
- gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
- break;
- }
-
- case 0xa: /* rev, and hlt */
- {
- int op1 = extract32(insn, 6, 2);
-
- if (op1 == 2) {
- /* HLT */
- int imm6 = extract32(insn, 0, 6);
-
- gen_hlt(s, imm6);
- break;
- }
-
- /* Otherwise this is rev, in decodetree */
- goto illegal_op;
- }
-
- case 6: /* setend, cps; in decodetree */
- goto illegal_op;
-
- default:
- goto undef;
- }
- break;
-
case 13: /* conditional branch or swi, in decodetree */
goto illegal_op;
@@ -10822,7 +10776,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
}
return;
illegal_op:
-undef:
gen_illegal_op(s);
}
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index f4091c812d..17297a3032 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ... @rdm
# Hints
+%it_cond 5:3 !function=times_2
+
{
- YIELD 1011 1111 0001 0000
- WFE 1011 1111 0010 0000
- WFI 1011 1111 0011 0000
+ {
+ YIELD 1011 1111 0001 0000
+ WFE 1011 1111 0010 0000
+ WFI 1011 1111 0011 0000
- # TODO: Implement SEV, SEVL; may help SMP performance.
- # SEV 1011 1111 0100 0000
- # SEVL 1011 1111 0101 0000
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1011 1111 0100 0000
+ # SEVL 1011 1111 0101 0000
- # The canonical nop has the second nibble as 0000, but the whole of the
- # rest of the space is a reserved hint, behaves as nop.
- NOP 1011 1111 ---- 0000
+ # The canonical nop has the second nibble as 0000, but the whole of the
+ # rest of the space is a reserved hint, behaves as nop.
+ NOP 1011 1111 ---- 0000
+ }
+ IT 1011 1111 ... imm:5 &ci cond=%it_cond
}
+# Miscellaneous 16-bit instructions
+
+%imm6_9_3 9:1 3:5 !function=times_2
+
+HLT 1011 1010 10 imm:6 &i
+BKPT 1011 1110 imm:8 &i
+CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3
+
# Push and Pop
%push_list 0:9 !function=t16_push_list
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (59 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) Richard Henderson
` (7 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 26 ++------------------------
target/arm/t16.decode | 8 ++++++++
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f3a946d8c9..f9022fe65c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10657,7 +10657,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, op, rm, rd, shift;
+ uint32_t val, rd;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10669,29 +10669,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/* fall back to legacy decoder */
switch (insn >> 12) {
- case 0: case 1:
-
- rd = insn & 7;
- op = (insn >> 11) & 3;
- if (op == 3) {
- /*
- * 0b0001_1xxx_xxxx_xxxx
- * - Add, subtract (three low registers)
- * - Add, subtract (two low registers and immediate)
- * In decodetree.
- */
- goto illegal_op;
- } else {
- /* shift immediate */
- rm = (insn >> 3) & 7;
- shift = (insn >> 6) & 0x1f;
- tmp = load_reg(s, rm);
- gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
- }
- break;
+ case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
goto illegal_op;
case 4:
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 17297a3032..ddffd073a2 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \
STM 11000 ... ........ @ldstm
LDM_t16 11001 ... ........ @ldstm
+# Shift (immediate)
+
+@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0
+
+MOV_rrri 000 00 ..... ... ... @shift_i shty=0 # LSL
+MOV_rrri 000 01 ..... ... ... @shift_i shty=1 # LSR
+MOV_rrri 000 10 ..... ... ... @shift_i shty=2 # ASR
+
# Add/subtract (three low registers)
@addsub_3 ....... rm:3 rn:3 rd:3 \
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal)
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (60 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch Richard Henderson
` (6 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 42 ++----------------------------------------
target/arm/t16.decode | 4 ++++
2 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f9022fe65c..f1cab437e0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1011,14 +1011,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 a32, int index) \
{ \
gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
-} \
-static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
- TCGv_i32 val, \
- TCGv_i32 a32, int index, \
- ISSInfo issinfo) \
-{ \
- gen_aa32_ld##SUFF(s, val, a32, index); \
- disas_set_da_iss(s, OPC, issinfo); \
}
#define DO_GEN_ST(SUFF, OPC) \
@@ -1026,14 +1018,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 a32, int index) \
{ \
gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
-} \
-static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
- TCGv_i32 val, \
- TCGv_i32 a32, int index, \
- ISSInfo issinfo) \
-{ \
- gen_aa32_st##SUFF(s, val, a32, index); \
- disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
}
static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -1082,9 +1066,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
}
-DO_GEN_LD(8s, MO_SB)
DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16s, MO_SW)
DO_GEN_LD(16u, MO_UW)
DO_GEN_LD(32u, MO_UL)
DO_GEN_ST(8, MO_UB)
@@ -10657,11 +10639,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, rd;
+ uint32_t val;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
- TCGv_i32 addr;
if (disas_t16(s, insn)) {
return;
@@ -10671,26 +10652,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
switch (insn >> 12) {
case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
- goto illegal_op;
- case 4:
- if (insn & (1 << 11)) {
- rd = (insn >> 8) & 7;
- /* load pc-relative. Bit 1 of PC is ignored. */
- addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
- rd | ISSIs16Bit);
- tcg_temp_free_i32(addr);
- store_reg(s, rd, tmp);
- break;
- }
-
- /*
- * - Data-processing (two low registers), in decodetree
- * - data processing extended, branch and exchange, in decodetree
- */
- goto illegal_op;
-
+ case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */
case 5: /* load/store register offset, in decodetree */
case 6: /* load/store word immediate offset, in decodetree */
case 7: /* load/store byte immediate offset, in decodetree */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index ddffd073a2..c18d146a84 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2
STR_ri 10010 ... ........ @ldst_spec_i rn=13
LDR_ri 10011 ... ........ @ldst_spec_i rn=13
+# Load (PC-relative)
+
+LDR_ri 01001 ... ........ @ldst_spec_i rn=15
+
# Add PC/SP (immediate)
ADR 10100 rd:3 ........ imm=%imm8_0x4
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (61 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches Richard Henderson
` (5 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 9 ++-------
target/arm/t16.decode | 6 ++++++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f1cab437e0..480515a0a9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10639,7 +10639,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10683,12 +10682,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
gen_bx(s, tmp);
break;
}
- /* unconditional branch */
- val = s->pc_read;
- offset = ((int32_t)insn << 21) >> 21;
- val += offset << 1;
- gen_jmp(s, val);
- break;
+ /* unconditional branch, in decodetree */
+ goto illegal_op;
case 15:
/* thumb_insn_is_16bit() ensures we can't get here for
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index c18d146a84..457f2f4178 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -268,3 +268,9 @@ LDM 1011 110 ......... \
SVC 1101 1111 imm:8 &i
B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
}
+
+# Unconditional Branch
+
+%imm11_0x2 0:s11 !function=times_2
+
+B 11100 ........... &i imm=%imm11_0x2
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (62 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn Richard Henderson
` (4 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 89 +++++++++++++++++++-----------------------
target/arm/t16.decode | 3 ++
2 files changed, 43 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 480515a0a9..a8db6e9280 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10055,6 +10055,44 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a)
+{
+ /*
+ * thumb_insn_is_16bit() ensures we can't get here for
+ * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
+ */
+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+ tcg_gen_movi_i32(cpu_R[14], s->pc_read + (a->imm << 12));
+ return true;
+}
+
+static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+ tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1);
+ tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
+ gen_bx(s, tmp);
+ return true;
+}
+
+static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a)
+{
+ TCGv_i32 tmp;
+
+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+ if (!ENABLE_ARCH_5) {
+ return false;
+ }
+ tmp = tcg_temp_new_i32();
+ tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1);
+ tcg_gen_andi_i32(tmp, tmp, -4);
+ tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
+ gen_bx(s, tmp);
+ return true;
+}
+
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
{
TCGv_i32 addr, tmp;
@@ -10639,10 +10677,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- int32_t offset;
- TCGv_i32 tmp;
- TCGv_i32 tmp2;
-
if (disas_t16(s, insn)) {
return;
}
@@ -10661,53 +10695,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 11: /* misc, in decodetree */
case 12: /* load/store multiple, in decodetree */
case 13: /* conditional branch or swi, in decodetree */
- goto illegal_op;
-
case 14:
- if (insn & (1 << 11)) {
- /* thumb_insn_is_16bit() ensures we can't get here for
- * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
- * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
- */
- assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
- ARCH(5);
- offset = ((insn & 0x7ff) << 1);
- tmp = load_reg(s, 14);
- tcg_gen_addi_i32(tmp, tmp, offset);
- tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
-
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, s->pc | 1);
- store_reg(s, 14, tmp2);
- gen_bx(s, tmp);
- break;
- }
- /* unconditional branch, in decodetree */
- goto illegal_op;
-
case 15:
- /* thumb_insn_is_16bit() ensures we can't get here for
- * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
- */
- assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
-
- if (insn & (1 << 11)) {
- /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
- offset = ((insn & 0x7ff) << 1) | 1;
- tmp = load_reg(s, 14);
- tcg_gen_addi_i32(tmp, tmp, offset);
-
- tmp2 = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp2, s->pc | 1);
- store_reg(s, 14, tmp2);
- gen_bx(s, tmp);
- } else {
- /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
- uint32_t uoffset = ((int32_t)insn << 21) >> 9;
-
- tcg_gen_movi_i32(cpu_R[14], s->pc_read + uoffset);
- }
- break;
+ /* branches, in decodetree */
+ goto illegal_op;
}
return;
illegal_op:
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 457f2f4178..105218882a 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -274,3 +274,6 @@ LDM 1011 110 ......... \
%imm11_0x2 0:s11 !function=times_2
B 11100 ........... &i imm=%imm11_0x2
+BLX_suffix 11101 imm:11 &i
+BL_BLX_prefix 11110 imm:s11 &i
+BL_suffix 11111 imm:11 &i
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (63 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
` (3 subsequent siblings)
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
Now that everything is converted, remove the rest of
the legacy decode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 27 ++-------------------------
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a8db6e9280..c2b8b86fd2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10677,32 +10677,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- if (disas_t16(s, insn)) {
- return;
+ if (!disas_t16(s, insn)) {
+ gen_illegal_op(s);
}
- /* fall back to legacy decoder */
-
- switch (insn >> 12) {
- case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
- case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
- case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */
- case 5: /* load/store register offset, in decodetree */
- case 6: /* load/store word immediate offset, in decodetree */
- case 7: /* load/store byte immediate offset, in decodetree */
- case 8: /* load/store halfword immediate offset, in decodetree */
- case 9: /* load/store from stack, in decodetree */
- case 10: /* add PC/SP (immediate), in decodetree */
- case 11: /* misc, in decodetree */
- case 12: /* load/store multiple, in decodetree */
- case 13: /* conditional branch or swi, in decodetree */
- case 14:
- case 15:
- /* branches, in decodetree */
- goto illegal_op;
- }
- return;
-illegal_op:
- gen_illegal_op(s);
}
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (64 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 18:13 ` Peter Maydell
2019-07-26 17:50 ` [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i Richard Henderson
` (2 subsequent siblings)
68 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
We miss quite a number of single-step events by having
the check in the wrong place.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c2b8b86fd2..9ae9b23823 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2740,7 +2740,10 @@ static void gen_goto_ptr(void)
*/
static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
{
- if (use_goto_tb(s, dest)) {
+ if (unlikely(is_singlestepping(s))) {
+ gen_set_pc_im(s, dest);
+ gen_singlestep_exception(s);
+ } else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
gen_set_pc_im(s, dest);
tcg_gen_exit_tb(s->base.tb, n);
@@ -2751,16 +2754,9 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
s->base.is_jmp = DISAS_NORETURN;
}
-static inline void gen_jmp (DisasContext *s, uint32_t dest)
+static inline void gen_jmp(DisasContext *s, uint32_t dest)
{
- if (unlikely(is_singlestepping(s))) {
- /* An indirect jump so that we still trigger the debug exception. */
- if (s->thumb)
- dest |= 1;
- gen_bx_im(s, dest);
- } else {
- gen_goto_tb(s, 0, dest);
- }
+ gen_goto_tb(s, 0, dest);
}
static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (65 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
@ 2019-07-26 17:50 ` Richard Henderson
2019-07-26 18:40 ` [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-05 15:44 ` Peter Maydell
68 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 17:50 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
This is the only remaining use of gen_bx_im. Simplify, since we know
the destination mode is changing. Use gen_jmp for the actual branch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9ae9b23823..dc51e1e622 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -813,21 +813,6 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
tcg_gen_movi_i32(cpu_R[15], val);
}
-/* Set PC and Thumb state from an immediate address. */
-static inline void gen_bx_im(DisasContext *s, uint32_t addr)
-{
- TCGv_i32 tmp;
-
- s->base.is_jmp = DISAS_JUMP;
- if (s->thumb != (addr & 1)) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, addr & 1);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_movi_i32(cpu_R[15], addr & ~1);
-}
-
/* Set PC and Thumb state from var. var is marked as dead. */
static inline void gen_bx(DisasContext *s, TCGv_i32 var)
{
@@ -10042,12 +10027,18 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
+ TCGv_i32 tmp;
+
/* For A32, ARCH(5) is checked near the start of the uncond block. */
if (s->thumb && (a->imm & 2)) {
return false;
}
tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb);
- gen_bx_im(s, (s->pc_read & ~3) + a->imm + !s->thumb);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(tmp, !s->thumb);
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
+ tcg_temp_free_i32(tmp);
+ gen_jmp(s, (s->pc_read & ~3) + a->imm);
return true;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
@ 2019-07-26 18:13 ` Peter Maydell
2019-07-26 18:34 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-26 18:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We miss quite a number of single-step events by having
> the check in the wrong place.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 16 ++++++----------
> 1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index c2b8b86fd2..9ae9b23823 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -2740,7 +2740,10 @@ static void gen_goto_ptr(void)
> */
> static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
> {
> - if (use_goto_tb(s, dest)) {
> + if (unlikely(is_singlestepping(s))) {
> + gen_set_pc_im(s, dest);
> + gen_singlestep_exception(s);
> + } else if (use_goto_tb(s, dest)) {
> tcg_gen_goto_tb(n);
> gen_set_pc_im(s, dest);
> tcg_gen_exit_tb(s->base.tb, n);
> @@ -2751,16 +2754,9 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
> s->base.is_jmp = DISAS_NORETURN;
> }
>
> -static inline void gen_jmp (DisasContext *s, uint32_t dest)
> +static inline void gen_jmp(DisasContext *s, uint32_t dest)
> {
> - if (unlikely(is_singlestepping(s))) {
> - /* An indirect jump so that we still trigger the debug exception. */
> - if (s->thumb)
> - dest |= 1;
> - gen_bx_im(s, dest);
> - } else {
> - gen_goto_tb(s, 0, dest);
> - }
> + gen_goto_tb(s, 0, dest);
> }
>
> static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
I haven't tested but I'm not sure this change is right.
The idea of the current code is that we handle generating
the actual singlestep exception in arm_tr_tb_stop() at the
end, rather than in the process of generating code for the
insn. This change means we now do a gen_singlestep_exception()
in the gen_jmp()/gen_goto_tb() part of the code, but we haven't
removed the handling of it in arm_tr_tb_stop(), so we're now
doing this in two places. Why doesn't the current design work?
And if we need to do something different for the route to
"change the PC via gen_jmp()" why don't we need to do it
also when we change the PC via eg gen_bx_im() ?
(Incidentally, the only places other than gen_jmp()
which call gen_goto_tb() are:
* the end-of-TB handling of DISAS_NEXT/DISAS_TOO_MANY
* four places for barrier insns where we use a
gen_goto_tb to end the TB -- this isn't consistent
with how we end the TB for other situations...)
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb
2019-07-26 18:13 ` Peter Maydell
@ 2019-07-26 18:34 ` Richard Henderson
0 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-26 18:34 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/26/19 11:13 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We miss quite a number of single-step events by having
>> the check in the wrong place.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/translate.c | 16 ++++++----------
>> 1 file changed, 6 insertions(+), 10 deletions(-)
>>
>> diff --git a/target/arm/translate.c b/target/arm/translate.c
>> index c2b8b86fd2..9ae9b23823 100644
>> --- a/target/arm/translate.c
>> +++ b/target/arm/translate.c
>> @@ -2740,7 +2740,10 @@ static void gen_goto_ptr(void)
>> */
>> static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
>> {
>> - if (use_goto_tb(s, dest)) {
>> + if (unlikely(is_singlestepping(s))) {
>> + gen_set_pc_im(s, dest);
>> + gen_singlestep_exception(s);
>> + } else if (use_goto_tb(s, dest)) {
>> tcg_gen_goto_tb(n);
>> gen_set_pc_im(s, dest);
>> tcg_gen_exit_tb(s->base.tb, n);
>> @@ -2751,16 +2754,9 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
>> s->base.is_jmp = DISAS_NORETURN;
>> }
>>
>> -static inline void gen_jmp (DisasContext *s, uint32_t dest)
>> +static inline void gen_jmp(DisasContext *s, uint32_t dest)
>> {
>> - if (unlikely(is_singlestepping(s))) {
>> - /* An indirect jump so that we still trigger the debug exception. */
>> - if (s->thumb)
>> - dest |= 1;
>> - gen_bx_im(s, dest);
>> - } else {
>> - gen_goto_tb(s, 0, dest);
>> - }
>> + gen_goto_tb(s, 0, dest);
>> }
>>
>> static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
>
> I haven't tested but I'm not sure this change is right.
> The idea of the current code is that we handle generating
> the actual singlestep exception in arm_tr_tb_stop() at the
> end, rather than in the process of generating code for the
> insn. This change means we now do a gen_singlestep_exception()
> in the gen_jmp()/gen_goto_tb() part of the code, but we haven't
> removed the handling of it in arm_tr_tb_stop(), so we're now
> doing this in two places. Why doesn't the current design work?
Note that the existing gen_goto_tb does not test for single-step, and always
emits NORETURN code, either via tcg_gen_goto_tb() or
tcg_gen_lookup_and_goto_ptr(). The singlestep exception is neither generated
nor would it be reachable.
Another way to do handle this would be to test single-step but set DISAS_JUMP
instead of actually generate the singlestep exception in gen_goto_tb. Do you
prefer that method?
> And if we need to do something different for the route to
> "change the PC via gen_jmp()" why don't we need to do it
> also when we change the PC via eg gen_bx_im() ?
See patch 67.
> * four places for barrier insns where we use a
> gen_goto_tb to end the TB -- this isn't consistent
> with how we end the TB for other situations...)
Fixing this sounds like a good cleanup.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (66 preceding siblings ...)
2019-07-26 17:50 ` [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i Richard Henderson
@ 2019-07-26 18:40 ` no-reply
2019-08-05 15:44 ` Peter Maydell
68 siblings, 0 replies; 110+ messages in thread
From: no-reply @ 2019-07-26 18:40 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-arm, alex.bennee, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190726175032.6769-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
Message-id: 20190726175032.6769-1-richard.henderson@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190726175032.6769-1-richard.henderson@linaro.org -> patchew/20190726175032.6769-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/edk2' (https://git.qemu.org/git/edk2.git) registered for path 'roms/edk2'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/opensbi' (https://git.qemu.org/git/opensbi.git) registered for path 'roms/opensbi'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://git.qemu.org/git/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'slirp' (https://git.qemu.org/git/libslirp.git) registered for path 'slirp'
Submodule 'tests/fp/berkeley-softfloat-3' (https://git.qemu.org/git/berkeley-softfloat-3.git) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://git.qemu.org/git/berkeley-testfloat-3.git) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'ba1ab360eebe6338bb8d7d83a9220ccf7e213af3'
Cloning into 'roms/edk2'...
Submodule path 'roms/edk2': checked out '20d2e5a125e34fc8501026613a71549b2a1a3e54'
Submodule 'SoftFloat' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'
Submodule 'CryptoPkg/Library/OpensslLib/openssl' (https://github.com/openssl/openssl) registered for path 'CryptoPkg/Library/OpensslLib/openssl'
Cloning into 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'...
Submodule path 'roms/edk2/ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'CryptoPkg/Library/OpensslLib/openssl'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl': checked out '50eaac9f3337667259de725451f201e784599687'
Submodule 'boringssl' (https://boringssl.googlesource.com/boringssl) registered for path 'boringssl'
Submodule 'krb5' (https://github.com/krb5/krb5) registered for path 'krb5'
Submodule 'pyca.cryptography' (https://github.com/pyca/cryptography.git) registered for path 'pyca-cryptography'
Cloning into 'boringssl'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/boringssl': checked out '2070f8ad9151dc8f3a73bffaa146b5e6937a583f'
Cloning into 'krb5'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/krb5': checked out 'b9ad6c49505c96a088326b62a52568e3484f2168'
Cloning into 'pyca-cryptography'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/pyca-cryptography': checked out '09403100de2f6f1cdd0d484dcb8e620f1c335c8f'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 'c79e0ecb84f4f1ee3f73f521622e264edd1bf174'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/opensbi'...
Submodule path 'roms/opensbi': checked out 'ce228ee0919deb9957192d723eecc8aaae2697c6'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 'bf0e13698872450164fa7040da36a95d2d4b326f'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a5cab58e9a3fb6e168aba919c5669bea406573b4'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '0f4fe84658165e96ce35870fd19fc634e182e77b'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out '261ca8e779e5138869a45f174caa49be6a274501'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd3689267f92c5956e09cc7d1baa4700141662bff'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'slirp'...
Submodule path 'slirp': checked out 'f0da6726207b740f6101028b2992f918477a4b08'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
3e96cf9 target/arm: Merge gen_bx_im into trans_BLX_i
773c770 target/arm: Move singlestep check from gen_jmp to gen_goto_tb
2a5246b target/arm: Clean up disas_thumb_insn
f985ef5 target/arm: Convert T16, long branches
2faac2a target/arm: Convert T16, Unconditional branch
1fb21ac target/arm: Convert T16, load (literal)
3624e32 target/arm: Convert T16, shift immediate
4fe1b9f target/arm: Convert T16, Miscellaneous 16-bit instructions
6a11d6a target/arm: Convert T16, Conditional branches, Supervisor call
ef85099 target/arm: Convert T16, push and pop
8e66d6c target/arm: Convert T16, nop hints
bbf4fab target/arm: Convert T16, Reverse bytes
b9d3b3d target/arm: Convert T16, Change processor state
8a316ac target/arm: Convert T16, extract
11f12d3 target/arm: Convert T16 adjust sp (immediate)
db70a80 target/arm: Convert T16 add, compare, move (two high registers)
a4baf44 target/arm: Convert T16 branch and exchange
b1de765 target/arm: Convert T16 one low register and immediate
521cb4f target/arm: Convert T16 add/sub (3 low, 2 low and imm)
ea841ad target/arm: Convert T16 load/store multiple
a24f7c2 target/arm: Convert T16 add pc/sp (immediate)
23702d1 target/arm: Convert T16 load/store (immediate offset)
e018c38 target/arm: Convert T16 load/store (register offset)
d375237 target/arm: Convert T16 data-processing (two low regs)
e2b0a6c target/arm: Add skeleton for T16 decodetree
36b9fa0 target/arm: Simplify disas_arm_insn
587b818 target/arm: Simplify disas_thumb2_insn
c030f15 target/arm: Convert TT
f07ccb6 target/arm: Convert SG
5b658a2 target/arm: Convert Table Branch
44ae137 target/arm: Convert Unallocated memory hint
22dc1ab target/arm: Convert PLI, PLD, PLDW
48b0cc4 target/arm: Convert SETEND
396f9b0 target/arm: Convert CPS (privileged)
9f42967 target/arm: Convert Clear-Exclusive, Barriers
6d7832b target/arm: Convert RFE and SRS
6baefa5 target/arm: Convert SVC
66bdd2b target/arm: Convert B, BL, BLX (immediate)
bb053c6 target/arm: Convert LDM, STM
129900f target/arm: Convert MOVW, MOVT
6cd498d target/arm: Convert Signed multiply, signed and unsigned divide
5f3c9f7 target/arm: Convert Packing, unpacking, saturation, and reversal
e2a764f target/arm: Convert Parallel addition and subtraction
837c8be target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
f4c9598 target/arm: Convert Synchronization primitives
e74158e target/arm: Convert load/store (register, immediate, literal)
c2962d5 target/arm: Convert T32 ADDW/SUBW
f41f8e6 target/arm: Convert the rest of A32 Miscelaneous instructions
a063450 target/arm: Convert Cyclic Redundancy Check
670924b target/arm: Convert MRS/MSR (banked, register)
0ca68c3 target/arm: Convert MSR (immediate) and hints
76ae2b1 target/arm: Convert Halfword multiply and multiply accumulate
b9c7121 target/arm: Convert Saturating addition and subtraction
4cf0de3 target/arm: Convert multiply and multiply accumulate
8f08e2c target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
9ff2962 target/arm: Introduce gen_illegal_op
9203cc5 target/arm: Add stubs for aa32 decodetree
c652286 target/arm: Move test for AL into arm_skip_unless
862414e target/arm: Fold a pc load into load_reg
69b8001 target/arm: Use store_reg_from_load in thumb2 code
b6cabf9 target/arm: Introduce add_reg_for_lit
840fdc0 target/arm: Introduce pc_read
5fa3ae2 target/arm: Use the saved value of the insn address
77512cc target/arm: Remove offset argument to gen_exception_internal_insn
17825b7 target/arm: Remove offset argument to gen_exception_bkpt_insn
eeda82e target/arm: Remove offset argument to gen_exception_insn
79d20cd decodetree: Allow !function with no input bits
=== OUTPUT BEGIN ===
1/67 Checking commit 79d20cda7b96 (decodetree: Allow !function with no input bits)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29:
new file mode 100644
total: 0 errors, 1 warnings, 13 lines checked
Patch 1/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/67 Checking commit eeda82e2506e (target/arm: Remove offset argument to gen_exception_insn)
3/67 Checking commit 17825b7218c5 (target/arm: Remove offset argument to gen_exception_bkpt_insn)
4/67 Checking commit 77512ccb9bdc (target/arm: Remove offset argument to gen_exception_internal_insn)
5/67 Checking commit 5fa3ae205e44 (target/arm: Use the saved value of the insn address)
6/67 Checking commit 840fdc031133 (target/arm: Introduce pc_read)
7/67 Checking commit b6cabf97a6e9 (target/arm: Introduce add_reg_for_lit)
8/67 Checking commit 69b8001fbec9 (target/arm: Use store_reg_from_load in thumb2 code)
9/67 Checking commit 862414ea9430 (target/arm: Fold a pc load into load_reg)
10/67 Checking commit c65228636caf (target/arm: Move test for AL into arm_skip_unless)
11/67 Checking commit 9203cc5c93cb (target/arm: Add stubs for aa32 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#46:
new file mode 100644
WARNING: architecture specific defines should be avoided
#147: FILE: target/arm/translate.c:7728:
+# ifdef __clang__
total: 0 errors, 2 warnings, 168 lines checked
Patch 11/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/67 Checking commit 9ff2962de826 (target/arm: Introduce gen_illegal_op)
13/67 Checking commit 8f08e2cadfd9 (target/arm: Convert Data Processing (reg, reg-shifted-reg, imm))
ERROR: suspect code indent for conditional statements (13, 17)
#551: FILE: target/arm/translate.c:8014:
+ if (a->s && a->rd == 15) {
+ if (IS_USER(s)) {
ERROR: suspect code indent for conditional statements (17, 21)
#552: FILE: target/arm/translate.c:8015:
+ if (IS_USER(s)) {
+ return false;
ERROR: suspect code indent for conditional statements (13, 17)
#575: FILE: target/arm/translate.c:8038:
+ if (a->s && a->rd == 15) {
+ if (IS_USER(s)) {
ERROR: suspect code indent for conditional statements (17, 21)
#576: FILE: target/arm/translate.c:8039:
+ if (IS_USER(s)) {
+ return false;
ERROR: suspect code indent for conditional statements (13, 17)
#580: FILE: target/arm/translate.c:8043:
+ } else if (a->rn == 13) {
+ result = STREG_SP_CHECK;
total: 5 errors, 0 warnings, 988 lines checked
Patch 13/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/67 Checking commit 4cf0de31365c (target/arm: Convert multiply and multiply accumulate)
15/67 Checking commit b9c7121e3e94 (target/arm: Convert Saturating addition and subtraction)
16/67 Checking commit 76ae2b182e23 (target/arm: Convert Halfword multiply and multiply accumulate)
17/67 Checking commit 0ca68c3e6e2d (target/arm: Convert MSR (immediate) and hints)
18/67 Checking commit 670924bed154 (target/arm: Convert MRS/MSR (banked, register))
19/67 Checking commit a06345040de2 (target/arm: Convert Cyclic Redundancy Check)
20/67 Checking commit f41f8e6227d0 (target/arm: Convert the rest of A32 Miscelaneous instructions)
21/67 Checking commit c2962d5d2129 (target/arm: Convert T32 ADDW/SUBW)
22/67 Checking commit e74158ee8bb6 (target/arm: Convert load/store (register, immediate, literal))
23/67 Checking commit f4c9598830eb (target/arm: Convert Synchronization primitives)
24/67 Checking commit 837c8be4e20e (target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF)
25/67 Checking commit e2a764fd4e94 (target/arm: Convert Parallel addition and subtraction)
26/67 Checking commit 5f3c9f750009 (target/arm: Convert Packing, unpacking, saturation, and reversal)
ERROR: trailing statements should be on next line
#803: FILE: target/arm/translate.c:11485:
+ case 1: gen_rev16(tmp, tmp); break;
ERROR: trailing statements should be on next line
#804: FILE: target/arm/translate.c:11486:
+ case 3: gen_revsh(tmp, tmp); break;
total: 2 errors, 0 warnings, 766 lines checked
Patch 26/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
27/67 Checking commit 6cd498dafa86 (target/arm: Convert Signed multiply, signed and unsigned divide)
28/67 Checking commit 129900feabf2 (target/arm: Convert MOVW, MOVT)
29/67 Checking commit bb053c64948b (target/arm: Convert LDM, STM)
30/67 Checking commit 66bdd2bc9873 (target/arm: Convert B, BL, BLX (immediate))
31/67 Checking commit 6baefa579e7f (target/arm: Convert SVC)
32/67 Checking commit 6d7832b65962 (target/arm: Convert RFE and SRS)
ERROR: trailing statements should be on next line
#72: FILE: target/arm/translate.c:10010:
+ case 0: offset = -4; break; /* DA */
ERROR: trailing statements should be on next line
#73: FILE: target/arm/translate.c:10011:
+ case 1: offset = 0; break; /* IA */
ERROR: trailing statements should be on next line
#74: FILE: target/arm/translate.c:10012:
+ case 2: offset = -8; break; /* DB */
ERROR: trailing statements should be on next line
#75: FILE: target/arm/translate.c:10013:
+ case 3: offset = 4; break; /* IB */
ERROR: trailing statements should be on next line
#91: FILE: target/arm/translate.c:10029:
+ case 0: offset = -8; break;
ERROR: trailing statements should be on next line
#92: FILE: target/arm/translate.c:10030:
+ case 1: offset = 4; break;
ERROR: trailing statements should be on next line
#93: FILE: target/arm/translate.c:10031:
+ case 2: offset = -4; break;
ERROR: trailing statements should be on next line
#94: FILE: target/arm/translate.c:10032:
+ case 3: offset = 0; break;
total: 8 errors, 0 warnings, 208 lines checked
Patch 32/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/67 Checking commit 9f42967c7dfa (target/arm: Convert Clear-Exclusive, Barriers)
34/67 Checking commit 396f9b0af3b2 (target/arm: Convert CPS (privileged))
35/67 Checking commit 48b0cc4253ea (target/arm: Convert SETEND)
36/67 Checking commit 22dc1abca836 (target/arm: Convert PLI, PLD, PLDW)
37/67 Checking commit 44ae1372a386 (target/arm: Convert Unallocated memory hint)
38/67 Checking commit 5b658a206f20 (target/arm: Convert Table Branch)
39/67 Checking commit f07ccb66063e (target/arm: Convert SG)
40/67 Checking commit c030f15fdeb5 (target/arm: Convert TT)
41/67 Checking commit 587b818c6c56 (target/arm: Simplify disas_thumb2_insn)
42/67 Checking commit 36b9fa03aa30 (target/arm: Simplify disas_arm_insn)
43/67 Checking commit e2b0a6c5f0d1 (target/arm: Add skeleton for T16 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
total: 0 errors, 1 warnings, 56 lines checked
Patch 43/67 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
44/67 Checking commit d375237de41a (target/arm: Convert T16 data-processing (two low regs))
45/67 Checking commit e018c3808763 (target/arm: Convert T16 load/store (register offset))
46/67 Checking commit 23702d173572 (target/arm: Convert T16 load/store (immediate offset))
47/67 Checking commit a24f7c2e5272 (target/arm: Convert T16 add pc/sp (immediate))
48/67 Checking commit ea841adddfbd (target/arm: Convert T16 load/store multiple)
49/67 Checking commit 521cb4f43ad1 (target/arm: Convert T16 add/sub (3 low, 2 low and imm))
50/67 Checking commit b1de765a80aa (target/arm: Convert T16 one low register and immediate)
51/67 Checking commit a4baf4481285 (target/arm: Convert T16 branch and exchange)
52/67 Checking commit db70a8090d99 (target/arm: Convert T16 add, compare, move (two high registers))
53/67 Checking commit 11f12d392985 (target/arm: Convert T16 adjust sp (immediate))
54/67 Checking commit 8a316ac286d3 (target/arm: Convert T16, extract)
55/67 Checking commit b9d3b3d6009e (target/arm: Convert T16, Change processor state)
56/67 Checking commit bbf4fabc01bb (target/arm: Convert T16, Reverse bytes)
57/67 Checking commit 8e66d6c87967 (target/arm: Convert T16, nop hints)
58/67 Checking commit ef8509911c56 (target/arm: Convert T16, push and pop)
59/67 Checking commit 6a11d6ac1c7e (target/arm: Convert T16, Conditional branches, Supervisor call)
60/67 Checking commit 4fe1b9f79975 (target/arm: Convert T16, Miscellaneous 16-bit instructions)
61/67 Checking commit 3624e32c47c1 (target/arm: Convert T16, shift immediate)
62/67 Checking commit 1fb21acaaff4 (target/arm: Convert T16, load (literal))
63/67 Checking commit 2faac2abfb65 (target/arm: Convert T16, Unconditional branch)
64/67 Checking commit f985ef5169f0 (target/arm: Convert T16, long branches)
65/67 Checking commit 2a5246bd4d7d (target/arm: Clean up disas_thumb_insn)
66/67 Checking commit 773c770a22d0 (target/arm: Move singlestep check from gen_jmp to gen_goto_tb)
67/67 Checking commit 3e96cf95bd0e (target/arm: Merge gen_bx_im into trans_BLX_i)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190726175032.6769-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
@ 2019-07-29 13:43 ` Peter Maydell
2019-07-30 1:30 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 13:43 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> With this, we can have the function return a value from the DisasContext.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> scripts/decodetree.py | 5 ++++-
> tests/decode/succ_function.decode | 2 ++
> 2 files changed, 6 insertions(+), 1 deletion(-)
> create mode 100644 tests/decode/succ_function.decode
>
> diff --git a/scripts/decodetree.py b/scripts/decodetree.py
> index d7a59d63ac..4259d87a95 100755
> --- a/scripts/decodetree.py
> +++ b/scripts/decodetree.py
> @@ -195,7 +195,10 @@ class MultiField:
> """Class representing a compound instruction field"""
> def __init__(self, subs, mask):
> self.subs = subs
> - self.sign = subs[0].sign
> + if len(subs):
> + self.sign = subs[0].sign
> + else:
> + self.sign = 0
> self.mask = mask
>
> def __str__(self):
> diff --git a/tests/decode/succ_function.decode b/tests/decode/succ_function.decode
> new file mode 100644
> index 0000000000..632a9de252
> --- /dev/null
> +++ b/tests/decode/succ_function.decode
> @@ -0,0 +1,2 @@
> +%foo !function=foo
> +foo 00000000000000000000000000000000 %foo
> --
> 2.17.1
Could you also update the documentation in docs/devel/decodetree.rst ?
This code change looks like it also now allows definitions
of fields that specify nothing at all (ie there's no check
that a field definition with no "unnamed_field" parts has
a !function specifier) -- what do they do, or should they
be made syntax errors ?
Is one of these functions which just returns a constant
from no input bits still a "static int func(DisasContext *s, int x)"
taking a pointless input argument, or is it now a
"static int func(DisasContext *s)" ? I guess from the fact
this code doesn't change the way a call is output that it
is the former, but would the latter be cleaner ?
(This would probably be implemented something like allowing
FunctionField to be passed a base == None instead of
allowing MultiFields with len(subs) == 0.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
@ 2019-07-29 13:48 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 13:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The address of the current insn is still available in s->base.pc_next.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-vfp.inc.c | 6 +++---
> target/arm/translate.c | 32 ++++++++++++++++----------------
> 2 files changed, 19 insertions(+), 19 deletions(-)
This works because all our uses of gen_exception_insn() are
for generating an exception at the PC of the current insn;
things like SVC/SMC/HVC which want to generate an exception
where the PC is that of the following insn are already handled
via a different function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
@ 2019-07-29 13:50 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 13:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The address of the current insn is still available in s->base.pc_next.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 33f78296eb..19b126d4f3 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -1256,12 +1256,12 @@ static void gen_exception_insn(DisasContext *s, int excp, int syn,
> s->base.is_jmp = DISAS_NORETURN;
> }
>
> -static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
> +static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
> {
> TCGv_i32 tcg_syn;
>
> gen_set_condexec(s);
> - gen_set_pc_im(s, s->pc - offset);
> + gen_set_pc_im(s, s->base.pc_next);
> tcg_syn = tcg_const_i32(syn);
> gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
> tcg_temp_free_i32(tcg_syn);
> @@ -8139,7 +8139,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> case 1:
> /* bkpt */
> ARCH(5);
> - gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
> + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
> break;
> case 2:
> /* Hypervisor call (v7) */
> @@ -11611,7 +11611,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> {
> int imm8 = extract32(insn, 0, 8);
> ARCH(5);
> - gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
> + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
> break;
> }
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
@ 2019-07-29 13:52 ` Peter Maydell
2019-07-30 2:11 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 13:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The actual argument is 0 for all callers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 19b126d4f3..0848fb933a 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -1239,10 +1239,10 @@ static inline void gen_smc(DisasContext *s)
> s->base.is_jmp = DISAS_SMC;
> }
>
> -static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
> +static void gen_exception_internal_insn(DisasContext *s, int excp)
> {
> gen_set_condexec(s);
> - gen_set_pc_im(s, s->pc - offset);
> + gen_set_pc_im(s, s->pc);
> gen_exception_internal(excp);
> s->base.is_jmp = DISAS_NORETURN;
> }
> @@ -1294,7 +1294,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
> s->current_el != 0 &&
> #endif
> (imm == (s->thumb ? 0x3c : 0xf000))) {
> - gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
> + gen_exception_internal_insn(s, EXCP_SEMIHOST);
> return;
> }
>
> @@ -11984,7 +11984,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
> /* End the TB early; it's likely not going to be executed */
> dc->base.is_jmp = DISAS_TOO_MANY;
> } else {
> - gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
> + gen_exception_internal_insn(dc, EXCP_DEBUG);
> /* The address covered by the breakpoint must be
> included in [tb->pc, tb->pc + tb->size) in order
> to for it to be properly cleared -- thus we
> --
> 2.17.1
I'm not so convinced about this one -- gen_exception_insn()
and gen_exception_internal_insn() shouldn't have the
same pattern of function prototype but different semantics
like this, it's confusing. It happens that both the cases
of wanting to generate an "internal" exception happen to want
it to be taken with the PC being for the following insn,
not the current one, but that seems more coincidence to
me than anything else.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
@ 2019-07-29 13:54 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 13:54 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The address of the current insn is still available in s->base.pc_next,
> and need not be recomputed from s->pc - 4.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
@ 2019-07-29 14:05 ` Peter Maydell
2019-07-30 0:38 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We currently have 3 different ways of computing the architectural
> value of "PC" as seen in the ARM ARM.
>
> The value of s->pc has been incremented past the current insn,
> but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
> for t16, PC = s->pc + 2. These differing computations make it
> impossible at present to unify the various code paths.
>
> Let s->pc_read hold the architectural value of PC for all cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.h | 10 ++++++++
> target/arm/translate.c | 53 ++++++++++++++++++------------------------
> 2 files changed, 32 insertions(+), 31 deletions(-)
>
> diff --git a/target/arm/translate.h b/target/arm/translate.h
> index a20f6e2056..2dfdd8ca66 100644
> --- a/target/arm/translate.h
> +++ b/target/arm/translate.h
> @@ -9,7 +9,17 @@ typedef struct DisasContext {
> DisasContextBase base;
> const ARMISARegisters *isar;
>
> + /*
> + * Summary of the various values for "PC":
> + * base.pc_next -- the start of the current insn
> + * pc -- the start of the next insn
These are confusingly named -- logically "pc_next" ought to
be the PC of the next instruction and "pc" ought to be
that of the current one...
> + * pc_read -- the value for "PC" in the ARM ARM;
nit: this line should end with a colon, rather than a semicolon
> + * in arm mode, the current insn + 8;
> + * in thumb mode, the current insn + 4;
> + * in aa64 mode, unused.
> + */
> target_ulong pc;
> + target_ulong pc_read;
> target_ulong page_start;
> uint32_t insn;
Why target_ulong rather than uint32_t, given this is
aarch32 only?
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
@ 2019-07-29 14:15 ` Peter Maydell
2019-07-30 0:51 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:15 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Used only on the thumb side so far, but will be more obvious
> once we start unifying the implementation of A32+T32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-vfp.inc.c | 34 +------
> target/arm/translate.c | 163 +++++++++++++++------------------
> 2 files changed, 76 insertions(+), 121 deletions(-)
>
> diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
> index e7389bc057..4066b2febf 100644
> --- a/target/arm/translate-vfp.inc.c
> +++ b/target/arm/translate-vfp.inc.c
> @@ -941,14 +941,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
> offset = -offset;
> }
>
> - if (s->thumb && a->rn == 15) {
> - /* This is actually UNPREDICTABLE */
> - addr = tcg_temp_new_i32();
> - tcg_gen_movi_i32(addr, s->pc & ~2);
> - } else {
> - addr = load_reg(s, a->rn);
> - }
> - tcg_gen_addi_i32(addr, addr, offset);
> + addr = add_reg_for_lit(s, a->rn, offset);
> tmp = tcg_temp_new_i32();
> if (a->l) {
> gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
> @@ -983,14 +976,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
> offset = -offset;
> }
>
> - if (s->thumb && a->rn == 15) {
> - /* This is actually UNPREDICTABLE */
> - addr = tcg_temp_new_i32();
> - tcg_gen_movi_i32(addr, s->pc & ~2);
> - } else {
> - addr = load_reg(s, a->rn);
> - }
> - tcg_gen_addi_i32(addr, addr, offset);
> + addr = add_reg_for_lit(s, a->rn, offset);
> tmp = tcg_temp_new_i64();
> if (a->l) {
> gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
> @@ -1029,13 +1015,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
> return true;
> }
>
> - if (s->thumb && a->rn == 15) {
> - /* This is actually UNPREDICTABLE */
> - addr = tcg_temp_new_i32();
> - tcg_gen_movi_i32(addr, s->pc & ~2);
> - } else {
> - addr = load_reg(s, a->rn);
> - }
> + addr = add_reg_for_lit(s, a->rn, 0);
> if (a->p) {
> /* pre-decrement */
> tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
> @@ -1112,13 +1092,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
> return true;
> }
>
> - if (s->thumb && a->rn == 15) {
> - /* This is actually UNPREDICTABLE */
> - addr = tcg_temp_new_i32();
> - tcg_gen_movi_i32(addr, s->pc & ~2);
> - } else {
> - addr = load_reg(s, a->rn);
> - }
> + addr = add_reg_for_lit(s, a->rn, 0);
> if (a->p) {
> /* pre-decrement */
> tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index a48e9a90f8..5e2dd8bb16 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -214,6 +214,23 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
> return tmp;
> }
>
> +/*
> + * Create a new temp, incremented by OFS, except PC is aligned but not
> + * incremented for thumb. This is used for load/store for which use of
> + * PC implies (literal), or ADD that implies ADR.
> + */
> +static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
> +{
> + TCGv_i32 tmp = tcg_temp_new_i32();
> +
> + if (reg == 15) {
> + tcg_gen_movi_i32(tmp, (s->pc_read & ~3) + ofs);
> + } else {
> + tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
> + }
> + return tmp;
> +}
This is losing the information in the comments about the UNPREDICTABLE
cases. Are there callsites where the new function is called where
"thumb and reg == 15" is not UNPREDICTABLE, or are they all
that way?
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
@ 2019-07-29 14:26 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There is an extra always-true ARMv5 test, but this will
> become more obvious once we start unifying the
> implementation of A32+T32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 5e2dd8bb16..e316eeb312 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -9773,13 +9773,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> /* Load. */
> tmp = tcg_temp_new_i32();
> gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
> - if (i == 15) {
> - gen_bx_excret(s, tmp);
> - } else if (i == rn) {
> + if (i == rn) {
> loaded_var = tmp;
> loaded_base = 1;
> } else {
> - store_reg(s, i, tmp);
> + store_reg_from_load(s, i, tmp);
> }
> } else {
> /* Store. */
I thought at first this would change behaviour if rn == 15
but in practice it doesn't because 15 is the end of the loop
anyway. (This is an UNPREDICTABLE case, but if they get in our
way it might be better to explicitly make them UNDEF rather than
just behaving like whatever falls out from the implementation.)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
@ 2019-07-29 14:27 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index e316eeb312..53c46fcdc4 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -9161,11 +9161,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> }
> } else {
> /* store */
> - if (i == 15) {
> - /* special case: r15 = PC + 8 */
> - tmp = tcg_temp_new_i32();
> - tcg_gen_movi_i32(tmp, s->pc_read);
> - } else if (user) {
> + if (user && i != 15) {
> tmp = tcg_temp_new_i32();
> tmp2 = tcg_const_i32(i);
> gen_helper_get_user_reg(tmp, cpu_env, tmp2);
> --
> 2.17.1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
@ 2019-07-29 14:32 ` Peter Maydell
2019-07-30 0:57 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We will shortly be calling this function much more often.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 28 ++++++++++++----------------
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 53c46fcdc4..36419025db 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7705,8 +7705,14 @@ static void arm_gen_condlabel(DisasContext *s)
> /* Skip this instruction if the ARM condition is false */
> static void arm_skip_unless(DisasContext *s, uint32_t cond)
> {
> - arm_gen_condlabel(s);
> - arm_gen_test_cc(cond ^ 1, s->condlabel);
> + /*
> + * Conditionally skip the insn. Note that both 0xe and 0xf mean
> + * "always"; 0xf is not "never".
> + */
> + if (cond < 0xe) {
> + arm_gen_condlabel(s);
> + arm_gen_test_cc(cond ^ 1, s->condlabel);
> + }
> }
>
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
> @@ -7944,11 +7950,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> }
> goto illegal_op;
> }
> - if (cond != 0xe) {
> - /* if not always execute, we generate a conditional jump to
> - next instruction */
> - arm_skip_unless(s, cond);
> - }
> +
> + arm_skip_unless(s, cond);
> +
> if ((insn & 0x0f900000) == 0x03000000) {
> if ((insn & (1 << 21)) == 0) {
> ARCH(6T2);
> @@ -12095,15 +12099,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> dc->insn = insn;
>
> if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
> - uint32_t cond = dc->condexec_cond;
> -
> - /*
> - * Conditionally skip the insn. Note that both 0xe and 0xf mean
> - * "always"; 0xf is not "never".
> - */
> - if (cond < 0x0e) {
> - arm_skip_unless(dc, cond);
> - }
> + arm_skip_unless(dc, dc->condexec_cond);
> }
In the other callsites for arm_skip_unless() the cond argument
can never be 0xe or 0xf.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
@ 2019-07-29 14:42 ` Peter Maydell
2019-08-06 21:41 ` Philippe Mathieu-Daudé
2019-08-08 11:41 ` Aleksandar Markovic
2 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:42 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Add the infrastructure that will become the new decoder.
> No instructions adjusted so far.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++-
> target/arm/Makefile.objs | 18 +++++++++++++++
> target/arm/a32-uncond.decode | 23 ++++++++++++++++++
> target/arm/a32.decode | 23 ++++++++++++++++++
> target/arm/t32.decode | 20 ++++++++++++++++
> 5 files changed, 128 insertions(+), 1 deletion(-)
> create mode 100644 target/arm/a32-uncond.decode
> create mode 100644 target/arm/a32.decode
> create mode 100644 target/arm/t32.decode
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 36419025db..4738b91957 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7715,6 +7715,33 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
> }
> }
>
> +/*
> + * Include the generated decoders.
> + * Note that the T32 decoder reuses some of the trans_* functions
> + * initially declared by the A32 decoder, which results in duplicate
> + * declaration warnings. Suppress them.
> + */
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic push
> +# pragma GCC diagnostic ignored "-Wredundant-decls"
> +# ifdef __clang__
> +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> +# endif
> +#endif
> +
> +#include "decode-a32.inc.c"
> +#include "decode-a32-uncond.inc.c"
> +#include "decode-t32.inc.c"
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic pop
> +#endif
I'm not a great fan of having to use the diagnostic pragmas --
they seem a bit ugly and not very robust. Is this the only way?
> +
> +/*
> + * Legacy decoder.
> + */
> +
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
> {
> unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
> @@ -7733,7 +7760,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> return;
> }
> cond = insn >> 28;
> - if (cond == 0xf){
> +
> + if (cond == 0xf) {
> /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
> * choose to UNDEF. In ARMv5 and above the space is used
> * for miscellaneous unconditional instructions.
This whitespace fixup should probably be in its own patch.
> @@ -7741,6 +7769,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> ARCH(5);
>
> /* Unconditional instructions. */
> + if (disas_a32_uncond(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> if (((insn >> 25) & 7) == 1) {
> /* NEON Data processing. */
> if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
> @@ -7953,6 +7986,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
>
> arm_skip_unless(s, cond);
>
> + if (disas_a32(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> if ((insn & 0x0f900000) == 0x03000000) {
> if ((insn & (1 << 21)) == 0) {
> ARCH(6T2);
> @@ -9440,6 +9478,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> ARCH(6T2);
> }
>
> + if (disas_t32(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> rn = (insn >> 16) & 0xf;
> rs = (insn >> 12) & 0xf;
> rd = (insn >> 8) & 0xf;
> diff --git a/target/arm/a32.decode b/target/arm/a32.decode
> new file mode 100644
> index 0000000000..2d84a02861
> --- /dev/null
> +++ b/target/arm/a32.decode
> @@ -0,0 +1,23 @@
> +# A32 conditional instructions
> +#
> +# Copyright (c) 2019 Linaro, Ltd
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
> +
> +#
> +# This file is processed by scripts/decodetree.py
> +#
> +# All of the insn that have a COND field in insn[31:28] are here.
> +# All insns that have 0xf in insn[31:28] are in a32u.decode.
"a32-uncond.decode"
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
@ 2019-07-29 14:44 ` Peter Maydell
2019-08-06 21:43 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 14:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Unify the code sequence for generating an illegal opcode exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-vfp.inc.c | 3 +--
> target/arm/translate.c | 21 +++++++++++----------
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(This feels like it should go earlier in the patchset, before the
introduction of the decode skeletons ?)
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
@ 2019-07-29 15:25 ` Peter Maydell
2019-07-30 1:25 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-07-29 15:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do these all in one lump because these are all logically intertwined.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 747 ++++++++++++++++++++---------------------
> target/arm/a32.decode | 84 +++++
> target/arm/t32.decode | 91 +++++
> 3 files changed, 536 insertions(+), 386 deletions(-
I'm afraid this patch is too big for me to digest :-(
I just spent about half an hour trying to figure out whether
the changes just to the thumb dp-immediate insns were right
and didn't manage to work through it all.
> +
> +# Data-processing (immediate)
> +
> +%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot
> +%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm
> +
> +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot
> +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
> +@S_xri_rot ....... .... . rn:4 . ... .... ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
> +
> +{
> + TST_rri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot
> + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot
> +}
> +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot
> +{
> + MOV_rri 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot
> + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + MVN_rri 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot
> + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + TEQ_rri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot
> + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + CMN_rri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
> + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
> +}
> +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot
> +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
> +{
> + CMP_rri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot
> + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
> +}
> +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
> --
Why do we split it up into all these different kinds of patterns
where some insns have special cases for rn==15 and some have
special cases for rd==15 ?
The legacy decoder doesn't seem to do that -- it treats everything
the same.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-07-29 14:05 ` Peter Maydell
@ 2019-07-30 0:38 ` Richard Henderson
2019-08-06 10:00 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 0:38 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 7:05 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We currently have 3 different ways of computing the architectural
>> value of "PC" as seen in the ARM ARM.
>>
>> The value of s->pc has been incremented past the current insn,
>> but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
>> for t16, PC = s->pc + 2. These differing computations make it
>> impossible at present to unify the various code paths.
>>
>> Let s->pc_read hold the architectural value of PC for all cases.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/translate.h | 10 ++++++++
>> target/arm/translate.c | 53 ++++++++++++++++++------------------------
>> 2 files changed, 32 insertions(+), 31 deletions(-)
>>
>> diff --git a/target/arm/translate.h b/target/arm/translate.h
>> index a20f6e2056..2dfdd8ca66 100644
>> --- a/target/arm/translate.h
>> +++ b/target/arm/translate.h
>> @@ -9,7 +9,17 @@ typedef struct DisasContext {
>> DisasContextBase base;
>> const ARMISARegisters *isar;
>>
>> + /*
>> + * Summary of the various values for "PC":
>> + * base.pc_next -- the start of the current insn
>> + * pc -- the start of the next insn
>
> These are confusingly named -- logically "pc_next" ought to
> be the PC of the next instruction and "pc" ought to be
> that of the current one...
Yes, well. I don't quite remember why "pc_next" was chosen for this field. It
is the "next" upon entry to tr_foo_disas_insn(). Often the target will
increment s->base.pc_next immediately, so it will also be the "next" insn
throughout translation. Though that isn't currently the case for ARM.
Once most of the uses of s->pc get moved to s->pc_read, it might be reasonable
to rename the remaining "s->base.pc_next" -> "s->pc_orig" and "s->pc" ->
"s->base.pc_next". Perhaps that would be clearer, I'm not sure.
>> + * pc_read -- the value for "PC" in the ARM ARM;
>
> nit: this line should end with a colon, rather than a semicolon
Oops, typo.
>> + * in arm mode, the current insn + 8;
>> + * in thumb mode, the current insn + 4;
>> + * in aa64 mode, unused.
>> + */
>> target_ulong pc;
>> + target_ulong pc_read;
>> target_ulong page_start;
>> uint32_t insn;
>
> Why target_ulong rather than uint32_t, given this is
> aarch32 only?
I didn't know if it would stay aarch32 only and it seemed more natural to match
the types.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit
2019-07-29 14:15 ` Peter Maydell
@ 2019-07-30 0:51 ` Richard Henderson
2019-08-06 9:44 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 0:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 7:15 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Used only on the thumb side so far, but will be more obvious
>> once we start unifying the implementation of A32+T32.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/translate-vfp.inc.c | 34 +------
>> target/arm/translate.c | 163 +++++++++++++++------------------
>> 2 files changed, 76 insertions(+), 121 deletions(-)
>>
>> diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
>> index e7389bc057..4066b2febf 100644
>> --- a/target/arm/translate-vfp.inc.c
>> +++ b/target/arm/translate-vfp.inc.c
>> @@ -941,14 +941,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
>> offset = -offset;
>> }
>>
>> - if (s->thumb && a->rn == 15) {
>> - /* This is actually UNPREDICTABLE */
>> - addr = tcg_temp_new_i32();
>> - tcg_gen_movi_i32(addr, s->pc & ~2);
>> - } else {
>> - addr = load_reg(s, a->rn);
>> - }
>> - tcg_gen_addi_i32(addr, addr, offset);
>> + addr = add_reg_for_lit(s, a->rn, offset);
>> tmp = tcg_temp_new_i32();
>> if (a->l) {
>> gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
>> @@ -983,14 +976,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
>> offset = -offset;
>> }
>>
>> - if (s->thumb && a->rn == 15) {
>> - /* This is actually UNPREDICTABLE */
>> - addr = tcg_temp_new_i32();
>> - tcg_gen_movi_i32(addr, s->pc & ~2);
>> - } else {
>> - addr = load_reg(s, a->rn);
>> - }
>> - tcg_gen_addi_i32(addr, addr, offset);
>> + addr = add_reg_for_lit(s, a->rn, offset);
>> tmp = tcg_temp_new_i64();
>> if (a->l) {
>> gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
>> @@ -1029,13 +1015,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
>> return true;
>> }
>>
>> - if (s->thumb && a->rn == 15) {
>> - /* This is actually UNPREDICTABLE */
>> - addr = tcg_temp_new_i32();
>> - tcg_gen_movi_i32(addr, s->pc & ~2);
>> - } else {
>> - addr = load_reg(s, a->rn);
>> - }
>> + addr = add_reg_for_lit(s, a->rn, 0);
>> if (a->p) {
>> /* pre-decrement */
>> tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
>> @@ -1112,13 +1092,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
>> return true;
>> }
>>
>> - if (s->thumb && a->rn == 15) {
>> - /* This is actually UNPREDICTABLE */
>> - addr = tcg_temp_new_i32();
>> - tcg_gen_movi_i32(addr, s->pc & ~2);
>> - } else {
>> - addr = load_reg(s, a->rn);
>> - }
>> + addr = add_reg_for_lit(s, a->rn, 0);
>> if (a->p) {
>> /* pre-decrement */
>> tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
>> diff --git a/target/arm/translate.c b/target/arm/translate.c
>> index a48e9a90f8..5e2dd8bb16 100644
>> --- a/target/arm/translate.c
>> +++ b/target/arm/translate.c
>> @@ -214,6 +214,23 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
>> return tmp;
>> }
>>
>> +/*
>> + * Create a new temp, incremented by OFS, except PC is aligned but not
>> + * incremented for thumb. This is used for load/store for which use of
>> + * PC implies (literal), or ADD that implies ADR.
>> + */
>> +static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
>> +{
>> + TCGv_i32 tmp = tcg_temp_new_i32();
>> +
>> + if (reg == 15) {
>> + tcg_gen_movi_i32(tmp, (s->pc_read & ~3) + ofs);
>> + } else {
>> + tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
>> + }
>> + return tmp;
>> +}
>
> This is losing the information in the comments about the UNPREDICTABLE
> cases. Are there callsites where the new function is called where
> "thumb and reg == 15" is not UNPREDICTABLE, or are they all
> that way?
These call sites are that way, but this function will eventually be used for
LDR (literal) and ADR, which obviously are not UNPREDICTABLE.
I don't think this comment attached to this code is useful as-is. Either we do
the natural a32-ish behaviour and use ALIGN(PC,4), or we should
gen_illegal_op() and be done with it.
Would you prefer a function like
/* Use of PC is UNPREDICTABLE in thumb mode, but allowed in arm mode. */
static TCGv_i32 load_reg_nothumbpc(DisasContext *s, int reg)
{
if (unlikely(reg == 15) && s->thumb) {
gen_illegal_op(s);
/* Unreachable tcg ops will be deleted but must still be legal. */
return tcg_const_i32(0);
}
return load_reg(s, reg);
}
for these specific usages?
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless
2019-07-29 14:32 ` Peter Maydell
@ 2019-07-30 0:57 ` Richard Henderson
2019-07-30 8:49 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 0:57 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 7:32 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We will shortly be calling this function much more often.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/translate.c | 28 ++++++++++++----------------
>> 1 file changed, 12 insertions(+), 16 deletions(-)
>>
>> diff --git a/target/arm/translate.c b/target/arm/translate.c
>> index 53c46fcdc4..36419025db 100644
>> --- a/target/arm/translate.c
>> +++ b/target/arm/translate.c
>> @@ -7705,8 +7705,14 @@ static void arm_gen_condlabel(DisasContext *s)
>> /* Skip this instruction if the ARM condition is false */
>> static void arm_skip_unless(DisasContext *s, uint32_t cond)
>> {
>> - arm_gen_condlabel(s);
>> - arm_gen_test_cc(cond ^ 1, s->condlabel);
>> + /*
>> + * Conditionally skip the insn. Note that both 0xe and 0xf mean
>> + * "always"; 0xf is not "never".
>> + */
>> + if (cond < 0xe) {
>> + arm_gen_condlabel(s);
>> + arm_gen_test_cc(cond ^ 1, s->condlabel);
>> + }
>> }
>>
>> static void disas_arm_insn(DisasContext *s, unsigned int insn)
>> @@ -7944,11 +7950,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
>> }
>> goto illegal_op;
>> }
>> - if (cond != 0xe) {
>> - /* if not always execute, we generate a conditional jump to
>> - next instruction */
>> - arm_skip_unless(s, cond);
>> - }
>> +
>> + arm_skip_unless(s, cond);
>> +
>> if ((insn & 0x0f900000) == 0x03000000) {
>> if ((insn & (1 << 21)) == 0) {
>> ARCH(6T2);
>> @@ -12095,15 +12099,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>> dc->insn = insn;
>>
>> if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
>> - uint32_t cond = dc->condexec_cond;
>> -
>> - /*
>> - * Conditionally skip the insn. Note that both 0xe and 0xf mean
>> - * "always"; 0xf is not "never".
>> - */
>> - if (cond < 0x0e) {
>> - arm_skip_unless(dc, cond);
>> - }
>> + arm_skip_unless(dc, dc->condexec_cond);
>> }
>
> In the other callsites for arm_skip_unless() the cond argument
> can never be 0xe or 0xf.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
In my original version I included cond in the fields collected by decodetree,
and so every single trans_* function called arm_skip_unless, so that would not
be the case there.
I discarded that in the version posted here, but I still think it might be a
cleaner design overall.
In the short term, maybe I should just discard this patch?
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
2019-07-29 15:25 ` Peter Maydell
@ 2019-07-30 1:25 ` Richard Henderson
0 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 1:25 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 8:25 AM, Peter Maydell wrote:
> I'm afraid this patch is too big for me to digest :-(
>
> I just spent about half an hour trying to figure out whether
> the changes just to the thumb dp-immediate insns were right
> and didn't manage to work through it all.
Hmm. It is probably the largest of the patches, and is caused by me trying to
do all of the insns handled by that one A32 code block.
I could perhaps split this to add fewer insns at a time, but I'd have to leave
the legacy decoder alone until the last patch, when it would go away all at
once. I'm not sure if that is more or less reviewable.
> Why do we split it up into all these different kinds of patterns
> where some insns have special cases for rn==15 and some have
> special cases for rd==15 ?
> The legacy decoder doesn't seem to do that -- it treats everything
> the same.
It sorta special cases them, without actually diagnosing the UNPREDICTABLE
cases of invalid unused operands.
ARM MOV + MVN special cases:
> - if (op1 != 0x0f && op1 != 0x0d) {
> - rn = (insn >> 16) & 0xf;
> - tmp = load_reg(s, rn);
> - } else {
> - tmp = NULL;
> - }
...
> - if (op1 != 0x0f && op1 != 0x0d) {
> - tcg_temp_free_i32(tmp2);
> - }
Here we have TST, TEQ, CMP, CMN:
> - case 0x08:
> - if (set_cc) {
> - tcg_gen_and_i32(tmp, tmp, tmp2);
> - gen_logic_CC(tmp);
> - }
> - tcg_temp_free_i32(tmp);
> - break;
> - case 0x09:
> - if (set_cc) {
> - tcg_gen_xor_i32(tmp, tmp, tmp2);
> - gen_logic_CC(tmp);
> - }
> - tcg_temp_free_i32(tmp);
> - break;
> - case 0x0a:
> - if (set_cc) {
> - gen_sub_CC(tmp, tmp, tmp2);
> - }
> - tcg_temp_free_i32(tmp);
> - break;
> - case 0x0b:
> - if (set_cc) {
> - gen_add_CC(tmp, tmp, tmp2);
> - }
> - tcg_temp_free_i32(tmp);
> - break;
I don't see bit 20 (set_cc) as even being optional in the decode, though rd is
RES0/SBZ and is thus ignoring it is valid for CONSTRAINED UNPREDICTABLE.
Thumb2 MOV, MVN (and the rest UNPREDICTABLE):
> /* Data processing register constant shift. */
> - if (rn == 15) {
> - tmp = tcg_temp_new_i32();
> - tcg_gen_movi_i32(tmp, 0);
> - } else {
> - tmp = load_reg(s, rn);
> - }
...
> - if (rn == 15) {
> - tmp = tcg_temp_new_i32();
> - tcg_gen_movi_i32(tmp, 0);
> - } else {
> - tmp = load_reg(s, rn);
> - }
TST, TEQ, CMP, CMN (and the rest UNPREDICTABLE):
> - } else if (rd != 15) {
> - store_reg(s, rd, tmp);
> - } else {
> - tcg_temp_free_i32(tmp);
> - }
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits
2019-07-29 13:43 ` Peter Maydell
@ 2019-07-30 1:30 ` Richard Henderson
0 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 1:30 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 6:43 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> With this, we can have the function return a value from the DisasContext.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> scripts/decodetree.py | 5 ++++-
>> tests/decode/succ_function.decode | 2 ++
>> 2 files changed, 6 insertions(+), 1 deletion(-)
>> create mode 100644 tests/decode/succ_function.decode
>>
>> diff --git a/scripts/decodetree.py b/scripts/decodetree.py
>> index d7a59d63ac..4259d87a95 100755
>> --- a/scripts/decodetree.py
>> +++ b/scripts/decodetree.py
>> @@ -195,7 +195,10 @@ class MultiField:
>> """Class representing a compound instruction field"""
>> def __init__(self, subs, mask):
>> self.subs = subs
>> - self.sign = subs[0].sign
>> + if len(subs):
>> + self.sign = subs[0].sign
>> + else:
>> + self.sign = 0
>> self.mask = mask
>>
>> def __str__(self):
>> diff --git a/tests/decode/succ_function.decode b/tests/decode/succ_function.decode
>> new file mode 100644
>> index 0000000000..632a9de252
>> --- /dev/null
>> +++ b/tests/decode/succ_function.decode
>> @@ -0,0 +1,2 @@
>> +%foo !function=foo
>> +foo 00000000000000000000000000000000 %foo
>> --
>> 2.17.1
>
> Could you also update the documentation in docs/devel/decodetree.rst ?
>
> This code change looks like it also now allows definitions
> of fields that specify nothing at all (ie there's no check
> that a field definition with no "unnamed_field" parts has
> a !function specifier) -- what do they do, or should they
> be made syntax errors ?
Ah good point. Should be syntax errors.
> Is one of these functions which just returns a constant
> from no input bits still a "static int func(DisasContext *s, int x)"
> taking a pointless input argument, or is it now a
> "static int func(DisasContext *s)" ? I guess from the fact
> this code doesn't change the way a call is output that it
> is the former, but would the latter be cleaner ?
Right on both counts. Because of how the loop in MultiField is set up, x will
always be given 0. I'll see about cleaning this up.
In the meantime, fyi, this is used for setting the S bit for thumb1 insns,
where S=0 iff the insn is within an IT block.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn
2019-07-29 13:52 ` Peter Maydell
@ 2019-07-30 2:11 ` Richard Henderson
2019-08-06 9:55 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-07-30 2:11 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 7/29/19 6:52 AM, Peter Maydell wrote:
> I'm not so convinced about this one -- gen_exception_insn()
> and gen_exception_internal_insn() shouldn't have the
> same pattern of function prototype but different semantics
> like this, it's confusing. It happens that both the cases
> of wanting to generate an "internal" exception happen to want
> it to be taken with the PC being for the following insn,
> not the current one, but that seems more coincidence to
> me than anything else.
I don't like "offsets", because they don't work as expected between different
modes. Would you prefer the pc in full be passed in? Would you prefer that
the previous patches also pass in a pc, instead of implicitly using
base.pc_next (you had rationale vs patch 2 for why it was ok as-is).
Shall we shuffle these patches later, after the Great Renaming of Things Named
PC, as discussed wrt patch 6 (pc_read and friends), so that the "offset"
parameter immediately becomes the Right Sort of PC, rather than some
intermediary confusion?
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless
2019-07-30 0:57 ` Richard Henderson
@ 2019-07-30 8:49 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-07-30 8:49 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Tue, 30 Jul 2019 at 01:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/29/19 7:32 AM, Peter Maydell wrote:
> > On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> We will shortly be calling this function much more often.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> >
> > In the other callsites for arm_skip_unless() the cond argument
> > can never be 0xe or 0xf.
> >
> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> In my original version I included cond in the fields collected by decodetree,
> and so every single trans_* function called arm_skip_unless, so that would not
> be the case there.
That remark was more a note about why the change is ok and doesn't
change behaviour for the other callsites that the patch doesn't touch.
(It's the kind of thing it's helpful to note in a commit message to
show that you've thought about it.)
> I discarded that in the version posted here, but I still think it might be a
> cleaner design overall.
>
> In the short term, maybe I should just discard this patch?
I don't have a strong opinion either way. Putting the cond check
inside the function seems cleaner even if we're only calling it in
a few places, I think.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
@ 2019-08-05 15:32 ` Peter Maydell
2019-08-05 16:20 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-08-05 15:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 214 ++++++++++++++++++++++++-----------------
> target/arm/a32.decode | 17 ++++
> target/arm/t32.decode | 19 ++++
> 3 files changed, 163 insertions(+), 87 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index ee7d53dfa5..354a52d36c 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7376,21 +7376,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
> store_reg(s, rhigh, tmp);
> }
>
> -/* load a 32-bit value from a register and perform a 64-bit accumulate. */
> -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
> -{
> - TCGv_i64 tmp;
> - TCGv_i32 tmp2;
> -
> - /* Load value and extend to 64 bits. */
> - tmp = tcg_temp_new_i64();
> - tmp2 = load_reg(s, rlow);
> - tcg_gen_extu_i32_i64(tmp, tmp2);
> - tcg_temp_free_i32(tmp2);
> - tcg_gen_add_i64(val, val, tmp);
> - tcg_temp_free_i64(tmp);
> -}
> -
> +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
> +{
> + TCGv_i32 t0, t1, t2, zero;
> +
> + if (s->thumb
> + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
> + : !ENABLE_ARCH_6) {
> + return false;
> + }
> +
> + t0 = load_reg(s, a->rm);
> + t1 = load_reg(s, a->rn);
> + tcg_gen_mulu2_i32(t0, t1, t0, t1);
> + zero = tcg_const_i32(0);
> + t2 = load_reg(s, a->ra);
> + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
> + tcg_temp_free_i32(t2);
> + t2 = load_reg(s, a->rd);
> + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(zero);
> + store_reg(s, a->ra, t0);
> + store_reg(s, a->rd, t1);
> + return true;
> +
Is using mulu2/add2/add2 like this really generating better
code than the mulu_i64_i32 and 2 64-bit adds that we had before?
If we're going to change how we're generating code it would be
nice to at least mention it in the commit message...
> @@ -10292,13 +10337,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> }
> }
> if (op & 4) {
> - /* umaal */
> - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
> - tcg_temp_free_i64(tmp64);
> - goto illegal_op;
> - }
> - gen_addq_lo(s, tmp64, rs);
> - gen_addq_lo(s, tmp64, rd);
> + /* umaal, in decodetree */
> + goto illegal_op;
> } else if (op & 0x40) {
> /* 64-bit accumulate. */
> gen_addq(s, tmp64, rs, rd);
This doesn't seem to remove all of the Thumb insns we implement
in the decode tree from the legacy decoder.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
@ 2019-08-05 15:40 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-08-05 15:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 1 -
> target/arm/op_helper.c | 15 ---------
> target/arm/translate.c | 74 +++++++++++++++++++++++++++---------------
> target/arm/a32.decode | 10 ++++++
> target/arm/t32.decode | 9 +++++
> 5 files changed, 66 insertions(+), 43 deletions(-)
>
> +/*
> + * Saturating addition and subtraction
> + */
> +
> +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub)
> +{
> + TCGv_i32 t0, t1;
> +
> + if (s->thumb
> + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
> + : !ENABLE_ARCH_5TE) {
> + return false;
> + }
> +
> + t0 = load_reg(s, a->rm);
> + t1 = load_reg(s, a->rn);
> + if (doub) {
> + gen_helper_add_saturate(t1, cpu_env, t1, t1);
> + }
> + if (add) {
> + gen_helper_add_saturate(t0, cpu_env, t0, t1);
> + } else {
> + gen_helper_sub_saturate(t0, cpu_env, t0, t1);
> + }
> + tcg_temp_free_i32(t1);
> + store_reg(s, a->rd, t0);
> + return true;
> +}
> +
> - case 0x5: /* saturating add/subtract */
> - ARCH(5TE);
> - rd = (insn >> 12) & 0xf;
> - rn = (insn >> 16) & 0xf;
> - tmp = load_reg(s, rm);
> - tmp2 = load_reg(s, rn);
> - if (op1 & 2)
> - gen_helper_double_saturate(tmp2, cpu_env, tmp2);
> - if (op1 & 1)
> - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
> - else
> - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
> - tcg_temp_free_i32(tmp2);
> - store_reg(s, rd, tmp);
> - break;
This is changing the way we generate code in the middle
of also doing the refactoring. Could you not do this,
please (or where it really does make sense to do it then
call it out in the commit message)? It makes it harder
to review because now I have to read the patch for two
different changes at once...
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
` (67 preceding siblings ...)
2019-07-26 18:40 ` [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree no-reply
@ 2019-08-05 15:44 ` Peter Maydell
2019-08-05 21:26 ` Richard Henderson
68 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-08-05 15:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This unifies the implementation of the actual instructions
> for a32, t32, and t16. In order to make this happen, we
> need several preliminary cleanups. Most importantly to how
> we handle the architectural representation of PC.
I'd be happy to take the preliminary-cleanups part (subject
to the various review comments) without waiting for the
rest of the series to get respun.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate
2019-08-05 15:32 ` Peter Maydell
@ 2019-08-05 16:20 ` Richard Henderson
0 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-08-05 16:20 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 8/5/19 8:32 AM, Peter Maydell wrote:
>> -/* load a 32-bit value from a register and perform a 64-bit accumulate. */
>> -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
>> -{
>> - TCGv_i64 tmp;
>> - TCGv_i32 tmp2;
>> -
>> - /* Load value and extend to 64 bits. */
>> - tmp = tcg_temp_new_i64();
>> - tmp2 = load_reg(s, rlow);
>> - tcg_gen_extu_i32_i64(tmp, tmp2);
>> - tcg_temp_free_i32(tmp2);
>> - tcg_gen_add_i64(val, val, tmp);
>> - tcg_temp_free_i64(tmp);
>> -}
>> -
>
>> +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
>> +{
>> + TCGv_i32 t0, t1, t2, zero;
>> +
>> + if (s->thumb
>> + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
>> + : !ENABLE_ARCH_6) {
>> + return false;
>> + }
>> +
>> + t0 = load_reg(s, a->rm);
>> + t1 = load_reg(s, a->rn);
>> + tcg_gen_mulu2_i32(t0, t1, t0, t1);
>> + zero = tcg_const_i32(0);
>> + t2 = load_reg(s, a->ra);
>> + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
>> + tcg_temp_free_i32(t2);
>> + t2 = load_reg(s, a->rd);
>> + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
>> + tcg_temp_free_i32(t2);
>> + tcg_temp_free_i32(zero);
>> + store_reg(s, a->ra, t0);
>> + store_reg(s, a->rd, t1);
>> + return true;
>> +
>
> Is using mulu2/add2/add2 like this really generating better
> code than the mulu_i64_i32 and 2 64-bit adds that we had before?
> If we're going to change how we're generating code it would be
> nice to at least mention it in the commit message...
I didn't really think about the code generation difference, merely that it
seemed more obvious, given that all of the inputs are i32, and we need i32
outputs. I assumed it wasn't written like this in the first place because
tcg_gen_mulu2_i32 is relatively new.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
2019-08-05 15:44 ` Peter Maydell
@ 2019-08-05 21:26 ` Richard Henderson
2019-08-06 10:01 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-08-05 21:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 8/5/19 8:44 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> This unifies the implementation of the actual instructions
>> for a32, t32, and t16. In order to make this happen, we
>> need several preliminary cleanups. Most importantly to how
>> we handle the architectural representation of PC.
>
> I'd be happy to take the preliminary-cleanups part (subject
> to the various review comments) without waiting for the
> rest of the series to get respun.
I had an outstanding question re patch 4:
Message-ID: <c7a3ef78-d541-aa0a-21a5-8b4f48db1fd7@linaro.org>
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06520.html
and another re patch 6:
Message-ID: <09b930e2-0a92-25a3-4e26-8bea1f437039@linaro.org>
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06508.html
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit
2019-07-30 0:51 ` Richard Henderson
@ 2019-08-06 9:44 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-08-06 9:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Tue, 30 Jul 2019 at 01:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/29/19 7:15 AM, Peter Maydell wrote:
> > On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> Used only on the thumb side so far, but will be more obvious
> >> once we start unifying the implementation of A32+T32.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> > This is losing the information in the comments about the UNPREDICTABLE
> > cases. Are there callsites where the new function is called where
> > "thumb and reg == 15" is not UNPREDICTABLE, or are they all
> > that way?
>
> These call sites are that way, but this function will eventually be used for
> LDR (literal) and ADR, which obviously are not UNPREDICTABLE.
>
> I don't think this comment attached to this code is useful as-is. Either we do
> the natural a32-ish behaviour and use ALIGN(PC,4), or we should
> gen_illegal_op() and be done with it.
I think it's usually worth noting when something's UNPREDICTABLE
and we're choosing to take the falls-out-of-the-code behaviour,
that's all.
> Would you prefer a function like
>
> /* Use of PC is UNPREDICTABLE in thumb mode, but allowed in arm mode. */
> static TCGv_i32 load_reg_nothumbpc(DisasContext *s, int reg)
> {
> if (unlikely(reg == 15) && s->thumb) {
> gen_illegal_op(s);
> /* Unreachable tcg ops will be deleted but must still be legal. */
> return tcg_const_i32(0);
> }
> return load_reg(s, reg);
> }
>
> for these specific usages?
I definitely don't favour this -- all our "is this going to UNDEF"
checks should go right at the start before we generate any
TCG code at all for the insn. One of the things I'm hoping this
series cleans up is that the current decoder is quite bad at
sometimes detecting UNDEF conditions late (which then results
in warnings about potential leaks of TCG variables).
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn
2019-07-30 2:11 ` Richard Henderson
@ 2019-08-06 9:55 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-08-06 9:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Tue, 30 Jul 2019 at 03:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/29/19 6:52 AM, Peter Maydell wrote:
> > I'm not so convinced about this one -- gen_exception_insn()
> > and gen_exception_internal_insn() shouldn't have the
> > same pattern of function prototype but different semantics
> > like this, it's confusing. It happens that both the cases
> > of wanting to generate an "internal" exception happen to want
> > it to be taken with the PC being for the following insn,
> > not the current one, but that seems more coincidence to
> > me than anything else.
>
> I don't like "offsets", because they don't work as expected between different
> modes. Would you prefer the pc in full be passed in? Would you prefer that
> the previous patches also pass in a pc, instead of implicitly using
> base.pc_next (you had rationale vs patch 2 for why it was ok as-is).
>
> Shall we shuffle these patches later, after the Great Renaming of Things Named
> PC, as discussed wrt patch 6 (pc_read and friends), so that the "offset"
> parameter immediately becomes the Right Sort of PC, rather than some
> intermediary confusion?
I think what we're really trying to distinguish here is two
orthogonal sets of possibilities:
* take an exception, with the PC pointing to the following insn
* take an exception, with the PC pointing to the current insn
and also
* take an "internal" exception
* take a guest-visible exception
(of which we happen to only want 2 of the 4 possible flavours at
the moment). I don't particularly mind what API we use as long
as the naming/parameter setup cleanly separates out the two
orthogonal concerns such that you could have all four without
having to rename anything. Possibilities:
* have gen_exception{_internal,}_insn and
gen_exception{_internal,}_next_insn
* have the functions take a bool for "exception on this insn
or on next insn?" (not ideal because 'bool' parameters are
a bit opaque in meaning at the callsites)
* pass in the specific PC to use
PS: the "_insn" part of the function name isn't sacrosanct:
it sort of makes sense I think but if better names occur that
don't include it that's fine.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-07-30 0:38 ` Richard Henderson
@ 2019-08-06 10:00 ` Peter Maydell
2019-08-06 15:04 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-08-06 10:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Tue, 30 Jul 2019 at 01:39, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/29/19 7:05 AM, Peter Maydell wrote:
> > On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> We currently have 3 different ways of computing the architectural
> >> value of "PC" as seen in the ARM ARM.
> >>
> >> The value of s->pc has been incremented past the current insn,
> >> but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
> >> for t16, PC = s->pc + 2. These differing computations make it
> >> impossible at present to unify the various code paths.
> >>
> >> Let s->pc_read hold the architectural value of PC for all cases.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> >> target/arm/translate.h | 10 ++++++++
> >> target/arm/translate.c | 53 ++++++++++++++++++------------------------
> >> 2 files changed, 32 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/target/arm/translate.h b/target/arm/translate.h
> >> index a20f6e2056..2dfdd8ca66 100644
> >> --- a/target/arm/translate.h
> >> +++ b/target/arm/translate.h
> >> @@ -9,7 +9,17 @@ typedef struct DisasContext {
> >> DisasContextBase base;
> >> const ARMISARegisters *isar;
> >>
> >> + /*
> >> + * Summary of the various values for "PC":
> >> + * base.pc_next -- the start of the current insn
> >> + * pc -- the start of the next insn
> >
> > These are confusingly named -- logically "pc_next" ought to
> > be the PC of the next instruction and "pc" ought to be
> > that of the current one...
>
> Yes, well. I don't quite remember why "pc_next" was chosen for this field. It
> is the "next" upon entry to tr_foo_disas_insn(). Often the target will
> increment s->base.pc_next immediately, so it will also be the "next" insn
> throughout translation. Though that isn't currently the case for ARM.
>
> Once most of the uses of s->pc get moved to s->pc_read, it might be reasonable
> to rename the remaining "s->base.pc_next" -> "s->pc_orig" and "s->pc" ->
> "s->base.pc_next". Perhaps that would be clearer, I'm not sure.
Renaming pc_next would be a cross-target change, so let's put that
on the shelf for the moment. Maybe just put a TODO comment to the
effect that we could consider renaming in future ?
Or we could just copy s->base.pc_next into s->some_field_we_choose_the_name_of,
eating 8 unnecessary bytes in the DisasContext struct but giving us a more
uniform s->something for all of the different PC variants rather than
having one of them be in s->base.something.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
2019-08-05 21:26 ` Richard Henderson
@ 2019-08-06 10:01 ` Peter Maydell
0 siblings, 0 replies; 110+ messages in thread
From: Peter Maydell @ 2019-08-06 10:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Mon, 5 Aug 2019 at 22:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/5/19 8:44 AM, Peter Maydell wrote:
> > On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> This unifies the implementation of the actual instructions
> >> for a32, t32, and t16. In order to make this happen, we
> >> need several preliminary cleanups. Most importantly to how
> >> we handle the architectural representation of PC.
> >
> > I'd be happy to take the preliminary-cleanups part (subject
> > to the various review comments) without waiting for the
> > rest of the series to get respun.
>
> I had an outstanding question re patch 4:
> Message-ID: <c7a3ef78-d541-aa0a-21a5-8b4f48db1fd7@linaro.org>
> https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06520.html
>
> and another re patch 6:
> Message-ID: <09b930e2-0a92-25a3-4e26-8bea1f437039@linaro.org>
> https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06508.html
I've followed up to 4, 6 and 7 giving some thoughts on those.
Anywhere I've still not been very specific it's because I don't
have a clear idea of the right thing, so use your own judgement :-)
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-08-06 10:00 ` Peter Maydell
@ 2019-08-06 15:04 ` Richard Henderson
2019-08-06 15:21 ` Peter Maydell
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-08-06 15:04 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 8/6/19 3:00 AM, Peter Maydell wrote:
> Renaming pc_next would be a cross-target change, so let's put that
> on the shelf for the moment. Maybe just put a TODO comment to the
> effect that we could consider renaming in future ?
I wasn't suggesting renaming the cross-target variable.
I was suggesting shuffling around the current names, and using "pc_next" for
what it sounds like -- the pc of the next insn.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-08-06 15:04 ` Richard Henderson
@ 2019-08-06 15:21 ` Peter Maydell
2019-08-06 15:53 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Peter Maydell @ 2019-08-06 15:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On Tue, 6 Aug 2019 at 16:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/6/19 3:00 AM, Peter Maydell wrote:
> > Renaming pc_next would be a cross-target change, so let's put that
> > on the shelf for the moment. Maybe just put a TODO comment to the
> > effect that we could consider renaming in future ?
>
> I wasn't suggesting renaming the cross-target variable.
>
> I was suggesting shuffling around the current names, and using "pc_next" for
> what it sounds like -- the pc of the next insn.
Oh, I see, so incrementing base->pc_next after we load
the insn? Yeah, that would work too. Though it seems a bit
odd to me to have the target-specific code modifying
a field in the base struct -- that seems like it ought to
be purely for the generic TCG code to use.
thanks
-- PMM
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read
2019-08-06 15:21 ` Peter Maydell
@ 2019-08-06 15:53 ` Richard Henderson
0 siblings, 0 replies; 110+ messages in thread
From: Richard Henderson @ 2019-08-06 15:53 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Alex Bennée, QEMU Developers
On 8/6/19 8:21 AM, Peter Maydell wrote:
> On Tue, 6 Aug 2019 at 16:04, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 8/6/19 3:00 AM, Peter Maydell wrote:
>>> Renaming pc_next would be a cross-target change, so let's put that
>>> on the shelf for the moment. Maybe just put a TODO comment to the
>>> effect that we could consider renaming in future ?
>>
>> I wasn't suggesting renaming the cross-target variable.
>>
>> I was suggesting shuffling around the current names, and using "pc_next" for
>> what it sounds like -- the pc of the next insn.
>
> Oh, I see, so incrementing base->pc_next after we load
> the insn? Yeah, that would work too. Though it seems a bit
> odd to me to have the target-specific code modifying
> a field in the base struct -- that seems like it ought to
> be purely for the generic TCG code to use.
Part of the contract with translator.c is that base.pc_next is updated. See
arm_post_translate_insn.
The difference would be to update early, immediately after reading the insn
word, before decode, instead of delaying the update until the end after decode.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-07-29 14:42 ` Peter Maydell
@ 2019-08-06 21:41 ` Philippe Mathieu-Daudé
2019-08-08 11:41 ` Aleksandar Markovic
2 siblings, 0 replies; 110+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-06 21:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
On 7/26/19 7:49 PM, Richard Henderson wrote:
> Add the infrastructure that will become the new decoder.
> No instructions adjusted so far.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++-
> target/arm/Makefile.objs | 18 +++++++++++++++
> target/arm/a32-uncond.decode | 23 ++++++++++++++++++
> target/arm/a32.decode | 23 ++++++++++++++++++
> target/arm/t32.decode | 20 ++++++++++++++++
> 5 files changed, 128 insertions(+), 1 deletion(-)
> create mode 100644 target/arm/a32-uncond.decode
> create mode 100644 target/arm/a32.decode
> create mode 100644 target/arm/t32.decode
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 36419025db..4738b91957 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7715,6 +7715,33 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
> }
> }
>
> +/*
> + * Include the generated decoders.
> + * Note that the T32 decoder reuses some of the trans_* functions
> + * initially declared by the A32 decoder, which results in duplicate
> + * declaration warnings. Suppress them.
Ah! This has been bugging me with the various MIPS ISA for some time
too... Which makes me wonder if this shouldn't be "generated" using some
option when calling the decodetree script. Or have it notice the target
has dup declarations and automatically emit the guard.
> + */
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic push
> +# pragma GCC diagnostic ignored "-Wredundant-decls"
> +# ifdef __clang__
> +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> +# endif
> +#endif
> +
> +#include "decode-a32.inc.c"
> +#include "decode-a32-uncond.inc.c"
> +#include "decode-t32.inc.c"
[...]
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
2019-07-29 14:44 ` Peter Maydell
@ 2019-08-06 21:43 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 110+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-06 21:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, qemu-arm, alex.bennee
On 7/26/19 7:49 PM, Richard Henderson wrote:
> Unify the code sequence for generating an illegal opcode exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/translate-vfp.inc.c | 3 +--
> target/arm/translate.c | 21 +++++++++++----------
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
> index 4066b2febf..1b08930649 100644
> --- a/target/arm/translate-vfp.inc.c
> +++ b/target/arm/translate-vfp.inc.c
> @@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
>
> if (!s->vfp_enabled && !ignore_vfp_enabled) {
> assert(!arm_dc_feature(s, ARM_FEATURE_M));
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> return false;
> }
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 4738b91957..0f21ee9ce7 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -1279,6 +1279,12 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
> s->base.is_jmp = DISAS_NORETURN;
> }
>
> +static void gen_illegal_op(DisasContext *s)
> +{
> + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> + default_exception_el(s));
> +}
> +
> /* Force a TB lookup after an instruction that changes the CPU state. */
> static inline void gen_lookup_tb(DisasContext *s)
> {
> @@ -1309,8 +1315,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
> return;
> }
>
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> }
>
> static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
> @@ -7631,8 +7636,7 @@ static void gen_srs(DisasContext *s,
> }
>
> if (undef) {
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> return;
> }
>
> @@ -9299,8 +9303,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> break;
> default:
> illegal_op:
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> break;
> }
> }
> @@ -10990,8 +10993,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> }
> return;
> illegal_op:
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> }
>
> static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> @@ -11816,8 +11818,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> return;
> illegal_op:
> undef:
> - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
> - default_exception_el(s));
> + gen_illegal_op(s);
> }
>
> static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-07-29 14:42 ` Peter Maydell
2019-08-06 21:41 ` Philippe Mathieu-Daudé
@ 2019-08-08 11:41 ` Aleksandar Markovic
2019-08-08 15:43 ` Richard Henderson
2 siblings, 1 reply; 110+ messages in thread
From: Aleksandar Markovic @ 2019-08-08 11:41 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, open list:Stellaris, Alex Bennée, QEMU Developers
On Fri, Jul 26, 2019 at 8:05 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Add the infrastructure that will become the new decoder.
> No instructions adjusted so far.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++-
> target/arm/Makefile.objs | 18 +++++++++++++++
> target/arm/a32-uncond.decode | 23 ++++++++++++++++++
> target/arm/a32.decode | 23 ++++++++++++++++++
> target/arm/t32.decode | 20 ++++++++++++++++
> 5 files changed, 128 insertions(+), 1 deletion(-)
> create mode 100644 target/arm/a32-uncond.decode
> create mode 100644 target/arm/a32.decode
> create mode 100644 target/arm/t32.decode
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 36419025db..4738b91957 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7715,6 +7715,33 @@ static void arm_skip_unless(DisasContext *s,
> uint32_t cond)
> }
> }
>
> +/*
> + * Include the generated decoders.
> + * Note that the T32 decoder reuses some of the trans_* functions
> + * initially declared by the A32 decoder, which results in duplicate
> + * declaration warnings. Suppress them.
> + */
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic push
> +# pragma GCC diagnostic ignored "-Wredundant-decls"
> +# ifdef __clang__
> +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> +# endif
> +#endif
> +
>
This looks more like a "band aid" solution rather than the right one.
I find it surprising that in spite of ever-growing complexity and numerous
refinements of the decodetree module, it still generates code that causes
these complaints of the compiler.
Regards,
Aleksandar
> +#include "decode-a32.inc.c"
> +#include "decode-a32-uncond.inc.c"
> +#include "decode-t32.inc.c"
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic pop
> +#endif
> +
> +/*
> + * Legacy decoder.
> + */
> +
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
> {
> unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
> @@ -7733,7 +7760,8 @@ static void disas_arm_insn(DisasContext *s, unsigned
> int insn)
> return;
> }
> cond = insn >> 28;
> - if (cond == 0xf){
> +
> + if (cond == 0xf) {
> /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
> * choose to UNDEF. In ARMv5 and above the space is used
> * for miscellaneous unconditional instructions.
> @@ -7741,6 +7769,11 @@ static void disas_arm_insn(DisasContext *s,
> unsigned int insn)
> ARCH(5);
>
> /* Unconditional instructions. */
> + if (disas_a32_uncond(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> if (((insn >> 25) & 7) == 1) {
> /* NEON Data processing. */
> if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
> @@ -7953,6 +7986,11 @@ static void disas_arm_insn(DisasContext *s,
> unsigned int insn)
>
> arm_skip_unless(s, cond);
>
> + if (disas_a32(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> if ((insn & 0x0f900000) == 0x03000000) {
> if ((insn & (1 << 21)) == 0) {
> ARCH(6T2);
> @@ -9440,6 +9478,11 @@ static void disas_thumb2_insn(DisasContext *s,
> uint32_t insn)
> ARCH(6T2);
> }
>
> + if (disas_t32(s, insn)) {
> + return;
> + }
> + /* fall back to legacy decoder */
> +
> rn = (insn >> 16) & 0xf;
> rs = (insn >> 12) & 0xf;
> rd = (insn >> 8) & 0xf;
> diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
> index 5cafc1eb6c..7806b4dac0 100644
> --- a/target/arm/Makefile.objs
> +++ b/target/arm/Makefile.objs
> @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c:
> $(SRC_PATH)/target/arm/vfp-uncond.decode $(D
> $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@
> $<,\
> "GEN", $(TARGET_DIR)$@)
>
> +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode
> $(DECODETREE)
> + $(call quiet-command,\
> + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
> + "GEN", $(TARGET_DIR)$@)
> +
> +target/arm/decode-a32-uncond.inc.c:
> $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
> + $(call quiet-command,\
> + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@
> $<,\
> + "GEN", $(TARGET_DIR)$@)
> +
> +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode
> $(DECODETREE)
> + $(call quiet-command,\
> + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
> + "GEN", $(TARGET_DIR)$@)
> +
> target/arm/translate-sve.o: target/arm/decode-sve.inc.c
> target/arm/translate.o: target/arm/decode-vfp.inc.c
> target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
> +target/arm/translate.o: target/arm/decode-a32.inc.c
> +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
> +target/arm/translate.o: target/arm/decode-t32.inc.c
>
> obj-y += tlb_helper.o debug_helper.o
> obj-y += translate.o op_helper.o
> diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
> new file mode 100644
> index 0000000000..8dee26d3b6
> --- /dev/null
> +++ b/target/arm/a32-uncond.decode
> @@ -0,0 +1,23 @@
> +# A32 unconditional instructions
> +#
> +# Copyright (c) 2019 Linaro, Ltd
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <
> http://www.gnu.org/licenses/>.
> +
> +#
> +# This file is processed by scripts/decodetree.py
> +#
> +# All insns that have 0xf in insn[31:28] are decoded here.
> +# All of those that have a COND field in insn[31:28] are in a32.decode
> +#
> diff --git a/target/arm/a32.decode b/target/arm/a32.decode
> new file mode 100644
> index 0000000000..2d84a02861
> --- /dev/null
> +++ b/target/arm/a32.decode
> @@ -0,0 +1,23 @@
> +# A32 conditional instructions
> +#
> +# Copyright (c) 2019 Linaro, Ltd
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <
> http://www.gnu.org/licenses/>.
> +
> +#
> +# This file is processed by scripts/decodetree.py
> +#
> +# All of the insn that have a COND field in insn[31:28] are here.
> +# All insns that have 0xf in insn[31:28] are in a32u.decode.
> +#
> diff --git a/target/arm/t32.decode b/target/arm/t32.decode
> new file mode 100644
> index 0000000000..ac01fb6958
> --- /dev/null
> +++ b/target/arm/t32.decode
> @@ -0,0 +1,20 @@
> +# Thumb2 instructions
> +#
> +# Copyright (c) 2019 Linaro, Ltd
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <
> http://www.gnu.org/licenses/>.
> +
> +#
> +# This file is processed by scripts/decodetree.py
> +#
> --
> 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-08-08 11:41 ` Aleksandar Markovic
@ 2019-08-08 15:43 ` Richard Henderson
2019-08-09 10:31 ` Aleksandar Markovic
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-08-08 15:43 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Peter Maydell, open list:Stellaris, Alex Bennée, QEMU Developers
On 8/8/19 4:41 AM, Aleksandar Markovic wrote:
> +/*
> + * Include the generated decoders.
> + * Note that the T32 decoder reuses some of the trans_* functions
> + * initially declared by the A32 decoder, which results in duplicate
> + * declaration warnings. Suppress them.
> + */
> +
> +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> +# pragma GCC diagnostic push
> +# pragma GCC diagnostic ignored "-Wredundant-decls"
> +# ifdef __clang__
> +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> +# endif
> +#endif
> +
>
>
> This looks more like a "band aid" solution rather than the right one.
What would the "right" solution be, would you say?
A couple of days ago Phil suggested moving these pragmas into the generated
code, so that this need not be done by hand in the several targets that use
multiple decoders. That sounds reasonable to me.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-08-08 15:43 ` Richard Henderson
@ 2019-08-09 10:31 ` Aleksandar Markovic
2019-08-09 14:55 ` Richard Henderson
0 siblings, 1 reply; 110+ messages in thread
From: Aleksandar Markovic @ 2019-08-09 10:31 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, open list:Stellaris, Alex Bennée, QEMU Developers
On Thu, Aug 8, 2019 at 5:43 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 8/8/19 4:41 AM, Aleksandar Markovic wrote:
> > +/*
> > + * Include the generated decoders.
> > + * Note that the T32 decoder reuses some of the trans_* functions
> > + * initially declared by the A32 decoder, which results in duplicate
> > + * declaration warnings. Suppress them.
> > + */
> > +
> > +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> > +# pragma GCC diagnostic push
> > +# pragma GCC diagnostic ignored "-Wredundant-decls"
> > +# ifdef __clang__
> > +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> > +# endif
> > +#endif
> > +
> >
> >
> > This looks more like a "band aid" solution rather than the right one.
>
> What would the "right" solution be, would you say?
>
>
The right (without quotation marks) solution is not to generate the code
that generates compiler complaints.
However, I do not say that this is a stopping issue for this series.
Perhaps at some time in future you can think of ways that would achieve not
resorting to pragmas. Obviously, in this case, decodetree-generated code
shows that it is inferior to human-generated code. Still, for now, go ahead
with this patch, as far as I am concerned.
Yours,
Aleksandar
> A couple of days ago Phil suggested moving these pragmas into the generated
> code, so that this need not be done by hand in the several targets that use
> multiple decoders. That sounds reasonable to me.
>
>
> r~
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-08-09 10:31 ` Aleksandar Markovic
@ 2019-08-09 14:55 ` Richard Henderson
2019-08-09 15:30 ` Aleksandar Markovic
0 siblings, 1 reply; 110+ messages in thread
From: Richard Henderson @ 2019-08-09 14:55 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Peter Maydell, open list:Stellaris, Alex Bennée, QEMU Developers
On 8/9/19 3:31 AM, Aleksandar Markovic wrote:
>
>
> On Thu, Aug 8, 2019 at 5:43 PM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>
> On 8/8/19 4:41 AM, Aleksandar Markovic wrote:
> > +/*
> > + * Include the generated decoders.
> > + * Note that the T32 decoder reuses some of the trans_* functions
> > + * initially declared by the A32 decoder, which results in duplicate
> > + * declaration warnings. Suppress them.
> > + */
> > +
> > +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> > +# pragma GCC diagnostic push
> > +# pragma GCC diagnostic ignored "-Wredundant-decls"
> > +# ifdef __clang__
> > +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> > +# endif
> > +#endif
> > +
> >
> >
> > This looks more like a "band aid" solution rather than the right one.
>
> What would the "right" solution be, would you say?
>
>
> The right (without quotation marks) solution is not to generate the code that
> generates compiler complaints.
That would be impossible with the information supplied.
Emitting zero declarations will result in invalid C. We ensure that each
individual decodetree file does not emit duplicates. However, there is no
knowledge across separate decodetree files about which declarations are duplicate.
In this particular case, I do not even agree that the warnings themselves are
useful. I suppose it's not impossible that they could diagnose some weirdness
in a code base, where a function is declared in multiple headers or a patch
application has gone awry leaving multiple sequential declarations, but
honestly how often does that happen?
I suppose with some work, we could not invoke decodetree multiple times, but
give it all of the input files at once, producing a single output file.
> Obviously, in this case, decodetree-generated code shows that it is
> inferior to human-generated code.
That is not obvious at all. Moreover, I disagree strongly.
r~
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree
2019-08-09 14:55 ` Richard Henderson
@ 2019-08-09 15:30 ` Aleksandar Markovic
0 siblings, 0 replies; 110+ messages in thread
From: Aleksandar Markovic @ 2019-08-09 15:30 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, open list:Stellaris, Alex Bennée, QEMU Developers
On Fri, Aug 9, 2019 at 4:55 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 8/9/19 3:31 AM, Aleksandar Markovic wrote:
> >
> >
> > On Thu, Aug 8, 2019 at 5:43 PM Richard Henderson <
> richard.henderson@linaro.org
> > <mailto:richard.henderson@linaro.org>> wrote:
> >
> > On 8/8/19 4:41 AM, Aleksandar Markovic wrote:
> > > +/*
> > > + * Include the generated decoders.
> > > + * Note that the T32 decoder reuses some of the trans_*
> functions
> > > + * initially declared by the A32 decoder, which results in
> duplicate
> > > + * declaration warnings. Suppress them.
> > > + */
> > > +
> > > +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
> > > +# pragma GCC diagnostic push
> > > +# pragma GCC diagnostic ignored "-Wredundant-decls"
> > > +# ifdef __clang__
> > > +# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> > > +# endif
> > > +#endif
> > > +
> > >
> > >
> > > This looks more like a "band aid" solution rather than the right
> one.
> >
> > What would the "right" solution be, would you say?
> >
> >
> > The right (without quotation marks) solution is not to generate the code
> that
> > generates compiler complaints.
>
> That would be impossible with the information supplied.
>
That limitation is a fault of decodetree design, not an obstacle per se.
> Emitting zero declarations will result in invalid C. We ensure that each
> individual decodetree file does not emit duplicates. However, there is no
> knowledge across separate decodetree files about which declarations are
> duplicate.
>
> In this particular case, I do not even agree that the warnings themselves
> are
> useful. I suppose it's not impossible that they could diagnose some
> weirdness
> in a code base, where a function is declared in multiple headers or a patch
> application has gone awry leaving multiple sequential declarations, but
> honestly how often does that happen?
>
> I suppose with some work, we could not invoke decodetree multiple times,
> but
> give it all of the input files at once, producing a single output file.
>
>
> > Obviously, in this case, decodetree-generated code shows that it is
> > inferior to human-generated code.
>
> That is not obvious at all. Moreover, I disagree strongly.
>
>
OK. I'm fine with your disagreeing. That why open source exists - to have
opportunities to hear different views.
Yours,
Aleksandar
> r~
>
^ permalink raw reply [flat|nested] 110+ messages in thread
end of thread, other threads:[~2019-08-09 15:31 UTC | newest]
Thread overview: 110+ messages (download: mbox.gz / follow: Atom feed)
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2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
2019-07-29 13:43 ` Peter Maydell
2019-07-30 1:30 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
2019-07-29 13:48 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
2019-07-29 13:50 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
2019-07-29 13:52 ` Peter Maydell
2019-07-30 2:11 ` Richard Henderson
2019-08-06 9:55 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
2019-07-29 13:54 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
2019-07-29 14:05 ` Peter Maydell
2019-07-30 0:38 ` Richard Henderson
2019-08-06 10:00 ` Peter Maydell
2019-08-06 15:04 ` Richard Henderson
2019-08-06 15:21 ` Peter Maydell
2019-08-06 15:53 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
2019-07-29 14:15 ` Peter Maydell
2019-07-30 0:51 ` Richard Henderson
2019-08-06 9:44 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-07-29 14:26 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
2019-07-29 14:27 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
2019-07-29 14:32 ` Peter Maydell
2019-07-30 0:57 ` Richard Henderson
2019-07-30 8:49 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-07-29 14:42 ` Peter Maydell
2019-08-06 21:41 ` Philippe Mathieu-Daudé
2019-08-08 11:41 ` Aleksandar Markovic
2019-08-08 15:43 ` Richard Henderson
2019-08-09 10:31 ` Aleksandar Markovic
2019-08-09 14:55 ` Richard Henderson
2019-08-09 15:30 ` Aleksandar Markovic
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
2019-07-29 14:44 ` Peter Maydell
2019-08-06 21:43 ` Philippe Mathieu-Daudé
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
2019-07-29 15:25 ` Peter Maydell
2019-07-30 1:25 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-05 15:32 ` Peter Maydell
2019-08-05 16:20 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-05 15:40 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 39/67] target/arm: Convert SG Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 40/67] target/arm: Convert TT Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
2019-07-26 18:13 ` Peter Maydell
2019-07-26 18:34 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i Richard Henderson
2019-07-26 18:40 ` [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-05 15:44 ` Peter Maydell
2019-08-05 21:26 ` Richard Henderson
2019-08-06 10:01 ` Peter Maydell
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