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* [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC
@ 2023-09-11 13:53 Peter Maydell
  2023-09-11 13:53 ` [PATCH 1/7] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
                   ` (7 more replies)
  0 siblings, 8 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

This patchset started off as "implement FEAT_HBC" but I ended
up finding I needed to do a bit of cleanup regarding the elf
hwcaps bits, so most of the patchset is that cleanup and the
FEAT_HBC is the simple patch at the end.

Patch 1 is the ID_AA64ISAR2_EL1 that's been on the list multiple
times already. It's in a target-arm pullreq that's already on
the list, so I've only included it here so the series compiles
as a standalone patchset.

Patch 2 is a bugfix for some errors in feature string names
in the emulated /proc/cpuinfo.

Patches 3-6 update our definitions of hwcap bit values from the
current Linux kernel source tree, our ID register field definitions
from the current public system register XML, and make sure we're
in sync with the kernel about what hwcap bits we report and what
ID register fields we expose to user-only guest processes.
(The only actual bug fixed here is some missing arm32 hwcap bits,
but the rest of the changes are useful to, for instance, let us
add FEAT_HBC support.)

Patch 7 is the actual FEAT_HBC support. This feature is a variant
on the B.cond conditional branch that provides some hint
information to the branch predictor; since we don't do branch
prediction this is easy for us to implement.

Patch 7 will have an obvious trivial textual conflict with
the FEAT_MOPS work; I suspect this will get in first, since it's
much simpler. I also forgot about the hwcap for FEAT_MOPS, but
once these patches are applied that is a one-liner fix to add
the GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS).

thanks
-- PMM

Aaron Lindsay (1):
  target/arm: Add ID_AA64ISAR2_EL1

Peter Maydell (6):
  linux-user/elfload.c: Correct SME feature names reported in cpuinfo
  linux-user/elfload.c: Add missing arm and arm64 hwcap values
  linux-user/elfload.c: Report previously missing arm32 hwcaps
  target/arm: Update AArch64 ID register field definitions
  target/arm: Update user-mode ID reg mask values
  target/arm: Implement FEAT_HBC

 docs/system/arm/emulation.rst  |  1 +
 target/arm/cpu.h               | 28 ++++++++++++++
 target/arm/tcg/a64.decode      |  3 +-
 linux-user/elfload.c           | 71 ++++++++++++++++++++++++++++++----
 target/arm/helper.c            | 15 +++++--
 target/arm/hvf/hvf.c           |  1 +
 target/arm/kvm64.c             |  2 +
 target/arm/tcg/cpu64.c         |  4 ++
 target/arm/tcg/translate-a64.c |  4 ++
 9 files changed, 118 insertions(+), 11 deletions(-)

-- 
2.34.1



^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 1/7] target/arm: Add ID_AA64ISAR2_EL1
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 13:53 ` [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo Peter Maydell
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

From: Aaron Lindsay <aaron@os.amperecomputing.com>

Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
[PMM: drop the HVF part of the patch and just comment that
 we need to do something when the register appears in that API]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     | 1 +
 target/arm/helper.c  | 4 ++--
 target/arm/hvf/hvf.c | 1 +
 target/arm/kvm64.c   | 2 ++
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d50cd918580..e637796fd83 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1033,6 +1033,7 @@ struct ArchCPU {
         uint32_t dbgdevid1;
         uint64_t id_aa64isar0;
         uint64_t id_aa64isar1;
+        uint64_t id_aa64isar2;
         uint64_t id_aa64pfr0;
         uint64_t id_aa64pfr1;
         uint64_t id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e3f5a7d2bdc..f9f7c3c39e9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8435,11 +8435,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
               .resetvalue = cpu->isar.id_aa64isar1 },
-            { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
-              .resetvalue = 0 },
+              .resetvalue = cpu->isar.id_aa64isar2 },
             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 486f90be1d2..546c0e817f4 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -847,6 +847,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
         { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
         { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
+        /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
         { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
         { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
         { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 4d904a1d11b..ac440c33f9a 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -304,6 +304,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 6, 0));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
                               ARM64_SYS_REG(3, 0, 0, 6, 1));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
+                              ARM64_SYS_REG(3, 0, 0, 6, 2));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
                               ARM64_SYS_REG(3, 0, 0, 7, 0));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
  2023-09-11 13:53 ` [PATCH 1/7] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 14:51   ` Philippe Mathieu-Daudé
  2023-09-11 13:53 ` [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values Peter Maydell
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

Some of the names we use for CPU features in linux-user's dummy
/proc/cpuinfo don't match the strings in the real kernel in
arch/arm64/kernel/cpuinfo.c. Specifically, the SME related
features have an underscore in the HWCAP_FOO define name,
but (like the SVE ones) they do not have an underscore in the
string in cpuinfo. Correct the errors.

Fixes: a55b9e7226708 ("linux-user: Emulate /proc/cpuinfo on aarch64 and arm")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/elfload.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index a5b28fa3e7a..5ce009d7137 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -844,13 +844,13 @@ const char *elf_hwcap2_str(uint32_t bit)
     [__builtin_ctz(ARM_HWCAP2_A64_RPRES        )] = "rpres",
     [__builtin_ctz(ARM_HWCAP2_A64_MTE3         )] = "mte3",
     [__builtin_ctz(ARM_HWCAP2_A64_SME          )] = "sme",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64   )] = "sme_i16i64",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64   )] = "sme_f64f64",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32    )] = "sme_i8i32",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32   )] = "sme_f16f32",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32   )] = "sme_b16f32",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32   )] = "sme_f32f32",
-    [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64     )] = "sme_fa64",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64   )] = "smei16i64",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64   )] = "smef64f64",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32    )] = "smei8i32",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32   )] = "smef16f32",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32   )] = "smeb16f32",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32   )] = "smef32f32",
+    [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64     )] = "smefa64",
     };
 
     return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
  2023-09-11 13:53 ` [PATCH 1/7] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
  2023-09-11 13:53 ` [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 14:59   ` Philippe Mathieu-Daudé
  2023-09-11 13:53 ` [PATCH 4/7] linux-user/elfload.c: Report previously missing arm32 hwcaps Peter Maydell
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

Our lists of Arm 32 and 64 bit hwcap values have lagged behind
the Linux kernel. Update them to include all the bits defined
as of upstream Linux git commit a48fa7efaf1161c1 (in the middle
of the kernel 6.6 dev cycle).

For 64-bit, we don't yet implement any of the features reported via
these hwcap bits.  For 32-bit we do in fact already implement them
all; we'll add the code to set them in a subsequent commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/elfload.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 5ce009d7137..d51d077998a 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -402,6 +402,12 @@ enum
     ARM_HWCAP_ARM_VFPD32    = 1 << 19,
     ARM_HWCAP_ARM_LPAE      = 1 << 20,
     ARM_HWCAP_ARM_EVTSTRM   = 1 << 21,
+    ARM_HWCAP_ARM_FPHP      = 1 << 22,
+    ARM_HWCAP_ARM_ASIMDHP   = 1 << 23,
+    ARM_HWCAP_ARM_ASIMDDP   = 1 << 24,
+    ARM_HWCAP_ARM_ASIMDFHM  = 1 << 25,
+    ARM_HWCAP_ARM_ASIMDBF16 = 1 << 26,
+    ARM_HWCAP_ARM_I8MM      = 1 << 27,
 };
 
 enum {
@@ -410,6 +416,8 @@ enum {
     ARM_HWCAP2_ARM_SHA1     = 1 << 2,
     ARM_HWCAP2_ARM_SHA2     = 1 << 3,
     ARM_HWCAP2_ARM_CRC32    = 1 << 4,
+    ARM_HWCAP2_ARM_SB       = 1 << 5,
+    ARM_HWCAP2_ARM_SSBS     = 1 << 6,
 };
 
 /* The commpage only exists for 32 bit kernels */
@@ -540,6 +548,12 @@ const char *elf_hwcap_str(uint32_t bit)
     [__builtin_ctz(ARM_HWCAP_ARM_VFPD32   )] = "vfpd32",
     [__builtin_ctz(ARM_HWCAP_ARM_LPAE     )] = "lpae",
     [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM  )] = "evtstrm",
+    [__builtin_ctz(ARM_HWCAP_ARM_FPHP     )] = "fphp",
+    [__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP  )] = "asimdhp",
+    [__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP  )] = "asimddp",
+    [__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] = "asimdfhm",
+    [__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] = "asimdbf16",
+    [__builtin_ctz(ARM_HWCAP_ARM_I8MM     )] = "i8mm",
     };
 
     return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
@@ -553,6 +567,8 @@ const char *elf_hwcap2_str(uint32_t bit)
     [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] = "sha1",
     [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] = "sha2",
     [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] = "crc32",
+    [__builtin_ctz(ARM_HWCAP2_ARM_SB   )] = "sb",
+    [__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] = "ssbs",
     };
 
     return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
@@ -696,6 +712,20 @@ enum {
     ARM_HWCAP2_A64_SME_B16F32   = 1 << 28,
     ARM_HWCAP2_A64_SME_F32F32   = 1 << 29,
     ARM_HWCAP2_A64_SME_FA64     = 1 << 30,
+    ARM_HWCAP2_A64_WFXT         = 1ULL << 31,
+    ARM_HWCAP2_A64_EBF16        = 1ULL << 32,
+    ARM_HWCAP2_A64_SVE_EBF16    = 1ULL << 33,
+    ARM_HWCAP2_A64_CSSC         = 1ULL << 34,
+    ARM_HWCAP2_A64_RPRFM        = 1ULL << 35,
+    ARM_HWCAP2_A64_SVE2P1       = 1ULL << 36,
+    ARM_HWCAP2_A64_SME2         = 1ULL << 37,
+    ARM_HWCAP2_A64_SME2P1       = 1ULL << 38,
+    ARM_HWCAP2_A64_SME_I16I32   = 1ULL << 39,
+    ARM_HWCAP2_A64_SME_BI32I32  = 1ULL << 40,
+    ARM_HWCAP2_A64_SME_B16B16   = 1ULL << 41,
+    ARM_HWCAP2_A64_SME_F16F16   = 1ULL << 42,
+    ARM_HWCAP2_A64_MOPS         = 1ULL << 43,
+    ARM_HWCAP2_A64_HBC          = 1ULL << 44,
 };
 
 #define ELF_HWCAP   get_elf_hwcap()
@@ -851,6 +881,20 @@ const char *elf_hwcap2_str(uint32_t bit)
     [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32   )] = "smeb16f32",
     [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32   )] = "smef32f32",
     [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64     )] = "smefa64",
+    [__builtin_ctz(ARM_HWCAP2_A64_WFXT         )] = "wfxt",
+    [__builtin_ctzll(ARM_HWCAP2_A64_EBF16      )] = "ebf16",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16  )] = "sveebf16",
+    [__builtin_ctzll(ARM_HWCAP2_A64_CSSC       )] = "cssc",
+    [__builtin_ctzll(ARM_HWCAP2_A64_RPRFM      )] = "rprfm",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1     )] = "sve2p1",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME2       )] = "sme2",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME2P1     )] = "sme2p1",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] = "smei16i32",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] = "smebi32i32",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] = "smeb16b16",
+    [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] = "smef16f16",
+    [__builtin_ctzll(ARM_HWCAP2_A64_MOPS       )] = "mops",
+    [__builtin_ctzll(ARM_HWCAP2_A64_HBC        )] = "hbc",
     };
 
     return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 4/7] linux-user/elfload.c: Report previously missing arm32 hwcaps
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
                   ` (2 preceding siblings ...)
  2023-09-11 13:53 ` [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 13:53 ` [PATCH 5/7] target/arm: Update AArch64 ID register field definitions Peter Maydell
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

Add the code to report the arm32 hwcaps we were previously missing:
 ss, ssbs, fphp, asimdhp, asimddp, asimdfhm, asimdbf16, i8mm

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/elfload.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index d51d077998a..bbb4f08109c 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -506,6 +506,16 @@ uint32_t get_elf_hwcap(void)
         }
     }
     GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
+    /*
+     * MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same
+     * isar_feature function for both. The kernel reports them as two hwcaps.
+     */
+    GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP);
+    GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP);
+    GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP);
+    GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM);
+    GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16);
+    GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM);
 
     return hwcaps;
 }
@@ -520,6 +530,8 @@ uint32_t get_elf_hwcap2(void)
     GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
     GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
     GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
+    GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB);
+    GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS);
     return hwcaps;
 }
 
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 5/7] target/arm: Update AArch64 ID register field definitions
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
                   ` (3 preceding siblings ...)
  2023-09-11 13:53 ` [PATCH 4/7] linux-user/elfload.c: Report previously missing arm32 hwcaps Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 14:36   ` Peter Maydell
  2023-09-11 13:53 ` [PATCH 6/7] target/arm: Update user-mode ID reg mask values Peter Maydell
                   ` (2 subsequent siblings)
  7 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

Update our AArch64 ID register field definitions from the 2023-06
system register XML release:
 https://developer.arm.com/documentation/ddi0601/2023-06/

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
This is intended to allow updating the set of ID register
fields we expose for user-only mode, so I have only
updated the AArch64 ID registers, not AArch32.
---
 target/arm/cpu.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e637796fd83..eddf2d3b72c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2165,6 +2165,7 @@ FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
+FIELD(ID_AA64ISAR0, TME, 24, 4)
 FIELD(ID_AA64ISAR0, RDM, 28, 4)
 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
 FIELD(ID_AA64ISAR0, SM3, 36, 4)
@@ -2199,6 +2200,13 @@ FIELD(ID_AA64ISAR2, APA3, 12, 4)
 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
 FIELD(ID_AA64ISAR2, BC, 20, 4)
 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
+FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
+FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
+FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
+FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
+FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
+FIELD(ID_AA64ISAR2, CSSC, 52, 4)
+FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -2226,6 +2234,12 @@ FIELD(ID_AA64PFR1, SME, 24, 4)
 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
 FIELD(ID_AA64PFR1, NMI, 36, 4)
+FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
+FIELD(ID_AA64PFR1, GCS, 44, 4)
+FIELD(ID_AA64PFR1, THE, 48, 4)
+FIELD(ID_AA64PFR1, MTEX, 52, 4)
+FIELD(ID_AA64PFR1, DF2, 56, 4)
+FIELD(ID_AA64PFR1, PFAR, 60, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -2257,6 +2271,7 @@ FIELD(ID_AA64MMFR1, AFP, 44, 4)
 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
+FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -2278,7 +2293,9 @@ FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
 FIELD(ID_AA64DFR0, BRPS, 12, 4)
+FIELD(ID_AA64DFR0, PMSS, 16, 4)
 FIELD(ID_AA64DFR0, WRPS, 20, 4)
+FIELD(ID_AA64DFR0, SEBEP, 24, 4)
 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
@@ -2286,6 +2303,7 @@ FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 FIELD(ID_AA64DFR0, BRBE, 52, 4)
+FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
 
 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
@@ -2299,9 +2317,13 @@ FIELD(ID_AA64ZFR0, F32MM, 52, 4)
 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
 
 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
+FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
+FIELD(ID_AA64SMFR0, F16F16, 42, 1)
+FIELD(ID_AA64SMFR0, B16B16, 43, 1)
+FIELD(ID_AA64SMFR0, I16I32, 44, 4)
 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 6/7] target/arm: Update user-mode ID reg mask values
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
                   ` (4 preceding siblings ...)
  2023-09-11 13:53 ` [PATCH 5/7] target/arm: Update AArch64 ID register field definitions Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-21 15:03   ` Peter Maydell
  2023-09-11 13:53 ` [PATCH 7/7] target/arm: Implement FEAT_HBC Peter Maydell
  2023-09-12  0:44 ` [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Richard Henderson
  7 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

For user-only mode we reveal a subset of the AArch64 ID registers
to the guest, to emulate the kernel's trap-and-emulate-ID-regs
handling. Update the feature bit masks to match upstream kernel
commit a48fa7efaf1161c1c.

None of these features are yet implemented by QEMU, so this
doesn't yet have a behavioural change, but implementation of
FEAT_MOPS and FEAT_HBC is imminent.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index f9f7c3c39e9..ad84fcf041d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8621,11 +8621,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
                                R_ID_AA64ZFR0_F64MM_MASK },
             { .name = "ID_AA64SMFR0_EL1",
               .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
+                               R_ID_AA64SMFR0_BI32I32_MASK |
                                R_ID_AA64SMFR0_B16F32_MASK |
                                R_ID_AA64SMFR0_F16F32_MASK |
                                R_ID_AA64SMFR0_I8I32_MASK |
+                               R_ID_AA64SMFR0_F16F16_MASK |
+                               R_ID_AA64SMFR0_B16B16_MASK |
+                               R_ID_AA64SMFR0_I16I32_MASK |
                                R_ID_AA64SMFR0_F64F64_MASK |
                                R_ID_AA64SMFR0_I16I64_MASK |
+                               R_ID_AA64SMFR0_SMEVER_MASK |
                                R_ID_AA64SMFR0_FA64_MASK },
             { .name = "ID_AA64MMFR0_EL1",
               .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
@@ -8676,7 +8681,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
                                R_ID_AA64ISAR2_RPRES_MASK |
                                R_ID_AA64ISAR2_GPA3_MASK |
-                               R_ID_AA64ISAR2_APA3_MASK },
+                               R_ID_AA64ISAR2_APA3_MASK |
+                               R_ID_AA64ISAR2_MOPS_MASK |
+                               R_ID_AA64ISAR2_BC_MASK |
+                               R_ID_AA64ISAR2_RPRFM_MASK |
+                               R_ID_AA64ISAR2_CSSC_MASK },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
               .is_glob = true },
         };
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 7/7] target/arm: Implement FEAT_HBC
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
                   ` (5 preceding siblings ...)
  2023-09-11 13:53 ` [PATCH 6/7] target/arm: Update user-mode ID reg mask values Peter Maydell
@ 2023-09-11 13:53 ` Peter Maydell
  2023-09-11 15:01   ` Philippe Mathieu-Daudé
  2023-09-12  0:44 ` [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Richard Henderson
  7 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 13:53 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

FEAT_HBC (Hinted conditional branches) provides a new instruction
BC.cond, which behaves exactly like the existing B.cond except
that it provides a hint to the branch predictor about the
likely behaviour of the branch.

Since QEMU does not implement branch prediction, we can treat
this identically to B.cond.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst  | 1 +
 target/arm/cpu.h               | 5 +++++
 target/arm/tcg/a64.decode      | 3 ++-
 linux-user/elfload.c           | 1 +
 target/arm/tcg/cpu64.c         | 4 ++++
 target/arm/tcg/translate-a64.c | 4 ++++
 6 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 2e6a7c8961e..34429054a3f 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -39,6 +39,7 @@ the following architecture extensions:
 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
 - FEAT_GTG (Guest translation granule size)
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
+- FEAT_HBC (Hinted conditional branches)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
 - FEAT_HPDS2 (Translation table page-based hardware attributes)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index eddf2d3b72c..fc45f1fb9e2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4050,6 +4050,11 @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
 }
 
+static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
+}
+
 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
 {
     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index ef64a3f9cba..71113173020 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -126,7 +126,8 @@ CBZ             sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
 
 TBZ             . 011011 nz:1 ..... .............. rt:5 &tbz  imm=%imm14 bitpos=%imm31_19
 
-B_cond          0101010 0 ................... 0 cond:4 imm=%imm19
+# B.cond and BC.cond
+B_cond          0101010 0 ................... c:1 cond:4 imm=%imm19
 
 BR              1101011 0000 11111 000000 rn:5 00000 &r
 BLR             1101011 0001 11111 000000 rn:5 00000 &r
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index bbb4f08109c..203a2b790d5 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -815,6 +815,7 @@ uint32_t get_elf_hwcap2(void)
     GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64);
     GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64);
     GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64);
+    GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC);
 
     return hwcaps;
 }
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 0f8972950d6..90e033bbc3a 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -814,6 +814,10 @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
     cpu->isar.id_aa64isar1 = t;
 
+    t = cpu->isar.id_aa64isar2;
+    t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1);      /* FEAT_HBC */
+    cpu->isar.id_aa64isar2 = t;
+
     t = cpu->isar.id_aa64pfr0;
     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0b77c92437f..15eca55fc75 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1453,6 +1453,10 @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a)
 
 static bool trans_B_cond(DisasContext *s, arg_B_cond *a)
 {
+    /* BC.cond is only present with FEAT_HBC */
+    if (a->c && !dc_isar_feature(aa64_hbc, s)) {
+        return false;
+    }
     reset_btype(s);
     if (a->cond < 0x0e) {
         /* genuinely conditional branches */
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH 5/7] target/arm: Update AArch64 ID register field definitions
  2023-09-11 13:53 ` [PATCH 5/7] target/arm: Update AArch64 ID register field definitions Peter Maydell
@ 2023-09-11 14:36   ` Peter Maydell
  0 siblings, 0 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 14:36 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

On Mon, 11 Sept 2023 at 14:53, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Update our AArch64 ID register field definitions from the 2023-06
> system register XML release:
>  https://developer.arm.com/documentation/ddi0601/2023-06/
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> This is intended to allow updating the set of ID register
> fields we expose for user-only mode, so I have only
> updated the AArch64 ID registers, not AArch32.
> ---
>  target/arm/cpu.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)

> @@ -2299,9 +2317,13 @@ FIELD(ID_AA64ZFR0, F32MM, 52, 4)
>  FIELD(ID_AA64ZFR0, F64MM, 56, 4)

I missed one line (failed to save editor buffer...):

+FIELD(ID_AA64ZFR0, B16B16, 24, 4)

-- PMM


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo
  2023-09-11 13:53 ` [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo Peter Maydell
@ 2023-09-11 14:51   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-11 14:51 UTC (permalink / raw)
  To: Peter Maydell, qemu-arm, qemu-devel

On 11/9/23 15:53, Peter Maydell wrote:
> Some of the names we use for CPU features in linux-user's dummy
> /proc/cpuinfo don't match the strings in the real kernel in
> arch/arm64/kernel/cpuinfo.c. Specifically, the SME related
> features have an underscore in the HWCAP_FOO define name,
> but (like the SVE ones) they do not have an underscore in the
> string in cpuinfo. Correct the errors.
> 
> Fixes: a55b9e7226708 ("linux-user: Emulate /proc/cpuinfo on aarch64 and arm")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   linux-user/elfload.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values
  2023-09-11 13:53 ` [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values Peter Maydell
@ 2023-09-11 14:59   ` Philippe Mathieu-Daudé
  2023-09-11 15:04     ` Peter Maydell
  0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-11 14:59 UTC (permalink / raw)
  To: Peter Maydell, qemu-arm, qemu-devel

On 11/9/23 15:53, Peter Maydell wrote:
> Our lists of Arm 32 and 64 bit hwcap values have lagged behind
> the Linux kernel. Update them to include all the bits defined
> as of upstream Linux git commit a48fa7efaf1161c1 (in the middle
> of the kernel 6.6 dev cycle).
> 
> For 64-bit, we don't yet implement any of the features reported via
> these hwcap bits.  For 32-bit we do in fact already implement them
> all; we'll add the code to set them in a subsequent commit.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   linux-user/elfload.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 44 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Why can't we import asm/hwcap.h with update-linux-headers.sh?


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 7/7] target/arm: Implement FEAT_HBC
  2023-09-11 13:53 ` [PATCH 7/7] target/arm: Implement FEAT_HBC Peter Maydell
@ 2023-09-11 15:01   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-11 15:01 UTC (permalink / raw)
  To: Peter Maydell, qemu-arm, qemu-devel

On 11/9/23 15:53, Peter Maydell wrote:
> FEAT_HBC (Hinted conditional branches) provides a new instruction
> BC.cond, which behaves exactly like the existing B.cond except
> that it provides a hint to the branch predictor about the
> likely behaviour of the branch.
> 
> Since QEMU does not implement branch prediction, we can treat
> this identically to B.cond.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   docs/system/arm/emulation.rst  | 1 +
>   target/arm/cpu.h               | 5 +++++
>   target/arm/tcg/a64.decode      | 3 ++-
>   linux-user/elfload.c           | 1 +
>   target/arm/tcg/cpu64.c         | 4 ++++
>   target/arm/tcg/translate-a64.c | 4 ++++
>   6 files changed, 17 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values
  2023-09-11 14:59   ` Philippe Mathieu-Daudé
@ 2023-09-11 15:04     ` Peter Maydell
  0 siblings, 0 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-11 15:04 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé; +Cc: qemu-arm, qemu-devel

On Mon, 11 Sept 2023 at 15:59, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> On 11/9/23 15:53, Peter Maydell wrote:
> > Our lists of Arm 32 and 64 bit hwcap values have lagged behind
> > the Linux kernel. Update them to include all the bits defined
> > as of upstream Linux git commit a48fa7efaf1161c1 (in the middle
> > of the kernel 6.6 dev cycle).
> >
> > For 64-bit, we don't yet implement any of the features reported via
> > these hwcap bits.  For 32-bit we do in fact already implement them
> > all; we'll add the code to set them in a subsequent commit.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> >   linux-user/elfload.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> >   1 file changed, 44 insertions(+)
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Why can't we import asm/hwcap.h with update-linux-headers.sh?

Probably no inherent reason, but historically linux-user has
always defined its own versions of target architecture
kernel header values and structures.

-- PMM


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC
  2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
                   ` (6 preceding siblings ...)
  2023-09-11 13:53 ` [PATCH 7/7] target/arm: Implement FEAT_HBC Peter Maydell
@ 2023-09-12  0:44 ` Richard Henderson
  7 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2023-09-12  0:44 UTC (permalink / raw)
  To: Peter Maydell, qemu-arm, qemu-devel

On 9/11/23 06:53, Peter Maydell wrote:
> Peter Maydell (6):
>    linux-user/elfload.c: Correct SME feature names reported in cpuinfo
>    linux-user/elfload.c: Add missing arm and arm64 hwcap values
>    linux-user/elfload.c: Report previously missing arm32 hwcaps
>    target/arm: Update AArch64 ID register field definitions
>    target/arm: Update user-mode ID reg mask values
>    target/arm: Implement FEAT_HBC

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 6/7] target/arm: Update user-mode ID reg mask values
  2023-09-11 13:53 ` [PATCH 6/7] target/arm: Update user-mode ID reg mask values Peter Maydell
@ 2023-09-21 15:03   ` Peter Maydell
  0 siblings, 0 replies; 15+ messages in thread
From: Peter Maydell @ 2023-09-21 15:03 UTC (permalink / raw)
  To: qemu-arm, qemu-devel

On Mon, 11 Sept 2023 at 14:53, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> For user-only mode we reveal a subset of the AArch64 ID registers
> to the guest, to emulate the kernel's trap-and-emulate-ID-regs
> handling. Update the feature bit masks to match upstream kernel
> commit a48fa7efaf1161c1c.
>
> None of these features are yet implemented by QEMU, so this
> doesn't yet have a behavioural change, but implementation of
> FEAT_MOPS and FEAT_HBC is imminent.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)

I forgot to update tests/tcg/aarch64/sysregs.c to indicate
that the new fields are permitted to be visible to userspace.
This patch needs the following squashed in:

diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
index d8eb06abcf2..f7a055f1d5f 100644
--- a/tests/tcg/aarch64/sysregs.c
+++ b/tests/tcg/aarch64/sysregs.c
@@ -126,7 +126,7 @@ int main(void)
      */
     get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
     get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
-    get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
+    get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(00ff,0000,00ff,ffff));
     /* TGran4 & TGran64 as pegged to -1 */
     get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
     get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
@@ -138,7 +138,7 @@ int main(void)
     get_cpu_reg_check_mask(id_aa64dfr0_el1,  _m(0000,0000,0000,0006));
     get_cpu_reg_check_zero(id_aa64dfr1_el1);
     get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1,  _m(0ff0,ff0f,00ff,00ff));
-    get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(80f1,00fd,0000,0000));
+    get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(8ff1,fcff,0000,0000));

     get_cpu_reg_check_zero(id_aa64afr0_el1);
     get_cpu_reg_check_zero(id_aa64afr1_el1);

to avoid check-tcg failing when the new features like FEAT_MOPS
or FEAT_HBC are present in 'max'.

-- PMM


^ permalink raw reply related	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2023-09-21 15:05 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
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2023-09-11 13:53 [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Peter Maydell
2023-09-11 13:53 ` [PATCH 1/7] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
2023-09-11 13:53 ` [PATCH 2/7] linux-user/elfload.c: Correct SME feature names reported in cpuinfo Peter Maydell
2023-09-11 14:51   ` Philippe Mathieu-Daudé
2023-09-11 13:53 ` [PATCH 3/7] linux-user/elfload.c: Add missing arm and arm64 hwcap values Peter Maydell
2023-09-11 14:59   ` Philippe Mathieu-Daudé
2023-09-11 15:04     ` Peter Maydell
2023-09-11 13:53 ` [PATCH 4/7] linux-user/elfload.c: Report previously missing arm32 hwcaps Peter Maydell
2023-09-11 13:53 ` [PATCH 5/7] target/arm: Update AArch64 ID register field definitions Peter Maydell
2023-09-11 14:36   ` Peter Maydell
2023-09-11 13:53 ` [PATCH 6/7] target/arm: Update user-mode ID reg mask values Peter Maydell
2023-09-21 15:03   ` Peter Maydell
2023-09-11 13:53 ` [PATCH 7/7] target/arm: Implement FEAT_HBC Peter Maydell
2023-09-11 15:01   ` Philippe Mathieu-Daudé
2023-09-12  0:44 ` [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Richard Henderson

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