Re: [PATCH 6/6] hw/gpio: Add GPIO model for Nuvoton NPCM7xx

[Peter Maydell <peter.maydell@linaro.org>]

On Fri, 9 Oct 2020 at 00:22, Havard Skinnemoen <hskinnemoen@google.com> wrote:
>
> The NPCM7xx chips have multiple GPIO controllers that are mostly
> identical except for some minor differences like the reset values of
> some registers. Each controller controls up to 32 pins.
>
> Each individual pin is modeled as a pair of unnamed GPIOs -- one for
> emitting the actual pin state, and one for driving the pin externally.
> Like the nRF51 GPIO controller, a gpio level may be negative, which
> means the pin is not driven, or floating.
>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> +static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
> +{
> +    ResettableClass *reset = RESETTABLE_CLASS(klass);
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +    QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
> +
> +    dc->desc = "NPCM7xx GPIO Controller";
> +    reset->phases.enter = npcm7xx_gpio_enter_reset;
> +    reset->phases.hold = npcm7xx_gpio_hold_reset;
> +    device_class_set_props(dc, npcm7xx_gpio_properties);
> +}

Missing vmstate struct. Otherwise device looks good.

thanks
-- PMM