* [PULL 00/26] target-arm queue
@ 2020-01-30 16:15 Peter Maydell
2020-01-30 16:15 ` [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES Peter Maydell
` (26 more replies)
0 siblings, 27 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
target-arm queue. The big thing here is the landing of the 3-phase
reset patches...
-- PMM
The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7:
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130
for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f:
target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
* target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
* aspeed: some minor bugfixes
* aspeed: add eMMC controller model for AST2600 SoC
* hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
* New 3-phase reset API for device models
* hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
* Arm KVM: stop/restart the guest counter when the VM is stopped and started
----------------------------------------------------------------
Andrew Jeffery (2):
hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
hw/arm: ast2600: Wire up the eMMC controller
Andrew Jones (6):
target/arm/kvm: trivial: Clean up header documentation
hw/arm/virt: Add missing 5.0 options call to 4.2 options
target/arm/kvm64: kvm64 cpus have timer registers
tests/arm-cpu-features: Check feature default values
target/arm/kvm: Implement virtual time adjustment
target/arm/cpu: Add the kvm-no-adjvtime CPU property
Cédric Le Goater (2):
ftgmac100: check RX and TX buffer alignment
hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0
Damien Hedde (11):
add device_legacy_reset function to prepare for reset api change
hw/core/qdev: add trace events to help with resettable transition
hw/core: create Resettable QOM interface
hw/core: add Resettable support to BusClass and DeviceClass
hw/core/resettable: add support for changing parent
hw/core/qdev: handle parent bus change regarding resettable
hw/core/qdev: update hotplug reset regarding resettable
hw/core: deprecate old reset functions and introduce new ones
docs/devel/reset.rst: add doc about Resettable interface
vl: replace deprecated qbus_reset_all registration
hw/s390x/ipl: replace deprecated qdev_reset_all registration
Joel Stanley (1):
misc/pca9552: Add qom set and get
Peter Maydell (2):
hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
Philippe Mathieu-Daudé (1):
hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
Zenghui Yu (1):
hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
hw/core/Makefile.objs | 1 +
tests/Makefile.include | 1 +
include/hw/arm/aspeed.h | 2 +
include/hw/arm/aspeed_soc.h | 2 +
include/hw/arm/virt.h | 1 +
include/hw/qdev-core.h | 58 +++++++-
include/hw/resettable.h | 247 +++++++++++++++++++++++++++++++++
include/hw/sd/aspeed_sdhci.h | 1 +
target/arm/cpu.h | 7 +
target/arm/kvm_arm.h | 95 ++++++++++---
hw/arm/aspeed.c | 72 ++++++++--
hw/arm/aspeed_ast2600.c | 31 ++++-
hw/arm/aspeed_soc.c | 2 +
hw/arm/raspi.c | 2 -
hw/arm/virt.c | 9 ++
hw/audio/intel-hda.c | 2 +-
hw/core/bus.c | 102 ++++++++++++++
hw/core/or-irq.c | 2 +-
hw/core/qdev.c | 160 ++++++++++++++++++++--
hw/core/resettable.c | 301 +++++++++++++++++++++++++++++++++++++++++
hw/hyperv/hyperv.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/ide/microdrive.c | 8 +-
hw/intc/arm_gicv3_kvm.c | 11 +-
hw/intc/spapr_xive.c | 2 +-
hw/misc/pca9552.c | 90 ++++++++++++
hw/net/ftgmac100.c | 13 ++
hw/ppc/pnv_psi.c | 4 +-
hw/ppc/spapr_pci.c | 2 +-
hw/ppc/spapr_vio.c | 2 +-
hw/s390x/ipl.c | 10 +-
hw/s390x/s390-pci-inst.c | 2 +-
hw/scsi/vmw_pvscsi.c | 2 +-
hw/sd/aspeed_sdhci.c | 11 +-
hw/sd/omap_mmc.c | 2 +-
hw/sd/pl181.c | 2 +-
target/arm/arm-semi.c | 9 ++
target/arm/cpu.c | 2 +
target/arm/cpu64.c | 1 +
target/arm/kvm.c | 120 ++++++++++++++++
target/arm/kvm32.c | 3 +
target/arm/kvm64.c | 4 +
target/arm/machine.c | 7 +
target/arm/monitor.c | 1 +
tests/qtest/arm-cpu-features.c | 41 ++++--
vl.c | 10 +-
docs/arm-cpu-features.rst | 37 ++++-
docs/devel/index.rst | 1 +
docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++
hw/core/trace-events | 27 ++++
51 files changed, 1727 insertions(+), 90 deletions(-)
create mode 100644 include/hw/resettable.h
create mode 100644 hw/core/resettable.c
create mode 100644 docs/devel/reset.rst
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr Peter Maydell
` (25 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
The num-lines property of the TYPE_OR_GATE device sets the number
of input lines it has. An assert() in or_irq_realize() restricts
this to the maximum supported by the implementation. However we
got the condition in the assert wrong: it should be using <=,
because num-lines == MAX_OR_LINES is permitted, and means that
all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array
are used.
We didn't notice this previously because no user has so far
needed that many input lines.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200120142235.10432-1-peter.maydell@linaro.org
---
hw/core/or-irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
index 4bbdbcb321b..d8f3754e967 100644
--- a/hw/core/or-irq.c
+++ b/hw/core/or-irq.c
@@ -58,7 +58,7 @@ static void or_irq_realize(DeviceState *dev, Error **errp)
{
qemu_or_irq *s = OR_IRQ(dev);
- assert(s->num_lines < MAX_OR_LINES);
+ assert(s->num_lines <= MAX_OR_LINES);
qdev_init_gpio_in(dev, or_irq_handler, s->num_lines);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
2020-01-30 16:15 ` [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Peter Maydell
` (24 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
The guest can use the semihosting API to open a handle
corresponding to QEMU's own stdin, stdout, or stderr.
When the guest closes this handle, we should not
close the underlying host stdin/stdout/stderr
the way we would do if the handle corresponded to
a host fd we'd opened on behalf of the guest in SYS_OPEN.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200124172954.28481-1-peter.maydell@linaro.org
---
target/arm/arm-semi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index 788fe61b51a..8718fd01948 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -403,6 +403,15 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf)
{
CPUARMState *env = &cpu->env;
+ /*
+ * Only close the underlying host fd if it's one we opened on behalf
+ * of the guest in SYS_OPEN.
+ */
+ if (gf->hostfd == STDIN_FILENO ||
+ gf->hostfd == STDOUT_FILENO ||
+ gf->hostfd == STDERR_FILENO) {
+ return 0;
+ }
return set_swi_errno(env, close(gf->hostfd));
}
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
2020-01-30 16:15 ` [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES Peter Maydell
2020-01-30 16:15 ` [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller Peter Maydell
` (23 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jeffery <andrew@aj.id.au>
The AST2600 includes a second cut-down version of the SD/MMC controller
found in the AST2500, named the eMMC controller. It's cut down in the
sense that it only supports one slot rather than two, but it brings the
total number of slots supported by the AST2600 to three.
The existing code assumed that the SD controller always provided two
slots. Rework the SDHCI object to expose the number of slots as a
property to be set by the SoC configuration.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-2-clg@kaod.org
[PMM: fixed up to use device_class_set_props()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/sd/aspeed_sdhci.h | 1 +
hw/arm/aspeed.c | 2 +-
hw/arm/aspeed_ast2600.c | 2 ++
hw/arm/aspeed_soc.c | 2 ++
hw/sd/aspeed_sdhci.c | 11 +++++++++--
5 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index dfdab437902..dffbb46946b 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState {
SysBusDevice parent;
SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
+ uint8_t num_slots;
MemoryRegion iomem;
qemu_irq irq;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc06af4fbb3..4174e313cae 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -263,7 +263,7 @@ static void aspeed_machine_init(MachineState *machine)
amc->i2c_init(bmc);
}
- for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) {
+ for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
DriveInfo *dinfo = drive_get_next(IF_SD);
BlockBackend *blk;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 89e4b009504..fb73c4043ea 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -199,6 +199,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
TYPE_ASPEED_SDHCI);
+ object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
+
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 99892cbae67..b5e809a1d3f 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -209,6 +209,8 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
TYPE_ASPEED_SDHCI);
+ object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
+
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index cff3eb7dd21..6a039a1d2f1 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -13,6 +13,7 @@
#include "qapi/error.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
#define ASPEED_SDHCI_INFO 0x00
#define ASPEED_SDHCI_INFO_RESET 0x00030000
@@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
/* Create input irqs for the slots */
qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
- sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);
+ sdhci, NULL, sdhci->num_slots);
sysbus_init_irq(sbd, &sdhci->irq);
memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
sdhci, TYPE_ASPEED_SDHCI, 0x1000);
sysbus_init_mmio(sbd, &sdhci->iomem);
- for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
+ for (int i = 0; i < sdhci->num_slots; ++i) {
Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
@@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = {
},
};
+static Property aspeed_sdhci_properties[] = {
+ DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
{
DeviceClass *dc = DEVICE_CLASS(classp);
@@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
dc->realize = aspeed_sdhci_realize;
dc->reset = aspeed_sdhci_reset;
dc->vmsd = &vmstate_aspeed_sdhci;
+ device_class_set_props(dc, aspeed_sdhci_properties);
}
static TypeInfo aspeed_sdhci_info = {
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2020-01-30 16:15 ` [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 05/26] ftgmac100: check RX and TX buffer alignment Peter Maydell
` (22 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jeffery <andrew@aj.id.au>
Initialise another SDHCI model instance for the AST2600's eMMC
controller and use the SDHCI's num_slots value introduced previously to
determine whether we should create an SD card instance for the new slot.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-3-clg@kaod.org
[ clg : - removed ternary operator from sdhci_attach_drive()
- renamed SDHCI objects with a '-controller' prefix ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/aspeed_soc.h | 2 ++
hw/arm/aspeed.c | 26 +++++++++++++++++---------
hw/arm/aspeed_ast2600.c | 29 ++++++++++++++++++++++++++---
3 files changed, 45 insertions(+), 12 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e84380984f7..90ac7f7ffa3 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -57,6 +57,7 @@ typedef struct AspeedSoCState {
AspeedGPIOState gpio;
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
+ AspeedSDHCIState emmc;
} AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -126,6 +127,7 @@ enum {
ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
+ ASPEED_EMMC,
};
#endif /* ASPEED_SOC_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 4174e313cae..8702256af1b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -171,6 +171,19 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
}
}
+static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
+{
+ DeviceState *card;
+
+ card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
+ TYPE_SD_CARD);
+ if (dinfo) {
+ qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ }
+ object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+}
+
static void aspeed_machine_init(MachineState *machine)
{
AspeedBoardState *bmc;
@@ -264,16 +277,11 @@ static void aspeed_machine_init(MachineState *machine)
}
for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
- SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
- DriveInfo *dinfo = drive_get_next(IF_SD);
- BlockBackend *blk;
- DeviceState *card;
+ sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
+ }
- blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
- card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
- TYPE_SD_CARD);
- qdev_prop_set_drive(card, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+ if (bmc->soc.emmc.num_slots) {
+ sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
}
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index fb73c4043ea..90cf1c755d3 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_ADC] = 0x1E6E9000,
[ASPEED_VIDEO] = 0x1E700000,
[ASPEED_SDHCI] = 0x1E740000,
+ [ASPEED_EMMC] = 0x1E750000,
[ASPEED_GPIO] = 0x1E780000,
[ASPEED_GPIO_1_8V] = 0x1E780800,
[ASPEED_RTC] = 0x1E781000,
@@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
#define ASPEED_SOC_AST2600_MAX_IRQ 128
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_UART1] = 47,
[ASPEED_UART2] = 48,
@@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_ADC] = 78,
[ASPEED_XDMA] = 6,
[ASPEED_SDHCI] = 43,
+ [ASPEED_EMMC] = 15,
[ASPEED_GPIO] = 40,
[ASPEED_GPIO_1_8V] = 11,
[ASPEED_RTC] = 13,
@@ -196,16 +199,26 @@ static void aspeed_soc_ast2600_init(Object *obj)
sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
sizeof(s->gpio_1_8v), typename);
- sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
- TYPE_ASPEED_SDHCI);
+ sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
+ sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
- sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
+ sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
+ OBJECT(&s->sdhci.slots[i]),
sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
}
+
+ sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
+ sizeof(s->emmc), TYPE_ASPEED_SDHCI);
+
+ object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
+
+ sysbus_init_child_obj(obj, "emmc-controller.sdhci",
+ OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
+ TYPE_SYSBUS_SDHCI);
}
/*
@@ -497,6 +510,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_SDHCI));
+
+ /* eMMC */
+ object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
+ aspeed_soc_get_irq(s, ASPEED_EMMC));
}
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 05/26] ftgmac100: check RX and TX buffer alignment
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2020-01-30 16:15 ` [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 Peter Maydell
` (21 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Cédric Le Goater <clg@kaod.org>
These buffers should be aligned on 16 bytes.
Ignore invalid RX and TX buffer addresses and log an error. All
incoming and outgoing traffic will be dropped because no valid RX or
TX descriptors will be available.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-4-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/ftgmac100.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 4ad2594d3a6..2f92b65d4ef 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -198,6 +198,8 @@ typedef struct {
uint32_t des3;
} FTGMAC100Desc;
+#define FTGMAC100_DESC_ALIGNMENT 16
+
/*
* Specific RTL8211E MII Registers
*/
@@ -722,6 +724,12 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
s->itc = value;
break;
case FTGMAC100_RXR_BADR: /* Ring buffer address */
+ if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
+ HWADDR_PRIx "\n", __func__, value);
+ return;
+ }
+
s->rx_ring = value;
s->rx_descriptor = s->rx_ring;
break;
@@ -731,6 +739,11 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
break;
case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
+ if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
+ HWADDR_PRIx "\n", __func__, value);
+ return;
+ }
s->tx_ring = value;
s->tx_descriptor = s->tx_ring;
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2020-01-30 16:15 ` [PULL 05/26] ftgmac100: check RX and TX buffer alignment Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 07/26] misc/pca9552: Add qom set and get Peter Maydell
` (20 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Cédric Le Goater <clg@kaod.org>
The overhead for the OpenBMC firmware images using the a custom U-Boot
is around 2 seconds, which is fine, but with a U-Boot from mainline,
it takes an extra 50 seconds or so to reach Linux. A quick survey on
the number of reads performed on the flash memory region gives the
following figures :
OpenBMC U-Boot 922478 (~ 3.5 MBytes)
Mainline U-Boot 20569977 (~ 80 MBytes)
QEMU must be trashing the TCG TBs and reloading text very often. Some
addresses are read more than 250.000 times. Until we find a solution
to improve boot time, execution from MMIO is not activated by default.
Setting this option also breaks migration compatibility.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200114103433.30534-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/aspeed.h | 2 ++
hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++-----
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 4423cd0cda7..18521484b90 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -19,6 +19,8 @@ typedef struct AspeedBoardState AspeedBoardState;
typedef struct AspeedMachine {
MachineState parent_obj;
+
+ bool mmio_exec;
} AspeedMachine;
#define ASPEED_MACHINE_CLASS(klass) \
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8702256af1b..a17843f0d3b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -261,11 +261,18 @@ static void aspeed_machine_init(MachineState *machine)
* SoC and 128MB for the AST2500 SoC, which is twice as big as
* needed by the flash modules of the Aspeed machines.
*/
- memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
- fl->size, &error_abort);
- memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
- boot_rom);
- write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
+ if (ASPEED_MACHINE(machine)->mmio_exec) {
+ memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
+ &fl->mmio, 0, fl->size);
+ memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
+ boot_rom);
+ } else {
+ memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
+ fl->size, &error_abort);
+ memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
+ boot_rom);
+ write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
+ }
}
aspeed_board_binfo.ram_size = ram_size;
@@ -399,6 +406,30 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
/* Bus 11: TODO ucd90160@64 */
}
+static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
+{
+ return ASPEED_MACHINE(obj)->mmio_exec;
+}
+
+static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
+{
+ ASPEED_MACHINE(obj)->mmio_exec = value;
+}
+
+static void aspeed_machine_instance_init(Object *obj)
+{
+ ASPEED_MACHINE(obj)->mmio_exec = false;
+}
+
+static void aspeed_machine_class_props_init(ObjectClass *oc)
+{
+ object_class_property_add_bool(oc, "execute-in-place",
+ aspeed_get_mmio_exec,
+ aspeed_set_mmio_exec, &error_abort);
+ object_class_property_set_description(oc, "execute-in-place",
+ "boot directly from CE0 flash device", &error_abort);
+}
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -408,6 +439,8 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_parallel = 1;
+
+ aspeed_machine_class_props_init(oc);
}
static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
@@ -550,6 +583,7 @@ static const TypeInfo aspeed_machine_types[] = {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(AspeedMachine),
+ .instance_init = aspeed_machine_instance_init,
.class_size = sizeof(AspeedMachineClass),
.class_init = aspeed_machine_class_init,
.abstract = true,
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 07/26] misc/pca9552: Add qom set and get
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2020-01-30 16:15 ` [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' Peter Maydell
` (19 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Joel Stanley <joel@jms.id.au>
Following the pattern of the work recently done with the ASPEED GPIO
model, this adds support for inspecting and modifying the PCA9552 LEDs
from the monitor.
(qemu) qom-set /machine/unattached/device[17] led0 on
(qemu) qom-set /machine/unattached/device[17] led0 off
(qemu) qom-set /machine/unattached/device[17] led0 pwm0
(qemu) qom-set /machine/unattached/device[17] led0 pwm1
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-6-clg@kaod.org
[clg: - removed the "qom-get" examples from the commit log
- merged memory leak fixes from Joel ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index 73be28d9369..efd961e0414 100644
--- a/hw/misc/pca9552.c
+++ b/hw/misc/pca9552.c
@@ -15,12 +15,16 @@
#include "hw/misc/pca9552.h"
#include "hw/misc/pca9552_regs.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
#define PCA9552_LED_ON 0x0
#define PCA9552_LED_OFF 0x1
#define PCA9552_LED_PWM0 0x2
#define PCA9552_LED_PWM1 0x3
+static const char *led_state[] = {"on", "off", "pwm0", "pwm1"};
+
static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin)
{
uint8_t reg = PCA9552_LS0 + (pin / 4);
@@ -169,6 +173,82 @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event)
return 0;
}
+static void pca9552_get_led(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ PCA9552State *s = PCA9552(obj);
+ int led, rc, reg;
+ uint8_t state;
+
+ rc = sscanf(name, "led%2d", &led);
+ if (rc != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+ if (led < 0 || led > s->nr_leds) {
+ error_setg(errp, "%s invalid led %s", __func__, name);
+ return;
+ }
+ /*
+ * Get the LSx register as the qom interface should expose the device
+ * state, not the modeled 'input line' behaviour which would come from
+ * reading the INPUTx reg
+ */
+ reg = PCA9552_LS0 + led / 4;
+ state = (pca9552_read(s, reg) >> (led % 8)) & 0x3;
+ visit_type_str(v, name, (char **)&led_state[state], errp);
+}
+
+/*
+ * Return an LED selector register value based on an existing one, with
+ * the appropriate 2-bit state value set for the given LED number (0-3).
+ */
+static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state)
+{
+ return (oldval & (~(0x3 << (led_num << 1)))) |
+ ((state & 0x3) << (led_num << 1));
+}
+
+static void pca9552_set_led(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ PCA9552State *s = PCA9552(obj);
+ Error *local_err = NULL;
+ int led, rc, reg, val;
+ uint8_t state;
+ char *state_str;
+
+ visit_type_str(v, name, &state_str, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ rc = sscanf(name, "led%2d", &led);
+ if (rc != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+ if (led < 0 || led > s->nr_leds) {
+ error_setg(errp, "%s invalid led %s", __func__, name);
+ return;
+ }
+
+ for (state = 0; state < ARRAY_SIZE(led_state); state++) {
+ if (!strcmp(state_str, led_state[state])) {
+ break;
+ }
+ }
+ if (state >= ARRAY_SIZE(led_state)) {
+ error_setg(errp, "%s invalid led state %s", __func__, state_str);
+ return;
+ }
+
+ reg = PCA9552_LS0 + led / 4;
+ val = pca9552_read(s, reg);
+ val = pca955x_ledsel(val, led % 4, state);
+ pca9552_write(s, reg, val);
+}
+
static const VMStateDescription pca9552_vmstate = {
.name = "PCA9552",
.version_id = 0,
@@ -204,6 +284,7 @@ static void pca9552_reset(DeviceState *dev)
static void pca9552_initfn(Object *obj)
{
PCA9552State *s = PCA9552(obj);
+ int led;
/* If support for the other PCA955X devices are implemented, these
* constant values might be part of class structure describing the
@@ -211,6 +292,15 @@ static void pca9552_initfn(Object *obj)
*/
s->max_reg = PCA9552_LS3;
s->nr_leds = 16;
+
+ for (led = 0; led < s->nr_leds; led++) {
+ char *name;
+
+ name = g_strdup_printf("led%d", led);
+ object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led,
+ NULL, NULL, NULL);
+ g_free(name);
+ }
}
static void pca9552_class_init(ObjectClass *klass, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2020-01-30 16:15 ` [PULL 07/26] misc/pca9552: Add qom set and get Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 09/26] add device_legacy_reset function to prepare for reset api change Peter Maydell
` (18 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Since we enabled parallel TCG code generation for softmmu (see
commit 3468b59 "tcg: enable multiple TCG contexts in softmmu")
and its subsequent fix (commit 72649619 "add .min_cpus and
.default_cpus fields to machine_class"), the raspi machines are
restricted to always use their 4 cores:
See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4):
222 static void raspi2_machine_init(MachineClass *mc)
223 {
224 mc->desc = "Raspberry Pi 2";
230 mc->max_cpus = BCM283X_NCPUS;
231 mc->min_cpus = BCM283X_NCPUS;
232 mc->default_cpus = BCM283X_NCPUS;
235 };
236 DEFINE_MACHINE("raspi2", raspi2_machine_init)
We can no longer use the -smp option, as we get:
$ qemu-system-arm -M raspi2 -smp 1
qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4
Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp,
remove the unuseful code.
We can achieve the same by using the '-global bcm2836.enabled-cpus=1'
option.
Reported-by: Laurent Bonnans <laurent.bonnans@here.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200120235159.18510-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/raspi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 6a510aafc19..3996f6c63a4 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -192,8 +192,6 @@ static void raspi_init(MachineState *machine, int version)
/* Setup the SOC */
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
&error_abort);
- object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus",
- &error_abort);
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
&error_abort);
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 09/26] add device_legacy_reset function to prepare for reset api change
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2020-01-30 16:15 ` [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition Peter Maydell
` (17 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Provide a temporary device_legacy_reset function doing what
device_reset does to prepare for the transition with Resettable
API.
All occurrence of device_reset in the code tree are also replaced
by device_legacy_reset.
The new resettable API has different prototype and semantics
(resetting child buses as well as the specified device). Subsequent
commits will make the changeover for each call site individually; once
that is complete device_legacy_reset() will be removed.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/qdev-core.h | 4 ++--
hw/audio/intel-hda.c | 2 +-
hw/core/qdev.c | 6 +++---
hw/hyperv/hyperv.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/ide/microdrive.c | 8 ++++----
hw/intc/spapr_xive.c | 2 +-
hw/ppc/pnv_psi.c | 4 ++--
hw/ppc/spapr_pci.c | 2 +-
hw/ppc/spapr_vio.c | 2 +-
hw/s390x/s390-pci-inst.c | 2 +-
hw/scsi/vmw_pvscsi.c | 2 +-
hw/sd/omap_mmc.c | 2 +-
hw/sd/pl181.c | 2 +-
15 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 5da94f872a8..627d653dc16 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -432,11 +432,11 @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev);
void qdev_machine_init(void);
/**
- * @device_reset
+ * device_legacy_reset:
*
* Reset a single device (by calling the reset method).
*/
-void device_reset(DeviceState *dev);
+void device_legacy_reset(DeviceState *dev);
void device_class_set_props(DeviceClass *dc, Property *props);
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index e96a707ac50..1bcc3e5cf80 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -1087,7 +1087,7 @@ static void intel_hda_reset(DeviceState *dev)
QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
DeviceState *qdev = kid->child;
cdev = HDA_CODEC_DEVICE(qdev);
- device_reset(DEVICE(cdev));
+ device_legacy_reset(DEVICE(cdev));
d->state_sts |= (1 << cdev->cad);
}
intel_hda_update_irq(d);
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 05c31df52d7..00230eecb77 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -298,7 +298,7 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
static int qdev_reset_one(DeviceState *dev, void *opaque)
{
- device_reset(dev);
+ device_legacy_reset(dev);
return 0;
}
@@ -867,7 +867,7 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
}
}
if (dev->hotplugged) {
- device_reset(dev);
+ device_legacy_reset(dev);
}
dev->pending_deleted_event = false;
@@ -1101,7 +1101,7 @@ void device_class_set_parent_unrealize(DeviceClass *dc,
dc->unrealize = dev_unrealize;
}
-void device_reset(DeviceState *dev)
+void device_legacy_reset(DeviceState *dev)
{
DeviceClass *klass = DEVICE_GET_CLASS(dev);
diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
index da8ce82725c..8ca3706f5b0 100644
--- a/hw/hyperv/hyperv.c
+++ b/hw/hyperv/hyperv.c
@@ -140,7 +140,7 @@ void hyperv_synic_reset(CPUState *cs)
SynICState *synic = get_synic(cs);
if (synic) {
- device_reset(DEVICE(synic));
+ device_legacy_reset(DEVICE(synic));
}
}
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 827ce29e58f..d23485108d9 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -370,7 +370,7 @@ static void microvm_machine_reset(MachineState *machine)
cpu = X86_CPU(cs);
if (cpu->apic_state) {
- device_reset(cpu->apic_state);
+ device_legacy_reset(cpu->apic_state);
}
}
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a6302a772d1..2ddce4230a8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1879,7 +1879,7 @@ static void pc_machine_reset(MachineState *machine)
cpu = X86_CPU(cs);
if (cpu->apic_state) {
- device_reset(cpu->apic_state);
+ device_legacy_reset(cpu->apic_state);
}
}
}
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
index b0272ea14b3..6b30e36ed83 100644
--- a/hw/ide/microdrive.c
+++ b/hw/ide/microdrive.c
@@ -173,7 +173,7 @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
case 0x00: /* Configuration Option Register */
s->opt = value & 0xcf;
if (value & OPT_SRESET) {
- device_reset(DEVICE(s));
+ device_legacy_reset(DEVICE(s));
}
md_interrupt_update(s);
break;
@@ -316,7 +316,7 @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
case 0xe: /* Device Control */
s->ctrl = value;
if (value & CTRL_SRST) {
- device_reset(DEVICE(s));
+ device_legacy_reset(DEVICE(s));
}
md_interrupt_update(s);
break;
@@ -541,7 +541,7 @@ static int dscm1xxxx_attach(PCMCIACardState *card)
md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
md->io_base = 0x0;
- device_reset(DEVICE(md));
+ device_legacy_reset(DEVICE(md));
md_interrupt_update(md);
return 0;
@@ -551,7 +551,7 @@ static int dscm1xxxx_detach(PCMCIACardState *card)
{
MicroDriveState *md = MICRODRIVE(card);
- device_reset(DEVICE(md));
+ device_legacy_reset(DEVICE(md));
return 0;
}
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 024b8ce2852..20c8155557d 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -1766,7 +1766,7 @@ static target_ulong h_int_reset(PowerPCCPU *cpu,
return H_PARAMETER;
}
- device_reset(DEVICE(xive));
+ device_legacy_reset(DEVICE(xive));
if (kvm_irqchip_in_kernel()) {
Error *local_err = NULL;
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 6baf9503a1c..c34a49b000f 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -466,7 +466,7 @@ static void pnv_psi_reset(DeviceState *dev)
static void pnv_psi_reset_handler(void *dev)
{
- device_reset(DEVICE(dev));
+ device_legacy_reset(DEVICE(dev));
}
static void pnv_psi_realize(DeviceState *dev, Error **errp)
@@ -715,7 +715,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
break;
case PSIHB9_INTERRUPT_CONTROL:
if (val & PSIHB9_IRQ_RESET) {
- device_reset(DEVICE(&psi9->source));
+ device_legacy_reset(DEVICE(&psi9->source));
}
psi->regs[reg] = val;
break;
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index e82bfc5ca7c..709a52780dd 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -2014,7 +2014,7 @@ static int spapr_phb_children_reset(Object *child, void *opaque)
DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
if (dev) {
- device_reset(dev);
+ device_legacy_reset(dev);
}
return 0;
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 554de9930dc..f14944e9007 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -304,7 +304,7 @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq)
static void spapr_vio_quiesce_one(SpaprVioDevice *dev)
{
if (dev->tcet) {
- device_reset(DEVICE(dev->tcet));
+ device_legacy_reset(DEVICE(dev->tcet));
}
free_crq(dev);
}
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 92c7e45df5f..2f7a7d7bd1b 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -243,7 +243,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
goto out;
}
- device_reset(DEVICE(pbdev));
+ device_legacy_reset(DEVICE(pbdev));
pbdev->fh &= ~FH_MASK_ENABLE;
pbdev->state = ZPCI_FS_DISABLED;
stl_p(&ressetpci->fh, pbdev->fh);
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 8f1aaf9c874..e4ee2e66435 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -838,7 +838,7 @@ pvscsi_on_cmd_reset_device(PVSCSIState *s)
if (sdev != NULL) {
s->resetting++;
- device_reset(&sdev->qdev);
+ device_legacy_reset(&sdev->qdev);
s->resetting--;
return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
}
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index c6e516b6113..4088a8a80bc 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -318,7 +318,7 @@ void omap_mmc_reset(struct omap_mmc_s *host)
* into any bus, and we must reset it manually. When omap_mmc is
* QOMified this must move into the QOM reset function.
*/
- device_reset(DEVICE(host->card));
+ device_legacy_reset(DEVICE(host->card));
}
static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 8033fe455d8..2b3776a6a0f 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -482,7 +482,7 @@ static void pl181_reset(DeviceState *d)
/* Since we're still using the legacy SD API the card is not plugged
* into any bus, and we must reset it manually.
*/
- device_reset(DEVICE(s->card));
+ device_legacy_reset(DEVICE(s->card));
}
static void pl181_init(Object *obj)
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2020-01-30 16:15 ` [PULL 09/26] add device_legacy_reset function to prepare for reset api change Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 11/26] hw/core: create Resettable QOM interface Peter Maydell
` (16 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Adds trace events to reset procedure and when updating the parent
bus of a device.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/core/qdev.c | 29 ++++++++++++++++++++++++++---
hw/core/trace-events | 9 +++++++++
2 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 00230eecb77..29e8c6b8dfc 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -38,6 +38,7 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "trace.h"
bool qdev_hotplug = false;
static bool qdev_hot_added = false;
@@ -98,7 +99,11 @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
bool replugging = dev->parent_bus != NULL;
if (replugging) {
- /* Keep a reference to the device while it's not plugged into
+ trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
+ dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
+ OBJECT(bus), object_get_typename(OBJECT(bus)));
+ /*
+ * Keep a reference to the device while it's not plugged into
* any bus, to avoid it potentially evaporating when it is
* dereffed in bus_remove_child().
*/
@@ -296,6 +301,18 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
return hotplug_ctrl;
}
+static int qdev_prereset(DeviceState *dev, void *opaque)
+{
+ trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev)));
+ return 0;
+}
+
+static int qbus_prereset(BusState *bus, void *opaque)
+{
+ trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus)));
+ return 0;
+}
+
static int qdev_reset_one(DeviceState *dev, void *opaque)
{
device_legacy_reset(dev);
@@ -306,6 +323,7 @@ static int qdev_reset_one(DeviceState *dev, void *opaque)
static int qbus_reset_one(BusState *bus, void *opaque)
{
BusClass *bc = BUS_GET_CLASS(bus);
+ trace_qbus_reset(bus, object_get_typename(OBJECT(bus)));
if (bc->reset) {
bc->reset(bus);
}
@@ -314,7 +332,9 @@ static int qbus_reset_one(BusState *bus, void *opaque)
void qdev_reset_all(DeviceState *dev)
{
- qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
+ trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev)));
+ qdev_walk_children(dev, qdev_prereset, qbus_prereset,
+ qdev_reset_one, qbus_reset_one, NULL);
}
void qdev_reset_all_fn(void *opaque)
@@ -324,7 +344,9 @@ void qdev_reset_all_fn(void *opaque)
void qbus_reset_all(BusState *bus)
{
- qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
+ trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus)));
+ qbus_walk_children(bus, qdev_prereset, qbus_prereset,
+ qdev_reset_one, qbus_reset_one, NULL);
}
void qbus_reset_all_fn(void *opaque)
@@ -1105,6 +1127,7 @@ void device_legacy_reset(DeviceState *dev)
{
DeviceClass *klass = DEVICE_GET_CLASS(dev);
+ trace_qdev_reset(dev, object_get_typename(OBJECT(dev)));
if (klass->reset) {
klass->reset(dev);
}
diff --git a/hw/core/trace-events b/hw/core/trace-events
index fe47a9c8cb1..a375aa88a48 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -1,2 +1,11 @@
# loader.c
loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d"
+
+# qdev.c
+qdev_reset(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 11/26] hw/core: create Resettable QOM interface
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2020-01-30 16:15 ` [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass Peter Maydell
` (15 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
This commit defines an interface allowing multi-phase reset. This aims
to solve a problem of the actual single-phase reset (built in
DeviceClass and BusClass): reset behavior is dependent on the order
in which reset handlers are called. In particular doing external
side-effect (like setting an qemu_irq) is problematic because receiving
object may not be reset yet.
The Resettable interface divides the reset in 3 well defined phases.
To reset an object tree, all 1st phases are executed then all 2nd then
all 3rd. See the comments in include/hw/resettable.h for a more complete
description. The interface defines 3 phases to let the future
possibility of holding an object into reset for some time.
The qdev/qbus reset in DeviceClass and BusClass will be modified in
following commits to use this interface. A mechanism is provided
to allow executing a transitional reset handler in place of the 2nd
phase which is executed in children-then-parent order inside a tree.
This will allow to transition devices and buses smoothly while
keeping the exact current qdev/qbus reset behavior for now.
Documentation will be added in a following commit.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/core/Makefile.objs | 1 +
include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++
hw/core/resettable.c | 238 ++++++++++++++++++++++++++++++++++++++++
hw/core/trace-events | 17 +++
4 files changed, 467 insertions(+)
create mode 100644 include/hw/resettable.h
create mode 100644 hw/core/resettable.c
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index a522b7297d3..9e41ec9a15d 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -2,6 +2,7 @@
common-obj-y += qdev.o qdev-properties.o
common-obj-y += bus.o
common-obj-y += cpu.o
+common-obj-y += resettable.o
common-obj-y += hotplug.o
common-obj-y += vmstate-if.o
# irq.o needed for qdev GPIO handling:
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
new file mode 100644
index 00000000000..c0b9fc6ad62
--- /dev/null
+++ b/include/hw/resettable.h
@@ -0,0 +1,211 @@
+/*
+ * Resettable interface header.
+ *
+ * Copyright (c) 2019 GreenSocs SAS
+ *
+ * Authors:
+ * Damien Hedde
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef HW_RESETTABLE_H
+#define HW_RESETTABLE_H
+
+#include "qom/object.h"
+
+#define TYPE_RESETTABLE_INTERFACE "resettable"
+
+#define RESETTABLE_CLASS(class) \
+ OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE)
+
+#define RESETTABLE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE)
+
+typedef struct ResettableState ResettableState;
+
+/**
+ * ResetType:
+ * Types of reset.
+ *
+ * + Cold: reset resulting from a power cycle of the object.
+ *
+ * TODO: Support has to be added to handle more types. In particular,
+ * ResettableState structure needs to be expanded.
+ */
+typedef enum ResetType {
+ RESET_TYPE_COLD,
+} ResetType;
+
+/*
+ * ResettableClass:
+ * Interface for resettable objects.
+ *
+ * See docs/devel/reset.rst for more detailed information about how QEMU models
+ * reset. This whole API must only be used when holding the iothread mutex.
+ *
+ * All objects which can be reset must implement this interface;
+ * it is usually provided by a base class such as DeviceClass or BusClass.
+ * Every Resettable object must maintain some state tracking the
+ * progress of a reset operation by providing a ResettableState structure.
+ * The functions defined in this module take care of updating the
+ * state of the reset.
+ * The base class implementation of the interface provides this
+ * state and implements the associated method: get_state.
+ *
+ * Concrete object implementations (typically specific devices
+ * such as a UART model) should provide the functions
+ * for the phases.enter, phases.hold and phases.exit methods, which
+ * they can set in their class init function, either directly or
+ * by calling resettable_class_set_parent_phases().
+ * The phase methods are guaranteed to only only ever be called once
+ * for any reset event, in the order 'enter', 'hold', 'exit'.
+ * An object will always move quickly from 'enter' to 'hold'
+ * but might remain in 'hold' for an arbitrary period of time
+ * before eventually reset is deasserted and the 'exit' phase is called.
+ * Object implementations should be prepared for functions handling
+ * inbound connections from other devices (such as qemu_irq handler
+ * functions) to be called at any point during reset after their
+ * 'enter' method has been called.
+ *
+ * Users of a resettable object should not call these methods
+ * directly, but instead use the function resettable_reset().
+ *
+ * @phases.enter: This phase is called when the object enters reset. It
+ * should reset local state of the object, but it must not do anything that
+ * has a side-effect on other objects, such as raising or lowering a qemu_irq
+ * line or reading or writing guest memory. It takes the reset's type as
+ * argument.
+ *
+ * @phases.hold: This phase is called for entry into reset, once every object
+ * in the system which is being reset has had its @phases.enter method called.
+ * At this point devices can do actions that affect other objects.
+ *
+ * @phases.exit: This phase is called when the object leaves the reset state.
+ * Actions affecting other objects are permitted.
+ *
+ * @get_state: Mandatory method which must return a pointer to a
+ * ResettableState.
+ *
+ * @get_transitional_function: transitional method to handle Resettable objects
+ * not yet fully moved to this interface. It will be removed as soon as it is
+ * not needed anymore. This method is optional and may return a pointer to a
+ * function to be used instead of the phases. If the method exists and returns
+ * a non-NULL function pointer then that function is executed as a replacement
+ * of the 'hold' phase method taking the object as argument. The two other phase
+ * methods are not executed.
+ *
+ * @child_foreach: Executes a given callback on every Resettable child. Child
+ * in this context means a child in the qbus tree, so the children of a qbus
+ * are the devices on it, and the children of a device are all the buses it
+ * owns. This is not the same as the QOM object hierarchy. The function takes
+ * additional opaque and ResetType arguments which must be passed unmodified to
+ * the callback.
+ */
+typedef void (*ResettableEnterPhase)(Object *obj, ResetType type);
+typedef void (*ResettableHoldPhase)(Object *obj);
+typedef void (*ResettableExitPhase)(Object *obj);
+typedef ResettableState * (*ResettableGetState)(Object *obj);
+typedef void (*ResettableTrFunction)(Object *obj);
+typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj);
+typedef void (*ResettableChildCallback)(Object *, void *opaque,
+ ResetType type);
+typedef void (*ResettableChildForeach)(Object *obj,
+ ResettableChildCallback cb,
+ void *opaque, ResetType type);
+typedef struct ResettablePhases {
+ ResettableEnterPhase enter;
+ ResettableHoldPhase hold;
+ ResettableExitPhase exit;
+} ResettablePhases;
+typedef struct ResettableClass {
+ InterfaceClass parent_class;
+
+ /* Phase methods */
+ ResettablePhases phases;
+
+ /* State access method */
+ ResettableGetState get_state;
+
+ /* Transitional method for legacy reset compatibility */
+ ResettableGetTrFunction get_transitional_function;
+
+ /* Hierarchy handling method */
+ ResettableChildForeach child_foreach;
+} ResettableClass;
+
+/**
+ * ResettableState:
+ * Structure holding reset related state. The fields should not be accessed
+ * directly; the definition is here to allow further inclusion into other
+ * objects.
+ *
+ * @count: Number of reset level the object is into. It is incremented when
+ * the reset operation starts and decremented when it finishes.
+ * @hold_phase_pending: flag which indicates that we need to invoke the 'hold'
+ * phase handler for this object.
+ * @exit_phase_in_progress: true if we are currently in the exit phase
+ */
+struct ResettableState {
+ unsigned count;
+ bool hold_phase_pending;
+ bool exit_phase_in_progress;
+};
+
+/**
+ * resettable_reset:
+ * Trigger a reset on an object @obj of type @type. @obj must implement
+ * Resettable interface.
+ *
+ * Calling this function is equivalent to calling @resettable_assert_reset()
+ * then @resettable_release_reset().
+ */
+void resettable_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_assert_reset:
+ * Put an object @obj into reset. @obj must implement Resettable interface.
+ *
+ * @resettable_release_reset() must eventually be called after this call.
+ * There must be one call to @resettable_release_reset() per call of
+ * @resettable_assert_reset(), with the same type argument.
+ *
+ * NOTE: Until support for migration is added, the @resettable_release_reset()
+ * must not be delayed. It must occur just after @resettable_assert_reset() so
+ * that migration cannot be triggered in between. Prefer using
+ * @resettable_reset() for now.
+ */
+void resettable_assert_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_release_reset:
+ * Release the object @obj from reset. @obj must implement Resettable interface.
+ *
+ * See @resettable_assert_reset() description for details.
+ */
+void resettable_release_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_is_in_reset:
+ * Return true if @obj is under reset.
+ *
+ * @obj must implement Resettable interface.
+ */
+bool resettable_is_in_reset(Object *obj);
+
+/**
+ * resettable_class_set_parent_phases:
+ *
+ * Save @rc current reset phases into @parent_phases and override @rc phases
+ * by the given new methods (@enter, @hold and @exit).
+ * Each phase is overridden only if the new one is not NULL allowing to
+ * override a subset of phases.
+ */
+void resettable_class_set_parent_phases(ResettableClass *rc,
+ ResettableEnterPhase enter,
+ ResettableHoldPhase hold,
+ ResettableExitPhase exit,
+ ResettablePhases *parent_phases);
+
+#endif
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
new file mode 100644
index 00000000000..91332084870
--- /dev/null
+++ b/hw/core/resettable.c
@@ -0,0 +1,238 @@
+/*
+ * Resettable interface.
+ *
+ * Copyright (c) 2019 GreenSocs SAS
+ *
+ * Authors:
+ * Damien Hedde
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "hw/resettable.h"
+#include "trace.h"
+
+/**
+ * resettable_phase_enter/hold/exit:
+ * Function executing a phase recursively in a resettable object and its
+ * children.
+ */
+static void resettable_phase_enter(Object *obj, void *opaque, ResetType type);
+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type);
+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
+
+/**
+ * enter_phase_in_progress:
+ * True if we are currently in reset enter phase.
+ *
+ * Note: This flag is only used to guarantee (using asserts) that the reset
+ * API is used correctly. We can use a global variable because we rely on the
+ * iothread mutex to ensure only one reset operation is in a progress at a
+ * given time.
+ */
+static bool enter_phase_in_progress;
+
+void resettable_reset(Object *obj, ResetType type)
+{
+ trace_resettable_reset(obj, type);
+ resettable_assert_reset(obj, type);
+ resettable_release_reset(obj, type);
+}
+
+void resettable_assert_reset(Object *obj, ResetType type)
+{
+ /* TODO: change this assert when adding support for other reset types */
+ assert(type == RESET_TYPE_COLD);
+ trace_resettable_reset_assert_begin(obj, type);
+ assert(!enter_phase_in_progress);
+
+ enter_phase_in_progress = true;
+ resettable_phase_enter(obj, NULL, type);
+ enter_phase_in_progress = false;
+
+ resettable_phase_hold(obj, NULL, type);
+
+ trace_resettable_reset_assert_end(obj);
+}
+
+void resettable_release_reset(Object *obj, ResetType type)
+{
+ /* TODO: change this assert when adding support for other reset types */
+ assert(type == RESET_TYPE_COLD);
+ trace_resettable_reset_release_begin(obj, type);
+ assert(!enter_phase_in_progress);
+
+ resettable_phase_exit(obj, NULL, type);
+
+ trace_resettable_reset_release_end(obj);
+}
+
+bool resettable_is_in_reset(Object *obj)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ ResettableState *s = rc->get_state(obj);
+
+ return s->count > 0;
+}
+
+/**
+ * resettable_child_foreach:
+ * helper to avoid checking the existence of the method.
+ */
+static void resettable_child_foreach(ResettableClass *rc, Object *obj,
+ ResettableChildCallback cb,
+ void *opaque, ResetType type)
+{
+ if (rc->child_foreach) {
+ rc->child_foreach(obj, cb, opaque, type);
+ }
+}
+
+/**
+ * resettable_get_tr_func:
+ * helper to fetch transitional reset callback if any.
+ */
+static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc,
+ Object *obj)
+{
+ ResettableTrFunction tr_func = NULL;
+ if (rc->get_transitional_function) {
+ tr_func = rc->get_transitional_function(obj);
+ }
+ return tr_func;
+}
+
+static void resettable_phase_enter(Object *obj, void *opaque, ResetType type)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ ResettableState *s = rc->get_state(obj);
+ const char *obj_typename = object_get_typename(obj);
+ bool action_needed = false;
+
+ /* exit phase has to finish properly before entering back in reset */
+ assert(!s->exit_phase_in_progress);
+
+ trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type);
+
+ /* Only take action if we really enter reset for the 1st time. */
+ /*
+ * TODO: if adding more ResetType support, some additional checks
+ * are probably needed here.
+ */
+ if (s->count++ == 0) {
+ action_needed = true;
+ }
+ /*
+ * We limit the count to an arbitrary "big" value. The value is big
+ * enough not to be triggered normally.
+ * The assert will stop an infinite loop if there is a cycle in the
+ * reset tree. The loop goes through resettable_foreach_child below
+ * which at some point will call us again.
+ */
+ assert(s->count <= 50);
+
+ /*
+ * handle the children even if action_needed is at false so that
+ * child counts are incremented too
+ */
+ resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type);
+
+ /* execute enter phase for the object if needed */
+ if (action_needed) {
+ trace_resettable_phase_enter_exec(obj, obj_typename, type,
+ !!rc->phases.enter);
+ if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) {
+ rc->phases.enter(obj, type);
+ }
+ s->hold_phase_pending = true;
+ }
+ trace_resettable_phase_enter_end(obj, obj_typename, s->count);
+}
+
+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ ResettableState *s = rc->get_state(obj);
+ const char *obj_typename = object_get_typename(obj);
+
+ /* exit phase has to finish properly before entering back in reset */
+ assert(!s->exit_phase_in_progress);
+
+ trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type);
+
+ /* handle children first */
+ resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type);
+
+ /* exec hold phase */
+ if (s->hold_phase_pending) {
+ s->hold_phase_pending = false;
+ ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj);
+ trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold);
+ if (tr_func) {
+ trace_resettable_transitional_function(obj, obj_typename);
+ tr_func(obj);
+ } else if (rc->phases.hold) {
+ rc->phases.hold(obj);
+ }
+ }
+ trace_resettable_phase_hold_end(obj, obj_typename, s->count);
+}
+
+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ ResettableState *s = rc->get_state(obj);
+ const char *obj_typename = object_get_typename(obj);
+
+ assert(!s->exit_phase_in_progress);
+ trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type);
+
+ /* exit_phase_in_progress ensures this phase is 'atomic' */
+ s->exit_phase_in_progress = true;
+ resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type);
+
+ assert(s->count > 0);
+ if (s->count == 1) {
+ trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
+ if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
+ rc->phases.exit(obj);
+ }
+ s->count = 0;
+ }
+ s->exit_phase_in_progress = false;
+ trace_resettable_phase_exit_end(obj, obj_typename, s->count);
+}
+
+void resettable_class_set_parent_phases(ResettableClass *rc,
+ ResettableEnterPhase enter,
+ ResettableHoldPhase hold,
+ ResettableExitPhase exit,
+ ResettablePhases *parent_phases)
+{
+ *parent_phases = rc->phases;
+ if (enter) {
+ rc->phases.enter = enter;
+ }
+ if (hold) {
+ rc->phases.hold = hold;
+ }
+ if (exit) {
+ rc->phases.exit = exit;
+ }
+}
+
+static const TypeInfo resettable_interface_info = {
+ .name = TYPE_RESETTABLE_INTERFACE,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(ResettableClass),
+};
+
+static void reset_register_types(void)
+{
+ type_register_static(&resettable_interface_info);
+}
+
+type_init(reset_register_types)
diff --git a/hw/core/trace-events b/hw/core/trace-events
index a375aa88a48..77d61cb66e6 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -9,3 +9,20 @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
+
+# resettable.c
+resettable_reset(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_assert_end(void *obj) "obj=%p"
+resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_release_end(void *obj) "obj=%p"
+resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
+resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
+resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
+resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2020-01-30 16:15 ` [PULL 11/26] hw/core: create Resettable QOM interface Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 13/26] hw/core/resettable: add support for changing parent Peter Maydell
` (14 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
This commit adds support of Resettable interface to buses and devices:
+ ResettableState structure is added in the Bus/Device state
+ Resettable methods are implemented.
+ device/bus_is_in_reset function defined
This commit allows to transition the objects to the new
multi-phase interface without changing the reset behavior at all.
Object single reset method can be split into the 3 different phases
but the 3 phases are still executed in a row for a given object.
From the qdev/qbus reset api point of view, nothing is changed.
qdev_reset_all() and qbus_reset_all() are not modified as well as
device_legacy_reset().
Transition of an object must be done from parent class to child class.
Care has been taken to allow the transition of a parent class
without requiring the child classes to be transitioned at the same
time. Note that SysBus and SysBusDevice class do not need any transition
because they do not override the legacy reset method.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/Makefile.include | 1 +
include/hw/qdev-core.h | 27 ++++++++++++
hw/core/bus.c | 97 ++++++++++++++++++++++++++++++++++++++++++
hw/core/qdev.c | 93 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 218 insertions(+)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index c6827ce8c29..a1bff5dcce0 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -429,6 +429,7 @@ tests/fp/%:
tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
hw/core/bus.o \
+ hw/core/resettable.o \
hw/core/irq.o \
hw/core/fw-path-provider.o \
hw/core/reset.o \
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 627d653dc16..09b7a441eb6 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -5,6 +5,7 @@
#include "qemu/bitmap.h"
#include "qom/object.h"
#include "hw/hotplug.h"
+#include "hw/resettable.h"
enum {
DEV_NVECTORS_UNSPECIFIED = -1,
@@ -122,6 +123,11 @@ typedef struct DeviceClass {
bool hotpluggable;
/* callbacks */
+ /*
+ * Reset method here is deprecated and replaced by methods in the
+ * resettable class interface to implement a multi-phase reset.
+ * TODO: remove once every reset callback is unused
+ */
DeviceReset reset;
DeviceRealize realize;
DeviceUnrealize unrealize;
@@ -146,6 +152,7 @@ struct NamedGPIOList {
/**
* DeviceState:
* @realized: Indicates whether the device has been fully constructed.
+ * @reset: ResettableState for the device; handled by Resettable interface.
*
* This structure should not be accessed directly. We declare it here
* so that it can be embedded in individual device state structures.
@@ -168,6 +175,7 @@ struct DeviceState {
int num_child_bus;
int instance_id_alias;
int alias_required_for_version;
+ ResettableState reset;
};
struct DeviceListener {
@@ -220,6 +228,7 @@ typedef struct BusChild {
/**
* BusState:
* @hotplug_handler: link to a hotplug handler associated with bus.
+ * @reset: ResettableState for the bus; handled by Resettable interface.
*/
struct BusState {
Object obj;
@@ -231,6 +240,7 @@ struct BusState {
int num_children;
QTAILQ_HEAD(, BusChild) children;
QLIST_ENTRY(BusState) sibling;
+ ResettableState reset;
};
/**
@@ -417,6 +427,18 @@ void qdev_reset_all_fn(void *opaque);
void qbus_reset_all(BusState *bus);
void qbus_reset_all_fn(void *opaque);
+/**
+ * device_is_in_reset:
+ * Return true if the device @dev is currently being reset.
+ */
+bool device_is_in_reset(DeviceState *dev);
+
+/**
+ * bus_is_in_reset:
+ * Return true if the bus @bus is currently being reset.
+ */
+bool bus_is_in_reset(BusState *bus);
+
/* This should go away once we get rid of the NULL bus hack */
BusState *sysbus_get_default(void);
@@ -440,6 +462,11 @@ void device_legacy_reset(DeviceState *dev);
void device_class_set_props(DeviceClass *dc, Property *props);
+/**
+ * device_class_set_parent_reset:
+ * TODO: remove the function when DeviceClass's reset method
+ * is not used anymore.
+ */
void device_class_set_parent_reset(DeviceClass *dc,
DeviceReset dev_reset,
DeviceReset *parent_reset);
diff --git a/hw/core/bus.c b/hw/core/bus.c
index 7f3d2a3dbda..2698f715bd7 100644
--- a/hw/core/bus.c
+++ b/hw/core/bus.c
@@ -68,6 +68,28 @@ int qbus_walk_children(BusState *bus,
return 0;
}
+bool bus_is_in_reset(BusState *bus)
+{
+ return resettable_is_in_reset(OBJECT(bus));
+}
+
+static ResettableState *bus_get_reset_state(Object *obj)
+{
+ BusState *bus = BUS(obj);
+ return &bus->reset;
+}
+
+static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
+ void *opaque, ResetType type)
+{
+ BusState *bus = BUS(obj);
+ BusChild *kid;
+
+ QTAILQ_FOREACH(kid, &bus->children, sibling) {
+ cb(OBJECT(kid->child), opaque, type);
+ }
+}
+
static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
{
const char *typename = object_get_typename(OBJECT(bus));
@@ -199,12 +221,83 @@ static char *default_bus_get_fw_dev_path(DeviceState *dev)
return g_strdup(object_get_typename(OBJECT(dev)));
}
+/**
+ * bus_phases_reset:
+ * Transition reset method for buses to allow moving
+ * smoothly from legacy reset method to multi-phases
+ */
+static void bus_phases_reset(BusState *bus)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(bus);
+
+ if (rc->phases.enter) {
+ rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD);
+ }
+ if (rc->phases.hold) {
+ rc->phases.hold(OBJECT(bus));
+ }
+ if (rc->phases.exit) {
+ rc->phases.exit(OBJECT(bus));
+ }
+}
+
+static void bus_transitional_reset(Object *obj)
+{
+ BusClass *bc = BUS_GET_CLASS(obj);
+
+ /*
+ * This will call either @bus_phases_reset (for multi-phases transitioned
+ * buses) or a bus's specific method for not-yet transitioned buses.
+ * In both case, it does not reset children.
+ */
+ if (bc->reset) {
+ bc->reset(BUS(obj));
+ }
+}
+
+/**
+ * bus_get_transitional_reset:
+ * check if the bus's class is ready for multi-phase
+ */
+static ResettableTrFunction bus_get_transitional_reset(Object *obj)
+{
+ BusClass *dc = BUS_GET_CLASS(obj);
+ if (dc->reset != bus_phases_reset) {
+ /*
+ * dc->reset has been overridden by a subclass,
+ * the bus is not ready for multi phase yet.
+ */
+ return bus_transitional_reset;
+ }
+ return NULL;
+}
+
static void bus_class_init(ObjectClass *class, void *data)
{
BusClass *bc = BUS_CLASS(class);
+ ResettableClass *rc = RESETTABLE_CLASS(class);
class->unparent = bus_unparent;
bc->get_fw_dev_path = default_bus_get_fw_dev_path;
+
+ rc->get_state = bus_get_reset_state;
+ rc->child_foreach = bus_reset_child_foreach;
+
+ /*
+ * @bus_phases_reset is put as the default reset method below, allowing
+ * to do the multi-phase transition from base classes to leaf classes. It
+ * allows a legacy-reset Bus class to extend a multi-phases-reset
+ * Bus class for the following reason:
+ * + If a base class B has been moved to multi-phase, then it does not
+ * override this default reset method and may have defined phase methods.
+ * + A child class C (extending class B) which uses
+ * bus_class_set_parent_reset() (or similar means) to override the
+ * reset method will still work as expected. @bus_phases_reset function
+ * will be registered as the parent reset method and effectively call
+ * parent reset phases.
+ */
+ bc->reset = bus_phases_reset;
+ rc->get_transitional_function = bus_get_transitional_reset;
}
static void qbus_finalize(Object *obj)
@@ -223,6 +316,10 @@ static const TypeInfo bus_info = {
.instance_init = qbus_initfn,
.instance_finalize = qbus_finalize,
.class_init = bus_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_RESETTABLE_INTERFACE },
+ { }
+ },
};
static void bus_register_types(void)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 29e8c6b8dfc..b2affd8f92b 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -355,6 +355,28 @@ void qbus_reset_all_fn(void *opaque)
qbus_reset_all(bus);
}
+bool device_is_in_reset(DeviceState *dev)
+{
+ return resettable_is_in_reset(OBJECT(dev));
+}
+
+static ResettableState *device_get_reset_state(Object *obj)
+{
+ DeviceState *dev = DEVICE(obj);
+ return &dev->reset;
+}
+
+static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb,
+ void *opaque, ResetType type)
+{
+ DeviceState *dev = DEVICE(obj);
+ BusState *bus;
+
+ QLIST_FOREACH(bus, &dev->child_bus, sibling) {
+ cb(OBJECT(bus), opaque, type);
+ }
+}
+
/* can be used as ->unplug() callback for the simple cases */
void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
@@ -1057,10 +1079,62 @@ device_vmstate_if_get_id(VMStateIf *obj)
return qdev_get_dev_path(dev);
}
+/**
+ * device_phases_reset:
+ * Transition reset method for devices to allow moving
+ * smoothly from legacy reset method to multi-phases
+ */
+static void device_phases_reset(DeviceState *dev)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(dev);
+
+ if (rc->phases.enter) {
+ rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
+ }
+ if (rc->phases.hold) {
+ rc->phases.hold(OBJECT(dev));
+ }
+ if (rc->phases.exit) {
+ rc->phases.exit(OBJECT(dev));
+ }
+}
+
+static void device_transitional_reset(Object *obj)
+{
+ DeviceClass *dc = DEVICE_GET_CLASS(obj);
+
+ /*
+ * This will call either @device_phases_reset (for multi-phases transitioned
+ * devices) or a device's specific method for not-yet transitioned devices.
+ * In both case, it does not reset children.
+ */
+ if (dc->reset) {
+ dc->reset(DEVICE(obj));
+ }
+}
+
+/**
+ * device_get_transitional_reset:
+ * check if the device's class is ready for multi-phase
+ */
+static ResettableTrFunction device_get_transitional_reset(Object *obj)
+{
+ DeviceClass *dc = DEVICE_GET_CLASS(obj);
+ if (dc->reset != device_phases_reset) {
+ /*
+ * dc->reset has been overridden by a subclass,
+ * the device is not ready for multi phase yet.
+ */
+ return device_transitional_reset;
+ }
+ return NULL;
+}
+
static void device_class_init(ObjectClass *class, void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
VMStateIfClass *vc = VMSTATE_IF_CLASS(class);
+ ResettableClass *rc = RESETTABLE_CLASS(class);
class->unparent = device_unparent;
@@ -1073,6 +1147,24 @@ static void device_class_init(ObjectClass *class, void *data)
dc->hotpluggable = true;
dc->user_creatable = true;
vc->get_id = device_vmstate_if_get_id;
+ rc->get_state = device_get_reset_state;
+ rc->child_foreach = device_reset_child_foreach;
+
+ /*
+ * @device_phases_reset is put as the default reset method below, allowing
+ * to do the multi-phase transition from base classes to leaf classes. It
+ * allows a legacy-reset Device class to extend a multi-phases-reset
+ * Device class for the following reason:
+ * + If a base class B has been moved to multi-phase, then it does not
+ * override this default reset method and may have defined phase methods.
+ * + A child class C (extending class B) which uses
+ * device_class_set_parent_reset() (or similar means) to override the
+ * reset method will still work as expected. @device_phases_reset function
+ * will be registered as the parent reset method and effectively call
+ * parent reset phases.
+ */
+ dc->reset = device_phases_reset;
+ rc->get_transitional_function = device_get_transitional_reset;
object_class_property_add_bool(class, "realized",
device_get_realized, device_set_realized,
@@ -1157,6 +1249,7 @@ static const TypeInfo device_type_info = {
.class_size = sizeof(DeviceClass),
.interfaces = (InterfaceInfo[]) {
{ TYPE_VMSTATE_IF },
+ { TYPE_RESETTABLE_INTERFACE },
{ }
}
};
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 13/26] hw/core/resettable: add support for changing parent
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2020-01-30 16:15 ` [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable Peter Maydell
` (13 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Add a function resettable_change_parent() to do the required
plumbing when changing the parent a of Resettable object.
We need to make sure that the reset state of the object remains
coherent with the reset state of the new parent.
We make the 2 following hypothesis:
+ when an object is put in a parent under reset, the object goes in
reset.
+ when an object is removed from a parent under reset, the object
leaves reset.
The added function avoids any glitch if both old and new parent are
already in reset.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/resettable.h | 16 +++++++++++
hw/core/resettable.c | 62 +++++++++++++++++++++++++++++++++++++++--
hw/core/trace-events | 1 +
3 files changed, 77 insertions(+), 2 deletions(-)
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index c0b9fc6ad62..96073354fd6 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -194,6 +194,22 @@ void resettable_release_reset(Object *obj, ResetType type);
*/
bool resettable_is_in_reset(Object *obj);
+/**
+ * resettable_change_parent:
+ * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp.
+ * All 3 objects must implement resettable interface. @oldp or @newp may be
+ * NULL.
+ *
+ * This function will adapt the reset state of @obj so that it is coherent
+ * with the reset state of @newp. It may trigger @resettable_assert_reset()
+ * or @resettable_release_reset(). It will do such things only if the reset
+ * state of @newp and @oldp are different.
+ *
+ * When using this function during reset, it must only be called during
+ * a hold phase method. Calling this during enter or exit phase is an error.
+ */
+void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
+
/**
* resettable_class_set_parent_phases:
*
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
index 91332084870..6e0b0f492f1 100644
--- a/hw/core/resettable.c
+++ b/hw/core/resettable.c
@@ -28,12 +28,16 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
* enter_phase_in_progress:
* True if we are currently in reset enter phase.
*
- * Note: This flag is only used to guarantee (using asserts) that the reset
- * API is used correctly. We can use a global variable because we rely on the
+ * exit_phase_in_progress:
+ * count the number of exit phase we are in.
+ *
+ * Note: These flags are only used to guarantee (using asserts) that the reset
+ * API is used correctly. We can use global variables because we rely on the
* iothread mutex to ensure only one reset operation is in a progress at a
* given time.
*/
static bool enter_phase_in_progress;
+static unsigned exit_phase_in_progress;
void resettable_reset(Object *obj, ResetType type)
{
@@ -65,7 +69,9 @@ void resettable_release_reset(Object *obj, ResetType type)
trace_resettable_reset_release_begin(obj, type);
assert(!enter_phase_in_progress);
+ exit_phase_in_progress += 1;
resettable_phase_exit(obj, NULL, type);
+ exit_phase_in_progress -= 1;
trace_resettable_reset_release_end(obj);
}
@@ -206,6 +212,58 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
trace_resettable_phase_exit_end(obj, obj_typename, s->count);
}
+/*
+ * resettable_get_count:
+ * Get the count of the Resettable object @obj. Return 0 if @obj is NULL.
+ */
+static unsigned resettable_get_count(Object *obj)
+{
+ if (obj) {
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ return rc->get_state(obj)->count;
+ }
+ return 0;
+}
+
+void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
+{
+ ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+ ResettableState *s = rc->get_state(obj);
+ unsigned newp_count = resettable_get_count(newp);
+ unsigned oldp_count = resettable_get_count(oldp);
+
+ /*
+ * Ensure we do not change parent when in enter or exit phase.
+ * During these phases, the reset subtree being updated is partly in reset
+ * and partly not in reset (it depends on the actual position in
+ * resettable_child_foreach()s). We are not able to tell in which part is a
+ * leaving or arriving device. Thus we cannot set the reset count of the
+ * moving device to the proper value.
+ */
+ assert(!enter_phase_in_progress && !exit_phase_in_progress);
+ trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count);
+
+ /*
+ * At most one of the two 'for' loops will be executed below
+ * in order to cope with the difference between the two counts.
+ */
+ /* if newp is more reset than oldp */
+ for (unsigned i = oldp_count; i < newp_count; i++) {
+ resettable_assert_reset(obj, RESET_TYPE_COLD);
+ }
+ /*
+ * if obj is leaving a bus under reset, we need to ensure
+ * hold phase is not pending.
+ */
+ if (oldp_count && s->hold_phase_pending) {
+ resettable_phase_hold(obj, NULL, RESET_TYPE_COLD);
+ }
+ /* if oldp is more reset than newp */
+ for (unsigned i = newp_count; i < oldp_count; i++) {
+ resettable_release_reset(obj, RESET_TYPE_COLD);
+ }
+}
+
void resettable_class_set_parent_phases(ResettableClass *rc,
ResettableEnterPhase enter,
ResettableHoldPhase hold,
diff --git a/hw/core/trace-events b/hw/core/trace-events
index 77d61cb66e6..aecd8e160eb 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -16,6 +16,7 @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
resettable_reset_assert_end(void *obj) "obj=%p"
resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
resettable_reset_release_end(void *obj) "obj=%p"
+resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)"
resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2020-01-30 16:15 ` [PULL 13/26] hw/core/resettable: add support for changing parent Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 15/26] hw/core/qdev: update hotplug reset " Peter Maydell
` (12 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
In qdev_set_parent_bus(), when changing the parent bus of a
realized device, if the source and destination buses are not in the
same reset state, some adaptations are required. This patch adds
needed call to resettable_change_parent() to make sure a device reset
state stays coherent with its parent bus.
The addition is a no-op if:
1. the device being parented is not realized.
2. the device is realized, but both buses are not under reset.
Case 2 means that as long as qdev_set_parent_bus() is called
during the machine realization procedure (which is before the
machine reset so nothing is in reset), it is a no op.
There are 52 call sites of qdev_set_parent_bus(). All but one fall
into the no-op case:
+ 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/
{vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device
parent bus just before realizing the same vdev(vgpu).
+ hw/core/qdev.c: when creating a device in qdev_try_create()
+ hw/core/sysbus.c: when initializing a device in the sysbus
+ hw/i386/amd_iommu.c: before realizing AMDVIState/pci
+ hw/isa/piix4.c: before realizing PIIX4State/rtc
+ hw/misc/auxbus.c: when creating an AUXBus
+ hw/misc/auxbus.c: when creating an AUXBus child
+ hw/misc/macio/macio.c: when initializing a MACIOState child
+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu
+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda
+ hw/net/virtio-net.c: Used for migration when using the failover
mechanism to migration a vfio-pci/net. It is
a no-op because at this point the device is
already on the bus.
+ hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root
+ hw/pci-host/gpex.c: before realizing GPEXHost/root
+ hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev
+ hw/pci-host/q35.c: before realizing Q35PCIHost/mch
+ hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev
+ hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root
+ hw/s390x/event-facility.c: when creating SCLPEventFacility/
TYPE_SCLP_QUIESCE
+ hw/s390x/event-facility.c: ditto with SCLPEventFacility/
TYPE_SCLP_CPU_HOTPLUG
+ hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice
just after realizing it. Ok because at this point the destination
bus (sysbus) is not in reset; the realize step is before the
machine reset.
+ hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below.
+ hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs
line in ssi_auto_connect_slave(). Ok because this function is only
used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c,
hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c.
+ hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device
+ qdev-monitor.c: in device hotplug creation procedure before realize
Note that this commit alone will have no effect, right now there is no
use of resettable API to reset anything. So a bus will never be tagged
as in-reset by this same API.
The one place where side-effect will occurs is in hw/sd/core.c in
sdbus_reparent_card(). This function is only used in the raspi machines,
including during the sysbus reset procedure. This case will be
carrefully handled when doing the multiple phase reset transition.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/core/qdev.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index b2affd8f92b..28fc93b1074 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -96,25 +96,31 @@ static void bus_add_child(BusState *bus, DeviceState *child)
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
{
- bool replugging = dev->parent_bus != NULL;
+ BusState *old_parent_bus = dev->parent_bus;
- if (replugging) {
+ if (old_parent_bus) {
trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
- dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
+ old_parent_bus, object_get_typename(OBJECT(old_parent_bus)),
OBJECT(bus), object_get_typename(OBJECT(bus)));
/*
* Keep a reference to the device while it's not plugged into
* any bus, to avoid it potentially evaporating when it is
* dereffed in bus_remove_child().
+ * Also keep the ref of the parent bus until the end, so that
+ * we can safely call resettable_change_parent() below.
*/
object_ref(OBJECT(dev));
bus_remove_child(dev->parent_bus, dev);
- object_unref(OBJECT(dev->parent_bus));
}
dev->parent_bus = bus;
object_ref(OBJECT(bus));
bus_add_child(bus, dev);
- if (replugging) {
+ if (dev->realized) {
+ resettable_change_parent(OBJECT(dev), OBJECT(bus),
+ OBJECT(old_parent_bus));
+ }
+ if (old_parent_bus) {
+ object_unref(OBJECT(old_parent_bus));
object_unref(OBJECT(dev));
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 15/26] hw/core/qdev: update hotplug reset regarding resettable
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2020-01-30 16:15 ` [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones Peter Maydell
` (11 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
This commit make use of the resettable API to reset the device being
hotplugged when it is realized. Also it ensures it is put in a reset
state coherent with the parent it is plugged into.
Note that there is a difference in the reset. Instead of resetting
only the hotplugged device, we reset also its subtree (switch to
resettable API). This is not expected to be a problem because
sub-buses are just realized too. If a hotplugged device has any
sub-buses it is logical to reset them too at this point.
The recently added should_be_hidden and PCI's partially_hotplugged
mechanisms do not interfere with realize operation:
+ In the should_be_hidden use case, device creation is
delayed.
+ The partially_hotplugged mechanism prevents a device to be
unplugged and unrealized from qdev POV and unrealized.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/resettable.h | 11 +++++++++++
hw/core/qdev.c | 15 ++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index 96073354fd6..5e215d94e42 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -153,6 +153,17 @@ struct ResettableState {
bool exit_phase_in_progress;
};
+/**
+ * resettable_state_clear:
+ * Clear the state. It puts the state to the initial (zeroed) state required
+ * to reuse an object. Typically used in realize step of base classes
+ * implementing the interface.
+ */
+static inline void resettable_state_clear(ResettableState *state)
+{
+ memset(state, 0, sizeof(ResettableState));
+}
+
/**
* resettable_reset:
* Trigger a reset on an object @obj of type @type. @obj must implement
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 28fc93b1074..7697f033b19 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -909,6 +909,12 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
}
}
+ /*
+ * Clear the reset state, in case the object was previously unrealized
+ * with a dirty state.
+ */
+ resettable_state_clear(&dev->reset);
+
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
object_property_set_bool(OBJECT(bus), true, "realized",
&local_err);
@@ -917,7 +923,14 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
}
}
if (dev->hotplugged) {
- device_legacy_reset(dev);
+ /*
+ * Reset the device, as well as its subtree which, at this point,
+ * should be realized too.
+ */
+ resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD);
+ resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus),
+ NULL);
+ resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD);
}
dev->pending_deleted_event = false;
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2020-01-30 16:15 ` [PULL 15/26] hw/core/qdev: update hotplug reset " Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface Peter Maydell
` (10 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Deprecate device_legacy_reset(), qdev_reset_all() and
qbus_reset_all() to be replaced by new functions
device_cold_reset() and bus_cold_reset() which uses resettable API.
Also introduce resettable_cold_reset_fn() which may be used as a
replacement for qdev_reset_all_fn and qbus_reset_all_fn().
Following patches will be needed to look at legacy reset call sites
and switch to resettable api. The legacy functions will be removed
when unused.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/qdev-core.h | 27 +++++++++++++++++++++++++++
include/hw/resettable.h | 9 +++++++++
hw/core/bus.c | 5 +++++
hw/core/qdev.c | 5 +++++
hw/core/resettable.c | 5 +++++
5 files changed, 51 insertions(+)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 09b7a441eb6..1405b8a990a 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -411,6 +411,13 @@ int qdev_walk_children(DeviceState *dev,
qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
void *opaque);
+/**
+ * @qdev_reset_all:
+ * Reset @dev. See @qbus_reset_all() for more details.
+ *
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use device_cold_reset() now.
+ */
void qdev_reset_all(DeviceState *dev);
void qdev_reset_all_fn(void *opaque);
@@ -423,10 +430,28 @@ void qdev_reset_all_fn(void *opaque);
* hard reset means that qbus_reset_all will reset all state of the device.
* For PCI devices, for example, this will include the base address registers
* or configuration space.
+ *
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use bus_cold_reset() now.
*/
void qbus_reset_all(BusState *bus);
void qbus_reset_all_fn(void *opaque);
+/**
+ * device_cold_reset:
+ * Reset device @dev and perform a recursive processing using the resettable
+ * interface. It triggers a RESET_TYPE_COLD.
+ */
+void device_cold_reset(DeviceState *dev);
+
+/**
+ * bus_cold_reset:
+ *
+ * Reset bus @bus and perform a recursive processing using the resettable
+ * interface. It triggers a RESET_TYPE_COLD.
+ */
+void bus_cold_reset(BusState *bus);
+
/**
* device_is_in_reset:
* Return true if the device @dev is currently being reset.
@@ -457,6 +482,8 @@ void qdev_machine_init(void);
* device_legacy_reset:
*
* Reset a single device (by calling the reset method).
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use device_cold_reset() now.
*/
void device_legacy_reset(DeviceState *dev);
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index 5e215d94e42..f4c4bab0eff 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -221,6 +221,15 @@ bool resettable_is_in_reset(Object *obj);
*/
void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
+/**
+ * resettable_cold_reset_fn:
+ * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD).
+ *
+ * This function is typically useful to register a reset handler with
+ * qemu_register_reset.
+ */
+void resettable_cold_reset_fn(void *opaque);
+
/**
* resettable_class_set_parent_phases:
*
diff --git a/hw/core/bus.c b/hw/core/bus.c
index 2698f715bd7..3dc0a825f09 100644
--- a/hw/core/bus.c
+++ b/hw/core/bus.c
@@ -68,6 +68,11 @@ int qbus_walk_children(BusState *bus,
return 0;
}
+void bus_cold_reset(BusState *bus)
+{
+ resettable_reset(OBJECT(bus), RESET_TYPE_COLD);
+}
+
bool bus_is_in_reset(BusState *bus)
{
return resettable_is_in_reset(OBJECT(bus));
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 7697f033b19..3937d1eb1a5 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -361,6 +361,11 @@ void qbus_reset_all_fn(void *opaque)
qbus_reset_all(bus);
}
+void device_cold_reset(DeviceState *dev)
+{
+ resettable_reset(OBJECT(dev), RESET_TYPE_COLD);
+}
+
bool device_is_in_reset(DeviceState *dev)
{
return resettable_is_in_reset(OBJECT(dev));
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
index 6e0b0f492f1..96a99ce39ea 100644
--- a/hw/core/resettable.c
+++ b/hw/core/resettable.c
@@ -264,6 +264,11 @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
}
}
+void resettable_cold_reset_fn(void *opaque)
+{
+ resettable_reset((Object *) opaque, RESET_TYPE_COLD);
+}
+
void resettable_class_set_parent_phases(ResettableClass *rc,
ResettableEnterPhase enter,
ResettableHoldPhase hold,
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2020-01-30 16:15 ` [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 18/26] vl: replace deprecated qbus_reset_all registration Peter Maydell
` (9 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/devel/index.rst | 1 +
docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 290 insertions(+)
create mode 100644 docs/devel/reset.rst
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index ac862152dcb..4dc2ca8d715 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -24,3 +24,4 @@ Contents:
tcg
tcg-plugins
bitops
+ reset
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
new file mode 100644
index 00000000000..abea1102dc4
--- /dev/null
+++ b/docs/devel/reset.rst
@@ -0,0 +1,289 @@
+
+=======================================
+Reset in QEMU: the Resettable interface
+=======================================
+
+The reset of qemu objects is handled using the resettable interface declared
+in ``include/hw/resettable.h``.
+
+This interface allows objects to be grouped (on a tree basis); so that the
+whole group can be reset consistently. Each individual member object does not
+have to care about others; in particular, problems of order (which object is
+reset first) are addressed.
+
+As of now DeviceClass and BusClass implement this interface.
+
+
+Triggering reset
+----------------
+
+This section documents the APIs which "users" of a resettable object should use
+to control it. All resettable control functions must be called while holding
+the iothread lock.
+
+You can apply a reset to an object using ``resettable_assert_reset()``. You need
+to call ``resettable_release_reset()`` to release the object from reset. To
+instantly reset an object, without keeping it in reset state, just call
+``resettable_reset()``. These functions take two parameters: a pointer to the
+object to reset and a reset type.
+
+Several types of reset will be supported. For now only cold reset is defined;
+others may be added later. The Resettable interface handles reset types with an
+enum:
+
+``RESET_TYPE_COLD``
+ Cold reset is supported by every resettable object. In QEMU, it means we reset
+ to the initial state corresponding to the start of QEMU; this might differ
+ from what is a real hardware cold reset. It differs from other resets (like
+ warm or bus resets) which may keep certain parts untouched.
+
+Calling ``resettable_reset()`` is equivalent to calling
+``resettable_assert_reset()`` then ``resettable_release_reset()``. It is
+possible to interleave multiple calls to these three functions. There may
+be several reset sources/controllers of a given object. The interface handles
+everything and the different reset controllers do not need to know anything
+about each others. The object will leave reset state only when each other
+controllers end their reset operation. This point is handled internally by
+maintaining a count of in-progress resets; it is crucial to call
+``resettable_release_reset()`` one time and only one time per
+``resettable_assert_reset()`` call.
+
+For now migration of a device or bus in reset is not supported. Care must be
+taken not to delay ``resettable_release_reset()`` after its
+``resettable_assert_reset()`` counterpart.
+
+Note that, since resettable is an interface, the API takes a simple Object as
+parameter. Still, it is a programming error to call a resettable function on a
+non-resettable object and it will trigger a run time assert error. Since most
+calls to resettable interface are done through base class functions, such an
+error is not likely to happen.
+
+For Devices and Buses, the following helper functions exist:
+
+- ``device_cold_reset()``
+- ``bus_cold_reset()``
+
+These are simple wrappers around resettable_reset() function; they only cast the
+Device or Bus into an Object and pass the cold reset type. When possible
+prefer to use these functions instead of ``resettable_reset()``.
+
+Device and bus functions co-exist because there can be semantic differences
+between resetting a bus and resetting the controller bridge which owns it.
+For example, consider a SCSI controller. Resetting the controller puts all
+its registers back to what reset state was as well as reset everything on the
+SCSI bus, whereas resetting just the SCSI bus only resets everything that's on
+it but not the controller.
+
+
+Multi-phase mechanism
+---------------------
+
+This section documents the internals of the resettable interface.
+
+The resettable interface uses a multi-phase system to relieve objects and
+machines from reset ordering problems. To address this, the reset operation
+of an object is split into three well defined phases.
+
+When resetting several objects (for example the whole machine at simulation
+startup), all first phases of all objects are executed, then all second phases
+and then all third phases.
+
+The three phases are:
+
+1. The **enter** phase is executed when the object enters reset. It resets only
+ local state of the object; it must not do anything that has a side-effect
+ on other objects, such as raising or lowering a qemu_irq line or reading or
+ writing guest memory.
+
+2. The **hold** phase is executed for entry into reset, once every object in the
+ group which is being reset has had its *enter* phase executed. At this point
+ devices can do actions that affect other objects.
+
+3. The **exit** phase is executed when the object leaves the reset state.
+ Actions affecting other objects are permitted.
+
+As said in previous section, the interface maintains a count of reset. This
+count is used to ensure phases are executed only when required. *enter* and
+*hold* phases are executed only when asserting reset for the first time
+(if an object is already in reset state when calling
+``resettable_assert_reset()`` or ``resettable_reset()``, they are not
+executed).
+The *exit* phase is executed only when the last reset operation ends. Therefore
+the object does not need to care how many of reset controllers it has and how
+many of them have started a reset.
+
+
+Handling reset in a resettable object
+-------------------------------------
+
+This section documents the APIs that an implementation of a resettable object
+must provide and what functions it has access to. It is intended for people
+who want to implement or convert a class which has the resettable interface;
+for example when specializing an existing device or bus.
+
+Methods to implement
+....................
+
+Three methods should be defined or left empty. Each method corresponds to a
+phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
+``phases.exit()``. They all take the object as parameter. The *enter* method
+also take the reset type as second parameter.
+
+When extending an existing class, these methods may need to be extended too.
+The ``resettable_class_set_parent_phases()`` class function may be used to
+backup parent class methods.
+
+Here follows an example to implement reset for a Device which sets an IO while
+in reset.
+
+::
+
+ static void mydev_reset_enter(Object *obj, ResetType type)
+ {
+ MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+ MyDevState *mydev = MYDEV(obj);
+ /* call parent class enter phase */
+ if (myclass->parent_phases.enter) {
+ myclass->parent_phases.enter(obj, type);
+ }
+ /* initialize local state only */
+ mydev->var = 0;
+ }
+
+ static void mydev_reset_hold(Object *obj)
+ {
+ MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+ MyDevState *mydev = MYDEV(obj);
+ /* call parent class hold phase */
+ if (myclass->parent_phases.hold) {
+ myclass->parent_phases.hold(obj);
+ }
+ /* set an IO */
+ qemu_set_irq(mydev->irq, 1);
+ }
+
+ static void mydev_reset_exit(Object *obj)
+ {
+ MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+ MyDevState *mydev = MYDEV(obj);
+ /* call parent class exit phase */
+ if (myclass->parent_phases.exit) {
+ myclass->parent_phases.exit(obj);
+ }
+ /* clear an IO */
+ qemu_set_irq(mydev->irq, 0);
+ }
+
+ typedef struct MyDevClass {
+ MyParentClass parent_class;
+ /* to store eventual parent reset methods */
+ ResettablePhases parent_phases;
+ } MyDevClass;
+
+ static void mydev_class_init(ObjectClass *class, void *data)
+ {
+ MyDevClass *myclass = MYDEV_CLASS(class);
+ ResettableClass *rc = RESETTABLE_CLASS(class);
+ resettable_class_set_parent_reset_phases(rc,
+ mydev_reset_enter,
+ mydev_reset_hold,
+ mydev_reset_exit,
+ &myclass->parent_phases);
+ }
+
+In the above example, we override all three phases. It is possible to override
+only some of them by passing NULL instead of a function pointer to
+``resettable_class_set_parent_reset_phases()``. For example, the following will
+only override the *enter* phase and leave *hold* and *exit* untouched::
+
+ resettable_class_set_parent_reset_phases(rc, mydev_reset_enter,
+ NULL, NULL,
+ &myclass->parent_phases);
+
+This is equivalent to providing a trivial implementation of the hold and exit
+phases which does nothing but call the parent class's implementation of the
+phase.
+
+Polling the reset state
+.......................
+
+Resettable interface provides the ``resettable_is_in_reset()`` function.
+This function returns true if the object parameter is currently under reset.
+
+An object is under reset from the beginning of the *init* phase to the end of
+the *exit* phase. During all three phases, the function will return that the
+object is in reset.
+
+This function may be used if the object behavior has to be adapted
+while in reset state. For example if a device has an irq input,
+it will probably need to ignore it while in reset; then it can for
+example check the reset state at the beginning of the irq callback.
+
+Note that until migration of the reset state is supported, an object
+should not be left in reset. So apart from being currently executing
+one of the reset phases, the only cases when this function will return
+true is if an external interaction (like changing an io) is made during
+*hold* or *exit* phase of another object in the same reset group.
+
+Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided
+for devices and buses and should be preferred.
+
+
+Base class handling of reset
+----------------------------
+
+This section documents parts of the reset mechanism that you only need to know
+about if you are extending it to work with a new base class other than
+DeviceClass or BusClass, or maintaining the existing code in those classes. Most
+people can ignore it.
+
+Methods to implement
+....................
+
+There are two other methods that need to exist in a class implementing the
+interface: ``get_state()`` and ``child_foreach()``.
+
+``get_state()`` is simple. *resettable* is an interface and, as a consequence,
+does not have any class state structure. But in order to factorize the code, we
+need one. This method must return a pointer to ``ResettableState`` structure.
+The structure must be allocated by the base class; preferably it should be
+located inside the object instance structure.
+
+``child_foreach()`` is more complex. It should execute the given callback on
+every reset child of the given resettable object. All children must be
+resettable too. Additional parameters (a reset type and an opaque pointer) must
+be passed to the callback too.
+
+In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located
+``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented
+to follow the bus hierarchy; for a bus, it calls the function on every child
+device; for a device, it calls the function on every bus child. When we reset
+the main system bus, we reset the whole machine bus tree.
+
+Changing a resettable parent
+............................
+
+One thing which should be taken care of by the base class is handling reset
+hierarchy changes.
+
+The reset hierarchy is supposed to be static and built during machine creation.
+But there are actually some exceptions. To cope with this, the resettable API
+provides ``resettable_change_parent()``. This function allows to set, update or
+remove the parent of a resettable object after machine creation is done. As
+parameters, it takes the object being moved, the old parent if any and the new
+parent if any.
+
+This function can be used at any time when not in a reset operation. During
+a reset operation it must be used only in *hold* phase. Using it in *enter* or
+*exit* phase is an error.
+Also it should not be used during machine creation, although it is harmless to
+do so: the function is a no-op as long as old and new parent are NULL or not
+in reset.
+
+There is currently 2 cases where this function is used:
+
+1. *device hotplug*; it means a new device is introduced on a live bus.
+
+2. *hot bus change*; it means an existing live device is added, moved or
+ removed in the bus hierarchy. At the moment, it occurs only in the raspi
+ machines for changing the sdbus used by sd card.
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 18/26] vl: replace deprecated qbus_reset_all registration
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2020-01-30 16:15 ` [PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration Peter Maydell
` (8 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Replace deprecated qbus_reset_all by resettable_cold_reset_fn for
the sysbus reset registration.
Apart for the raspi machines, this does not impact the behavior
because:
+ at this point resettable just calls the old reset methods of devices
and buses in the same order as qdev/qbus.
+ resettable handlers registered with qemu_register_reset are
serialized; there is no interleaving.
+ eventual explicit calls to legacy reset API (device_reset or
qdev/qbus_reset) inside this reset handler will not be masked out
by resettable mechanism; they do not go through resettable api.
For the raspi machines, during the sysbus reset the sd-card is not
reset twice anymore but only once. This is a consequence of switching
both sysbus reset and changing parent to resettable; it detects the
second reset is not needed. This has no impact on the state after
reset; the sd-card reset method only reset local state and query
information from the block backend.
The raspi reset change can be observed by using the following command
(reset will occurs, then do Ctrl-C to end qemu; no firmware is
given here).
qemu-system-aarch64 -M raspi3 \
-trace resettable_phase_hold_exec \
-trace qdev_update_parent_bus \
-trace resettable_change_parent \
-trace qdev_reset -trace qbus_reset
Before the patch, the qdev/qbus_reset traces show when reset method are
called. After the patch, the resettable_phase_hold_exec show when reset
method are called.
The traced reset order of the raspi3 is listed below. I've added empty
lines and the tree structure.
+->bcm2835-peripherals reset
|
| +->sd-card reset
| +->sd-bus reset
+->bcm2835_gpio reset
| -> dev_update_parent_bus (move the sd-card on the sdhci-bus)
| -> resettable_change_parent
|
+->bcm2835-dma reset
|
| +->bcm2835-sdhost-bus reset
+->bcm2835-sdhost reset
|
| +->sd-card (reset ONLY BEFORE BEFORE THE PATCH)
| +->sdhci-bus reset
+->generic-sdhci reset
|
+->bcm2835-rng reset
+->bcm2835-property reset
+->bcm2835-fb reset
+->bcm2835-mbox reset
+->bcm2835-aux reset
+->pl011 reset
+->bcm2835-ic reset
+->bcm2836-control reset
System reset
In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved
to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method.
Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus.
After the patch, it considered again for reset but its reset method is not
called because it is already flagged as reset.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
vl.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index b0f52c4d6e0..24951b51a94 100644
--- a/vl.c
+++ b/vl.c
@@ -4381,7 +4381,15 @@ int main(int argc, char **argv, char **envp)
/* TODO: once all bus devices are qdevified, this should be done
* when bus is created by qdev.c */
- qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
+ /*
+ * TODO: If we had a main 'reset container' that the whole system
+ * lived in, we could reset that using the multi-phase reset
+ * APIs. For the moment, we just reset the sysbus, which will cause
+ * all devices hanging off it (and all their child buses, recursively)
+ * to be reset. Note that this will *not* reset any Device objects
+ * which are not attached to some part of the qbus tree!
+ */
+ qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
qemu_run_machine_init_done_notifiers();
if (rom_check_and_register_reset() != 0) {
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2020-01-30 16:15 ` [PULL 18/26] vl: replace deprecated qbus_reset_all registration Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit Peter Maydell
` (7 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Damien Hedde <damien.hedde@greensocs.com>
Replace deprecated qdev_reset_all by resettable_cold_reset_fn for
the ipl registration in the main reset handlers.
This does not impact the behavior for the following reasons:
+ at this point resettable just call the old reset methods of devices
and buses in the same order than qdev/qbus.
+ resettable handlers registered with qemu_register_reset are
serialized; there is no interleaving.
+ eventual explicit calls to legacy reset API (device_reset or
qdev/qbus_reset) inside this reset handler will not be masked out
by resettable mechanism; they do not go through resettable api.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/s390x/ipl.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index ca8e7db4672..7773499d7f7 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -237,7 +237,15 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
*/
ipl->compat_start_addr = ipl->start_addr;
ipl->compat_bios_start_addr = ipl->bios_start_addr;
- qemu_register_reset(qdev_reset_all_fn, dev);
+ /*
+ * Because this Device is not on any bus in the qbus tree (it is
+ * not a sysbus device and it's not on some other bus like a PCI
+ * bus) it will not be automatically reset by the 'reset the
+ * sysbus' hook registered by vl.c like most devices. So we must
+ * manually register a reset hook for it.
+ * TODO: there should be a better way to do this.
+ */
+ qemu_register_reset(resettable_cold_reset_fn, dev);
error:
error_propagate(errp, err);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2020-01-30 16:15 ` [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 21/26] target/arm/kvm: trivial: Clean up header documentation Peter Maydell
` (6 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Zenghui Yu <yuzenghui@huawei.com>
If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when
restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC
initialization time".
And what's worse, PTZ is generally programmed by guest to indicate to the
Redistributor whether the LPI Pending table is zero when enabling LPIs.
If migration is triggered when the PTZ has just been cleared by guest (and
before enabling LPIs), we will see PTZ==1 on the destination side, which
is not as expected. Let's just drop this hackish userspace behavior.
Also take this chance to refine the comment a bit.
Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20200119133051.642-1-yuzenghui@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_kvm.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 9c7f4ab8711..49304ca589d 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -336,7 +336,10 @@ static void kvm_arm_gicv3_put(GICv3State *s)
kvm_gicd_access(s, GICD_CTLR, ®, true);
if (redist_typer & GICR_TYPER_PLPIS) {
- /* Set base addresses before LPIs are enabled by GICR_CTLR write */
+ /*
+ * Restore base addresses before LPIs are potentially enabled by
+ * GICR_CTLR write
+ */
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
@@ -347,12 +350,6 @@ static void kvm_arm_gicv3_put(GICv3State *s)
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true);
reg64 = c->gicr_pendbaser;
- if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
- /* Setting PTZ is advised if LPIs are disabled, to reduce
- * GIC initialization time.
- */
- reg64 |= GICR_PENDBASER_PTZ;
- }
regl = (uint32_t)reg64;
kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true);
regh = (uint32_t)(reg64 >> 32);
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 21/26] target/arm/kvm: trivial: Clean up header documentation
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2020-01-30 16:15 ` [PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options Peter Maydell
` (5 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-2-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 8e14d400e8a..b48a9c95573 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -28,9 +28,9 @@
int kvm_arm_vcpu_init(CPUState *cs);
/**
- * kvm_arm_vcpu_finalize
+ * kvm_arm_vcpu_finalize:
* @cs: CPUState
- * @feature: int
+ * @feature: feature to finalize
*
* Finalizes the configuration of the specified VCPU feature by
* invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
@@ -75,8 +75,8 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
int kvm_arm_init_cpreg_list(ARMCPU *cpu);
/**
- * kvm_arm_reg_syncs_via_cpreg_list
- * regidx: KVM register index
+ * kvm_arm_reg_syncs_via_cpreg_list:
+ * @regidx: KVM register index
*
* Return true if this KVM register should be synchronized via the
* cpreg list of arbitrary system registers, false if it is synchronized
@@ -85,8 +85,8 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu);
bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx);
/**
- * kvm_arm_cpreg_level
- * regidx: KVM register index
+ * kvm_arm_cpreg_level:
+ * @regidx: KVM register index
*
* Return the level of this coprocessor/system register. Return value is
* either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE.
@@ -148,6 +148,8 @@ void kvm_arm_init_serror_injection(CPUState *cs);
* @cpu: ARMCPU
*
* Get VCPU related state from kvm.
+ *
+ * Returns: 0 if success else < 0 error code
*/
int kvm_get_vcpu_events(ARMCPU *cpu);
@@ -156,6 +158,8 @@ int kvm_get_vcpu_events(ARMCPU *cpu);
* @cpu: ARMCPU
*
* Put VCPU related state to kvm.
+ *
+ * Returns: 0 if success else < 0 error code
*/
int kvm_put_vcpu_events(ARMCPU *cpu);
@@ -205,10 +209,12 @@ typedef struct ARMHostCPUFeatures {
/**
* kvm_arm_get_host_cpu_features:
- * @ahcc: ARMHostCPUClass to fill in
+ * @ahcf: ARMHostCPUClass to fill in
*
* Probe the capabilities of the host kernel's preferred CPU and fill
* in the ARMHostCPUClass struct accordingly.
+ *
+ * Returns true on success and false otherwise.
*/
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
@@ -242,7 +248,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
bool kvm_arm_aarch32_supported(CPUState *cs);
/**
- * bool kvm_arm_pmu_supported:
+ * kvm_arm_pmu_supported:
* @cs: CPUState
*
* Returns: true if the KVM VCPU can enable its PMU
@@ -251,7 +257,7 @@ bool kvm_arm_aarch32_supported(CPUState *cs);
bool kvm_arm_pmu_supported(CPUState *cs);
/**
- * bool kvm_arm_sve_supported:
+ * kvm_arm_sve_supported:
* @cs: CPUState
*
* Returns true if the KVM VCPU can enable SVE and false otherwise.
@@ -259,26 +265,30 @@ bool kvm_arm_pmu_supported(CPUState *cs);
bool kvm_arm_sve_supported(CPUState *cs);
/**
- * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
- * IPA address space supported by KVM
- *
+ * kvm_arm_get_max_vm_ipa_size:
* @ms: Machine state handle
+ *
+ * Returns the number of bits in the IPA address space supported by KVM
*/
int kvm_arm_get_max_vm_ipa_size(MachineState *ms);
/**
- * kvm_arm_sync_mpstate_to_kvm
+ * kvm_arm_sync_mpstate_to_kvm:
* @cpu: ARMCPU
*
* If supported set the KVM MP_STATE based on QEMU's model.
+ *
+ * Returns 0 on success and -1 on failure.
*/
int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
/**
- * kvm_arm_sync_mpstate_to_qemu
+ * kvm_arm_sync_mpstate_to_qemu:
* @cpu: ARMCPU
*
* If supported get the MP_STATE from KVM and store in QEMU's model.
+ *
+ * Returns 0 on success and aborts on failure.
*/
int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
@@ -292,7 +302,8 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
{
- /* This should never actually be called in the "not KVM" case,
+ /*
+ * This should never actually be called in the "not KVM" case,
* but set up the fields to indicate an error anyway.
*/
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
@@ -377,23 +388,20 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit);
*
* Return: TRUE if any hardware breakpoints in use.
*/
-
bool kvm_arm_hw_debug_active(CPUState *cs);
/**
* kvm_arm_copy_hw_debug_data:
- *
* @ptr: kvm_guest_debug_arch structure
*
* Copy the architecture specific debug registers into the
* kvm_guest_debug ioctl structure.
*/
struct kvm_guest_debug_arch;
-
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
/**
- * its_class_name
+ * its_class_name:
*
* Return the ITS class name to use depending on whether KVM acceleration
* and KVM CAP_SIGNAL_MSI are supported
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2020-01-30 16:15 ` [PULL 21/26] target/arm/kvm: trivial: Clean up header documentation Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers Peter Maydell
` (4 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-3-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 656b0081c2c..91d4b838b2e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2153,6 +2153,7 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
static void virt_machine_4_2_options(MachineClass *mc)
{
+ virt_machine_5_0_options(mc);
compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
}
DEFINE_VIRT_MACHINE(4, 2)
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2020-01-30 16:15 ` [PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 24/26] tests/arm-cpu-features: Check feature default values Peter Maydell
` (3 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
Add the missing GENERIC_TIMER feature to kvm64 cpus.
We don't currently use these registers when KVM is enabled, but it's
probably best we add the feature flag for consistency and potential
future use. There's also precedent, as we add the PMU feature flag to
KVM enabled guests, even though we don't use those registers either.
This change was originally posted as a hunk of a different, never
merged patch from Bijan Mottahedeh.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200120101023.16030-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 6344113a680..8955d23affd 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -604,6 +604,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
set_feature(&features, ARM_FEATURE_NEON);
set_feature(&features, ARM_FEATURE_AARCH64);
set_feature(&features, ARM_FEATURE_PMU);
+ set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
ahcf->features = features;
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 24/26] tests/arm-cpu-features: Check feature default values
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2020-01-30 16:15 ` [PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 25/26] target/arm/kvm: Implement virtual time adjustment Peter Maydell
` (2 subsequent siblings)
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
If we know what the default value should be then we can test for
that as well as the feature existence.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200120101023.16030-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index bef3ed24b60..a039e3c8d72 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -159,6 +159,25 @@ static bool resp_get_feature(QDict *resp, const char *feature)
qobject_unref(_resp); \
})
+#define assert_feature(qts, cpu_type, feature, expected_value) \
+({ \
+ QDict *_resp, *_props; \
+ \
+ _resp = do_query_no_props(qts, cpu_type); \
+ g_assert(_resp); \
+ g_assert(resp_has_props(_resp)); \
+ _props = resp_get_props(_resp); \
+ g_assert(qdict_get(_props, feature)); \
+ g_assert(qdict_get_bool(_props, feature) == (expected_value)); \
+ qobject_unref(_resp); \
+})
+
+#define assert_has_feature_enabled(qts, cpu_type, feature) \
+ assert_feature(qts, cpu_type, feature, true)
+
+#define assert_has_feature_disabled(qts, cpu_type, feature) \
+ assert_feature(qts, cpu_type, feature, false)
+
static void assert_type_full(QTestState *qts)
{
const char *error;
@@ -405,16 +424,16 @@ static void test_query_cpu_model_expansion(const void *data)
assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
/* Test expected feature presence/absence for some cpu types */
- assert_has_feature(qts, "max", "pmu");
- assert_has_feature(qts, "cortex-a15", "pmu");
+ assert_has_feature_enabled(qts, "max", "pmu");
+ assert_has_feature_enabled(qts, "cortex-a15", "pmu");
assert_has_not_feature(qts, "cortex-a15", "aarch64");
if (g_str_equal(qtest_get_arch(), "aarch64")) {
- assert_has_feature(qts, "max", "aarch64");
- assert_has_feature(qts, "max", "sve");
- assert_has_feature(qts, "max", "sve128");
- assert_has_feature(qts, "cortex-a57", "pmu");
- assert_has_feature(qts, "cortex-a57", "aarch64");
+ assert_has_feature_enabled(qts, "max", "aarch64");
+ assert_has_feature_enabled(qts, "max", "sve");
+ assert_has_feature_enabled(qts, "max", "sve128");
+ assert_has_feature_enabled(qts, "cortex-a57", "pmu");
+ assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
sve_tests_default(qts, "max");
@@ -451,8 +470,8 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
QDict *resp;
char *error;
- assert_has_feature(qts, "host", "aarch64");
- assert_has_feature(qts, "host", "pmu");
+ assert_has_feature_enabled(qts, "host", "aarch64");
+ assert_has_feature_enabled(qts, "host", "pmu");
assert_error(qts, "cortex-a15",
"We cannot guarantee the CPU type 'cortex-a15' works "
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 25/26] target/arm/kvm: Implement virtual time adjustment
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2020-01-30 16:15 ` [PULL 24/26] tests/arm-cpu-features: Check feature default values Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 16:15 ` [PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property Peter Maydell
2020-01-30 19:05 ` [PULL 00/26] target-arm queue Peter Maydell
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
When a VM is stopped (such as when it's paused) guest virtual time
should stop counting. Otherwise, when the VM is resumed it will
experience time jumps and its kernel may report soft lockups. Not
counting virtual time while the VM is stopped has the side effect
of making the guest's time appear to lag when compared with real
time, and even with time derived from the physical counter. For
this reason, this change, which is enabled by default, comes with
a KVM CPU feature allowing it to be disabled, restoring legacy
behavior.
This patch only provides the implementation of the virtual time
adjustment. A subsequent patch will provide the CPU property
allowing the change to be enabled and disabled.
Reported-by: Bijan Mottahedeh <bijan.mottahedeh@oracle.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-6-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 7 ++++
target/arm/kvm_arm.h | 38 ++++++++++++++++++
target/arm/kvm.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
target/arm/kvm32.c | 3 ++
target/arm/kvm64.c | 3 ++
target/arm/machine.c | 7 ++++
6 files changed, 150 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c1aedbeac0d..608fcbd0b75 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -821,6 +821,13 @@ struct ARMCPU {
/* KVM init features for this CPU */
uint32_t kvm_init_features[7];
+ /* KVM CPU state */
+
+ /* KVM virtual time adjustment */
+ bool kvm_adjvtime;
+ bool kvm_vtime_dirty;
+ uint64_t kvm_vtime;
+
/* Uniprocessor system with MP extensions */
bool mp_is_up;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index b48a9c95573..01a9a182785 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -127,6 +127,23 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level);
*/
bool write_kvmstate_to_list(ARMCPU *cpu);
+/**
+ * kvm_arm_cpu_pre_save:
+ * @cpu: ARMCPU
+ *
+ * Called after write_kvmstate_to_list() from cpu_pre_save() to update
+ * the cpreg list with KVM CPU state.
+ */
+void kvm_arm_cpu_pre_save(ARMCPU *cpu);
+
+/**
+ * kvm_arm_cpu_post_load:
+ * @cpu: ARMCPU
+ *
+ * Called from cpu_post_load() to update KVM CPU state from the cpreg list.
+ */
+void kvm_arm_cpu_post_load(ARMCPU *cpu);
+
/**
* kvm_arm_reset_vcpu:
* @cpu: ARMCPU
@@ -292,6 +309,24 @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
*/
int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
+/**
+ * kvm_arm_get_virtual_time:
+ * @cs: CPUState
+ *
+ * Gets the VCPU's virtual counter and stores it in the KVM CPU state.
+ */
+void kvm_arm_get_virtual_time(CPUState *cs);
+
+/**
+ * kvm_arm_put_virtual_time:
+ * @cs: CPUState
+ *
+ * Sets the VCPU's virtual counter to the value stored in the KVM CPU state.
+ */
+void kvm_arm_put_virtual_time(CPUState *cs);
+
+void kvm_arm_vm_state_change(void *opaque, int running, RunState state);
+
int kvm_arm_vgic_probe(void);
void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
@@ -339,6 +374,9 @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
static inline void kvm_arm_pmu_init(CPUState *cs) {}
static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
+
+static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
+static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
#endif
static inline const char *gic_class_name(void)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 8d828891506..e36ab0b38bf 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -357,6 +357,22 @@ static int compare_u64(const void *a, const void *b)
return 0;
}
+/*
+ * cpreg_values are sorted in ascending order by KVM register ID
+ * (see kvm_arm_init_cpreg_list). This allows us to cheaply find
+ * the storage for a KVM register by ID with a binary search.
+ */
+static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx)
+{
+ uint64_t *res;
+
+ res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len,
+ sizeof(uint64_t), compare_u64);
+ assert(res);
+
+ return &cpu->cpreg_values[res - cpu->cpreg_indexes];
+}
+
/* Initialize the ARMCPU cpreg list according to the kernel's
* definition of what CPU registers it knows about (and throw away
* the previous TCG-created cpreg list).
@@ -510,6 +526,23 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
return ok;
}
+void kvm_arm_cpu_pre_save(ARMCPU *cpu)
+{
+ /* KVM virtual time adjustment */
+ if (cpu->kvm_vtime_dirty) {
+ *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime;
+ }
+}
+
+void kvm_arm_cpu_post_load(ARMCPU *cpu)
+{
+ /* KVM virtual time adjustment */
+ if (cpu->kvm_adjvtime) {
+ cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT);
+ cpu->kvm_vtime_dirty = true;
+ }
+}
+
void kvm_arm_reset_vcpu(ARMCPU *cpu)
{
int ret;
@@ -577,6 +610,50 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
return 0;
}
+void kvm_arm_get_virtual_time(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ struct kvm_one_reg reg = {
+ .id = KVM_REG_ARM_TIMER_CNT,
+ .addr = (uintptr_t)&cpu->kvm_vtime,
+ };
+ int ret;
+
+ if (cpu->kvm_vtime_dirty) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
+ abort();
+ }
+
+ cpu->kvm_vtime_dirty = true;
+}
+
+void kvm_arm_put_virtual_time(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ struct kvm_one_reg reg = {
+ .id = KVM_REG_ARM_TIMER_CNT,
+ .addr = (uintptr_t)&cpu->kvm_vtime,
+ };
+ int ret;
+
+ if (!cpu->kvm_vtime_dirty) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
+ abort();
+ }
+
+ cpu->kvm_vtime_dirty = false;
+}
+
int kvm_put_vcpu_events(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -688,6 +765,21 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
return MEMTXATTRS_UNSPECIFIED;
}
+void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
+{
+ CPUState *cs = opaque;
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ if (running) {
+ if (cpu->kvm_adjvtime) {
+ kvm_arm_put_virtual_time(cs);
+ }
+ } else {
+ if (cpu->kvm_adjvtime) {
+ kvm_arm_get_virtual_time(cs);
+ }
+ }
+}
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 32bf8d6757c..3a8b437eef0 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -16,6 +16,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "qemu/timer.h"
+#include "sysemu/runstate.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "internals.h"
@@ -198,6 +199,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
return -EINVAL;
}
+ qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
+
/* Determine init features for this CPU */
memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
if (cpu->start_powered_off) {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 8955d23affd..fb21ab9e737 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -23,6 +23,7 @@
#include "qemu/host-utils.h"
#include "qemu/main-loop.h"
#include "exec/gdbstub.h"
+#include "sysemu/runstate.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_int.h"
#include "kvm_arm.h"
@@ -734,6 +735,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
return -EINVAL;
}
+ qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
+
/* Determine init features for this CPU */
memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
if (cpu->start_powered_off) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index eb28b2381bb..241890ac8cf 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -642,6 +642,12 @@ static int cpu_pre_save(void *opaque)
/* This should never fail */
abort();
}
+
+ /*
+ * kvm_arm_cpu_pre_save() must be called after
+ * write_kvmstate_to_list()
+ */
+ kvm_arm_cpu_pre_save(cpu);
} else {
if (!write_cpustate_to_list(cpu, false)) {
/* This should never fail. */
@@ -744,6 +750,7 @@ static int cpu_post_load(void *opaque, int version_id)
* we're using it.
*/
write_list_to_cpustate(cpu);
+ kvm_arm_cpu_post_load(cpu);
} else {
if (!write_list_to_cpustate(cpu)) {
return -1;
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2020-01-30 16:15 ` [PULL 25/26] target/arm/kvm: Implement virtual time adjustment Peter Maydell
@ 2020-01-30 16:15 ` Peter Maydell
2020-01-30 19:05 ` [PULL 00/26] target-arm queue Peter Maydell
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 16:15 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
kvm-no-adjvtime is a KVM specific CPU property and a first of its
kind. To accommodate it we also add kvm_arm_add_vcpu_properties()
and a KVM specific CPU properties description to the CPU features
document.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-7-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/virt.h | 1 +
target/arm/kvm_arm.h | 11 ++++++++++
hw/arm/virt.c | 8 ++++++++
target/arm/cpu.c | 2 ++
target/arm/cpu64.c | 1 +
target/arm/kvm.c | 28 +++++++++++++++++++++++++
target/arm/monitor.c | 1 +
tests/qtest/arm-cpu-features.c | 4 ++++
docs/arm-cpu-features.rst | 37 +++++++++++++++++++++++++++++++++-
9 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 38f0c33c77c..71508bf40c3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -109,6 +109,7 @@ typedef struct {
bool smbios_old_sys_ver;
bool no_highmem_ecam;
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
+ bool kvm_no_adjvtime;
} VirtMachineClass;
typedef struct {
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 01a9a182785..ae9e075d754 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -255,6 +255,15 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
*/
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
+/**
+ * kvm_arm_add_vcpu_properties:
+ * @obj: The CPU object to add the properties to
+ *
+ * Add all KVM specific CPU properties to the CPU object. These
+ * are the CPU properties with "kvm-" prefixed names.
+ */
+void kvm_arm_add_vcpu_properties(Object *obj);
+
/**
* kvm_arm_aarch32_supported:
* @cs: CPUState
@@ -345,6 +354,8 @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
cpu->host_cpu_probe_failed = true;
}
+static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
+
static inline bool kvm_arm_aarch32_supported(CPUState *cs)
{
return false;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 91d4b838b2e..f788fe27d63 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1663,6 +1663,11 @@ static void machvirt_init(MachineState *machine)
}
}
+ if (vmc->kvm_no_adjvtime &&
+ object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) {
+ object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL);
+ }
+
if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
object_property_set_bool(cpuobj, false, "pmu", NULL);
}
@@ -2153,8 +2158,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
static void virt_machine_4_2_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_5_0_options(mc);
compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
+ vmc->kvm_no_adjvtime = true;
}
DEFINE_VIRT_MACHINE(4, 2)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 06907b36d7d..f86e71a260d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2551,6 +2551,7 @@ static void arm_max_initfn(Object *obj)
if (kvm_enabled()) {
kvm_arm_set_cpu_features_from_host(cpu);
+ kvm_arm_add_vcpu_properties(obj);
} else {
cortex_a15_initfn(obj);
@@ -2743,6 +2744,7 @@ static void arm_host_initfn(Object *obj)
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
aarch64_add_sve_properties(obj);
}
+ kvm_arm_add_vcpu_properties(obj);
arm_cpu_post_init(obj);
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 61fd0ade29a..2d97bf45e1e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -605,6 +605,7 @@ static void aarch64_max_initfn(Object *obj)
if (kvm_enabled()) {
kvm_arm_set_cpu_features_from_host(cpu);
+ kvm_arm_add_vcpu_properties(obj);
} else {
uint64_t t;
uint32_t u;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index e36ab0b38bf..85860e6f954 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -17,6 +17,8 @@
#include "qemu/timer.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
+#include "qom/object.h"
+#include "qapi/error.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_int.h"
@@ -179,6 +181,32 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
env->features = arm_host_cpu_features.features;
}
+static bool kvm_no_adjvtime_get(Object *obj, Error **errp)
+{
+ return !ARM_CPU(obj)->kvm_adjvtime;
+}
+
+static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
+{
+ ARM_CPU(obj)->kvm_adjvtime = !value;
+}
+
+/* KVM VCPU properties should be prefixed with "kvm-". */
+void kvm_arm_add_vcpu_properties(Object *obj)
+{
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ ARM_CPU(obj)->kvm_adjvtime = true;
+ object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get,
+ kvm_no_adjvtime_set, &error_abort);
+ object_property_set_description(obj, "kvm-no-adjvtime",
+ "Set on to disable the adjustment of "
+ "the virtual counter. VM stopped time "
+ "will be counted.", &error_abort);
+}
+
bool kvm_arm_pmu_supported(CPUState *cpu)
{
return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index fa054f8a369..9725dfff16d 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -103,6 +103,7 @@ static const char *cpu_model_advertised_features[] = {
"sve128", "sve256", "sve384", "sve512",
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
+ "kvm-no-adjvtime",
NULL
};
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index a039e3c8d72..46921736766 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -428,6 +428,8 @@ static void test_query_cpu_model_expansion(const void *data)
assert_has_feature_enabled(qts, "cortex-a15", "pmu");
assert_has_not_feature(qts, "cortex-a15", "aarch64");
+ assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
+
if (g_str_equal(qtest_get_arch(), "aarch64")) {
assert_has_feature_enabled(qts, "max", "aarch64");
assert_has_feature_enabled(qts, "max", "sve");
@@ -462,6 +464,8 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
return;
}
+ assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
+
if (g_str_equal(qtest_get_arch(), "aarch64")) {
bool kvm_supports_sve;
char max_name[8], name[8];
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index 9b537a75e69..dbf3b7cf42c 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -31,7 +31,9 @@ supporting the feature or only supporting the feature under certain
configurations. For example, the `aarch64` CPU feature, which, when
disabled, enables the optional AArch32 CPU feature, is only supported
when using the KVM accelerator and when running on a host CPU type that
-supports the feature.
+supports the feature. While `aarch64` currently only works with KVM,
+it could work with TCG. CPU features that are specific to KVM are
+prefixed with "kvm-" and are described in "KVM VCPU Features".
CPU Feature Probing
===================
@@ -171,6 +173,39 @@ disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
properties have special semantics (see "SVE CPU Property Parsing
Semantics").
+KVM VCPU Features
+=================
+
+KVM VCPU features are CPU features that are specific to KVM, such as
+paravirt features or features that enable CPU virtualization extensions.
+The features' CPU properties are only available when KVM is enabled and
+are named with the prefix "kvm-". KVM VCPU features may be probed,
+enabled, and disabled in the same way as other CPU features. Below is
+the list of KVM VCPU features and their descriptions.
+
+ kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This
+ means that by default the virtual time
+ adjustment is enabled (vtime is *not not*
+ adjusted).
+
+ When virtual time adjustment is enabled each
+ time the VM transitions back to running state
+ the VCPU's virtual counter is updated to ensure
+ stopped time is not counted. This avoids time
+ jumps surprising guest OSes and applications,
+ as long as they use the virtual counter for
+ timekeeping. However it has the side effect of
+ the virtual and physical counters diverging.
+ All timekeeping based on the virtual counter
+ will appear to lag behind any timekeeping that
+ does not subtract VM stopped time. The guest
+ may resynchronize its virtual counter with
+ other time sources as needed.
+
+ Enable kvm-no-adjvtime to disable virtual time
+ adjustment, also restoring the legacy (pre-5.0)
+ behavior.
+
SVE CPU Properties
==================
--
2.20.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2020-01-30 16:15 ` [PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property Peter Maydell
@ 2020-01-30 19:05 ` Peter Maydell
26 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-01-30 19:05 UTC (permalink / raw)
To: QEMU Developers
On Thu, 30 Jan 2020 at 16:15, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue. The big thing here is the landing of the 3-phase
> reset patches...
>
> -- PMM
>
> The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7:
>
> Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130
>
> for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f:
>
> target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
> * target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
> * aspeed: some minor bugfixes
> * aspeed: add eMMC controller model for AST2600 SoC
> * hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
> * New 3-phase reset API for device models
> * hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
> * Arm KVM: stop/restart the guest counter when the VM is stopped and started
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2023-09-08 17:05 Peter Maydell
@ 2023-09-11 15:19 ` Stefan Hajnoczi
0 siblings, 0 replies; 40+ messages in thread
From: Stefan Hajnoczi @ 2023-09-11 15:19 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2023-09-08 17:05 Peter Maydell
2023-09-11 15:19 ` Stefan Hajnoczi
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2023-09-08 17:05 UTC (permalink / raw)
To: qemu-devel
Hi; here's the latest arm pullreq...
-- PMM
The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-09-07 10:29:06 -0400)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230908
for you to fetch changes up to c8f2eb5d414b788420b938f2ffdde891aa6c3ae8:
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE (2023-09-08 16:41:36 +0100)
----------------------------------------------------------------
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
----------------------------------------------------------------
Aaron Lindsay (6):
target/arm: Add ID_AA64ISAR2_EL1
target/arm: Add feature detection for FEAT_Pauth2 and extensions
target/arm: Implement FEAT_EPAC
target/arm: Implement FEAT_Pauth2
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
Colton Lewis (1):
arm64: Restore trapless ptimer access
Francisco Iglesias (8):
hw/misc: Introduce the Xilinx CFI interface
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
Philippe Mathieu-Daudé (1):
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
Richard Henderson (9):
tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC
target/arm: Don't change pauth features when changing algorithm
target/arm: Implement FEAT_PACQARMA3
target/arm: Do not use gen_mte_checkN in trans_STGP
target/arm: Implement RMR_ELx
target/arm: Implement cortex-a710
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement FEAT_TIDCP1
target/arm: Enable SCTLR_EL1.TIDCP for user-only
Shameer Kolothum (1):
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
MAINTAINERS | 10 +
docs/system/arm/cpu-features.rst | 21 +-
docs/system/arm/emulation.rst | 8 +
docs/system/arm/virt.rst | 1 +
include/hw/arm/xlnx-versal.h | 85 +++
include/hw/misc/xlnx-cfi-if.h | 59 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 303 +++++++++++
include/hw/misc/xlnx-versal-cfu.h | 258 ++++++++++
include/sysemu/kvm_int.h | 1 +
target/arm/cpu.h | 54 +-
target/arm/helper.h | 2 +
target/arm/syndrome.h | 7 +
target/arm/tcg/helper-a64.h | 4 +
tests/tcg/aarch64/pauth.h | 23 +
accel/kvm/kvm-all.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xlnx-versal.c | 155 +++++-
hw/intc/arm_gicv3_its.c | 15 +-
hw/misc/xlnx-cfi-if.c | 34 ++
hw/misc/xlnx-versal-cframe-reg.c | 858 +++++++++++++++++++++++++++++++
hw/misc/xlnx-versal-cfu.c | 563 ++++++++++++++++++++
target/arm/arm-qmp-cmds.c | 2 +-
target/arm/cpu.c | 4 +
target/arm/cpu64.c | 86 +++-
target/arm/helper.c | 68 ++-
target/arm/hvf/hvf.c | 1 +
target/arm/kvm.c | 61 +++
target/arm/kvm64.c | 3 +
target/arm/tcg/cpu64.c | 215 ++++++++
target/arm/tcg/op_helper.c | 33 ++
target/arm/tcg/pauth_helper.c | 180 +++++--
target/arm/tcg/translate-a64.c | 74 +--
target/arm/tcg/translate.c | 33 ++
tests/qtest/arm-cpu-features.c | 12 +-
tests/tcg/aarch64/pauth-2.c | 54 +-
tests/tcg/aarch64/pauth-4.c | 18 +-
tests/tcg/aarch64/pauth-5.c | 10 +
hw/misc/meson.build | 3 +
qemu-options.hx | 15 +
tests/tcg/aarch64/Makefile.target | 6 +-
40 files changed, 3184 insertions(+), 157 deletions(-)
create mode 100644 include/hw/misc/xlnx-cfi-if.h
create mode 100644 include/hw/misc/xlnx-versal-cframe-reg.h
create mode 100644 include/hw/misc/xlnx-versal-cfu.h
create mode 100644 tests/tcg/aarch64/pauth.h
create mode 100644 hw/misc/xlnx-cfi-if.c
create mode 100644 hw/misc/xlnx-versal-cframe-reg.c
create mode 100644 hw/misc/xlnx-versal-cfu.c
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2023-06-23 12:31 Peter Maydell
@ 2023-06-25 8:25 ` Richard Henderson
0 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2023-06-25 8:25 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 6/23/23 14:31, Peter Maydell wrote:
> Hi; here's a target-arm pullreq. Mostly this is RTH's FEAT_RME
> series; there are also a handful of bug fixes including some
> which aren't arm-specific but which it's convenient to include
> here.
>
> thanks
> -- PMM
>
> The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
>
> Merge tag 'q800-for-8.1-pull-request' ofhttps://github.com/vivier/qemu-m68k into staging (2023-06-22 10:18:32 +0200)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230623
>
> for you to fetch changes up to 497fad38979c16b6412388927401e577eba43d26:
>
> pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym (2023-06-23 11:46:02 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Add (experimental) support for FEAT_RME
> * host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
> * target/arm: Restructure has_vfp_d32 test
> * hw/arm/sbsa-ref: add ITS support in SBSA GIC
> * target/arm: Fix sve predicate store, 8 <= VQ <= 15
> * pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2023-06-23 12:31 Peter Maydell
2023-06-25 8:25 ` Richard Henderson
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2023-06-23 12:31 UTC (permalink / raw)
To: qemu-devel
Hi; here's a target-arm pullreq. Mostly this is RTH's FEAT_RME
series; there are also a handful of bug fixes including some
which aren't arm-specific but which it's convenient to include
here.
thanks
-- PMM
The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
Merge tag 'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2023-06-22 10:18:32 +0200)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230623
for you to fetch changes up to 497fad38979c16b6412388927401e577eba43d26:
pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym (2023-06-23 11:46:02 +0100)
----------------------------------------------------------------
target-arm queue:
* Add (experimental) support for FEAT_RME
* host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
* target/arm: Restructure has_vfp_d32 test
* hw/arm/sbsa-ref: add ITS support in SBSA GIC
* target/arm: Fix sve predicate store, 8 <= VQ <= 15
* pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
----------------------------------------------------------------
Peter Maydell (2):
host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
Richard Henderson (23):
target/arm: Add isar_feature_aa64_rme
target/arm: Update SCR and HCR for RME
target/arm: SCR_EL3.NS may be RES1
target/arm: Add RME cpregs
target/arm: Introduce ARMSecuritySpace
include/exec/memattrs: Add two bits of space to MemTxAttrs
target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx
target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
target/arm: Remove __attribute__((nonnull)) from ptw.c
target/arm: Pipe ARMSecuritySpace through ptw.c
target/arm: NSTable is RES0 for the RME EL3 regime
target/arm: Handle Block and Page bits for security space
target/arm: Handle no-execute for Realm and Root regimes
target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
target/arm: Move s1_is_el0 into S1Translate
target/arm: Use get_phys_addr_with_struct for stage2
target/arm: Add GPC syndrome
target/arm: Implement GPC exceptions
target/arm: Implement the granule protection check
target/arm: Add cpu properties for enabling FEAT_RME
docs/system/arm: Document FEAT_RME
target/arm: Restructure has_vfp_d32 test
target/arm: Fix sve predicate store, 8 <= VQ <= 15
Shashi Mallela (1):
hw/arm/sbsa-ref: add ITS support in SBSA GIC
docs/system/arm/cpu-features.rst | 23 ++
docs/system/arm/emulation.rst | 1 +
docs/system/arm/sbsa.rst | 14 +
include/exec/memattrs.h | 9 +-
include/qemu/compiler.h | 13 +
include/qemu/host-utils.h | 2 +-
target/arm/cpu.h | 151 ++++++++---
target/arm/internals.h | 27 ++
target/arm/syndrome.h | 10 +
hw/arm/sbsa-ref.c | 33 ++-
target/arm/cpu.c | 32 ++-
target/arm/helper.c | 162 ++++++++++-
target/arm/ptw.c | 570 +++++++++++++++++++++++++++++++--------
target/arm/tcg/cpu64.c | 53 ++++
target/arm/tcg/tlb_helper.c | 96 ++++++-
target/arm/tcg/translate-sve.c | 2 +-
pc-bios/keymaps/meson.build | 2 +-
17 files changed, 1034 insertions(+), 166 deletions(-)
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2023-01-23 13:35 Peter Maydell
@ 2023-01-23 15:17 ` Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2023-01-23 15:17 UTC (permalink / raw)
To: qemu-devel
On Mon, 23 Jan 2023 at 13:35, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 65cc5ccf06a74c98de73ec683d9a543baa302a12:
>
> Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging (2023-01-20 16:17:56 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230123
>
> for you to fetch changes up to 3b07a936d3bfe97b07ddffcfbb532985a88033dd:
>
> target/arm: Look up ARMCPRegInfo at runtime (2023-01-23 13:32:38 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Widen cnthctl_el2 to uint64_t
> * Unify checking for M Main Extension in MRS/MSR
> * bitbang_i2c, versatile_i2c: code cleanups
> * SME: refactor SME SM/ZA handling
> * Fix physical address resolution for MTE
> * Fix in_debug path in S1_ptw_translate
> * Don't set EXC_RETURN.ES if Security Extension not present
> * Implement DBGCLAIM registers
> * Provide stubs for more external debug registers
> * Look up ARMCPRegInfo at runtime, not translate time
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2023-01-23 13:35 Peter Maydell
2023-01-23 15:17 ` Peter Maydell
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2023-01-23 13:35 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 65cc5ccf06a74c98de73ec683d9a543baa302a12:
Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging (2023-01-20 16:17:56 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230123
for you to fetch changes up to 3b07a936d3bfe97b07ddffcfbb532985a88033dd:
target/arm: Look up ARMCPRegInfo at runtime (2023-01-23 13:32:38 +0000)
----------------------------------------------------------------
target-arm queue:
* Widen cnthctl_el2 to uint64_t
* Unify checking for M Main Extension in MRS/MSR
* bitbang_i2c, versatile_i2c: code cleanups
* SME: refactor SME SM/ZA handling
* Fix physical address resolution for MTE
* Fix in_debug path in S1_ptw_translate
* Don't set EXC_RETURN.ES if Security Extension not present
* Implement DBGCLAIM registers
* Provide stubs for more external debug registers
* Look up ARMCPRegInfo at runtime, not translate time
----------------------------------------------------------------
David Reiss (1):
target/arm: Unify checking for M Main Extension in MRS/MSR
Evgeny Iakovlev (2):
target/arm: implement DBGCLAIM registers
target/arm: provide stubs for more external debug registers
Peter Maydell (1):
target/arm: Don't set EXC_RETURN.ES if Security Extension not present
Philippe Mathieu-Daudé (10):
hw/i2c/bitbang_i2c: Define TYPE_GPIO_I2C in public header
hw/i2c/bitbang_i2c: Remove unused dummy MemoryRegion
hw/i2c/bitbang_i2c: Change state calling bitbang_i2c_set_state() helper
hw/i2c/bitbang_i2c: Trace state changes
hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events
hw/i2c/versatile_i2c: Drop useless casts from void * to pointer
hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C
hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro
hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c
Richard Henderson (12):
target/arm: Widen cnthctl_el2 to uint64_t
target/arm/sme: Reorg SME access handling in handle_msr_i()
target/arm/sme: Rebuild hflags in set_pstate() helpers
target/arm/sme: Introduce aarch64_set_svcr()
target/arm/sme: Reset SVE state in aarch64_set_svcr()
target/arm/sme: Reset ZA state in aarch64_set_svcr()
target/arm/sme: Rebuild hflags in aarch64_set_svcr()
target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr()
target/arm: Fix physical address resolution for MTE
target/arm: Fix in_debug path in S1_ptw_translate
target/arm: Reorg do_coproc_insn
target/arm: Look up ARMCPRegInfo at runtime
MAINTAINERS | 1 +
include/hw/i2c/arm_sbcon_i2c.h | 6 +-
include/hw/i2c/bitbang_i2c.h | 2 +
target/arm/cpu.h | 5 +-
target/arm/helper-sme.h | 3 +-
target/arm/helper.h | 11 +-
target/arm/translate.h | 7 +
hw/arm/musicpal.c | 3 +-
hw/arm/realview.c | 2 +-
hw/arm/versatilepb.c | 2 +-
hw/arm/vexpress.c | 2 +-
hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} | 39 ++-
hw/i2c/bitbang_i2c.c | 80 ++++--
linux-user/aarch64/cpu_loop.c | 11 +-
linux-user/aarch64/signal.c | 13 +-
target/arm/debug_helper.c | 54 ++++
target/arm/helper.c | 41 ++-
target/arm/m_helper.c | 24 +-
target/arm/mte_helper.c | 2 +-
target/arm/op_helper.c | 27 +-
target/arm/ptw.c | 4 +-
target/arm/sme_helper.c | 37 +--
target/arm/translate-a64.c | 68 +++--
target/arm/translate.c | 430 +++++++++++++++-------------
hw/arm/Kconfig | 4 +-
hw/i2c/Kconfig | 2 +-
hw/i2c/meson.build | 2 +-
hw/i2c/trace-events | 7 +
28 files changed, 506 insertions(+), 383 deletions(-)
rename hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} (70%)
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2022-03-02 20:52 Peter Maydell
@ 2022-03-03 19:57 ` Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2022-03-03 19:57 UTC (permalink / raw)
To: qemu-devel
On Wed, 2 Mar 2022 at 20:52, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
>
> Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302
>
> for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:
>
> ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * mps3-an547: Add missing user ahb interfaces
> * hw/arm/mps2-tz.c: Update AN547 documentation URL
> * hw/input/tsc210x: Don't abort on bad SPI word widths
> * hw/i2c: flatten pca954x mux device
> * target/arm: Support PSCI 1.1 and SMCCC 1.0
> * target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
> * tests/qtest: add qtests for npcm7xx sdhci
> * Implement FEAT_LVA
> * Implement FEAT_LPA
> * Implement FEAT_LPA2 (but do not enable it yet)
> * Report KVM's actual PSCI version to guest in dtb
> * ui/cocoa.m: Fix updateUIInfo threading issues
> * ui/cocoa.m: Remove unnecessary NSAutoreleasePools
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2022-03-02 20:52 Peter Maydell
2022-03-03 19:57 ` Peter Maydell
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2022-03-02 20:52 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302
for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:
ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)
----------------------------------------------------------------
target-arm queue:
* mps3-an547: Add missing user ahb interfaces
* hw/arm/mps2-tz.c: Update AN547 documentation URL
* hw/input/tsc210x: Don't abort on bad SPI word widths
* hw/i2c: flatten pca954x mux device
* target/arm: Support PSCI 1.1 and SMCCC 1.0
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
* tests/qtest: add qtests for npcm7xx sdhci
* Implement FEAT_LVA
* Implement FEAT_LPA
* Implement FEAT_LPA2 (but do not enable it yet)
* Report KVM's actual PSCI version to guest in dtb
* ui/cocoa.m: Fix updateUIInfo threading issues
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools
----------------------------------------------------------------
Akihiko Odaki (1):
target/arm: Support PSCI 1.1 and SMCCC 1.0
Jimmy Brisson (1):
mps3-an547: Add missing user ahb interfaces
Patrick Venture (1):
hw/i2c: flatten pca954x mux device
Peter Maydell (5):
hw/arm/mps2-tz.c: Update AN547 documentation URL
hw/input/tsc210x: Don't abort on bad SPI word widths
target/arm: Report KVM's actual PSCI version to guest in dtb
ui/cocoa.m: Fix updateUIInfo threading issues
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
Richard Henderson (16):
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
target/arm: Set TCR_EL1.TSZ for user-only
target/arm: Fault on invalid TCR_ELx.TxSZ
target/arm: Move arm_pamax out of line
target/arm: Pass outputsize down to check_s2_mmu_setup
target/arm: Use MAKE_64BIT_MASK to compute indexmask
target/arm: Honor TCR_ELx.{I}PS
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
target/arm: Implement FEAT_LVA
target/arm: Implement FEAT_LPA
target/arm: Extend arm_fi_to_lfsc to level -1
target/arm: Introduce tlbi_aa64_get_range
target/arm: Fix TLBIRange.base for 16k and 64k pages
target/arm: Validate tlbi TG matches translation granule in use
target/arm: Advertise all page sizes for -cpu max
target/arm: Implement FEAT_LPA2
Shengtan Mao (1):
tests/qtest: add qtests for npcm7xx sdhci
Wentao_Liang (1):
target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
docs/system/arm/emulation.rst | 3 +
include/hw/registerfields.h | 48 +++++-
target/arm/cpu-param.h | 4 +-
target/arm/cpu.h | 27 ++++
target/arm/internals.h | 58 ++++---
target/arm/kvm-consts.h | 14 +-
hw/arm/boot.c | 11 +-
hw/arm/mps2-tz.c | 6 +-
hw/i2c/i2c_mux_pca954x.c | 77 ++-------
hw/input/tsc210x.c | 8 +-
target/arm/cpu.c | 8 +-
target/arm/cpu64.c | 7 +-
target/arm/helper.c | 332 ++++++++++++++++++++++++++++++---------
target/arm/hvf/hvf.c | 27 +++-
target/arm/kvm64.c | 14 +-
target/arm/psci.c | 35 ++++-
target/arm/translate-a64.c | 2 +-
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
tests/qtest/meson.build | 1 +
ui/cocoa.m | 31 ++--
20 files changed, 736 insertions(+), 192 deletions(-)
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2022-02-21 9:27 Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2022-02-21 9:27 UTC (permalink / raw)
To: qemu-devel
The following changes since commit e670f6d825d4dee248b311197fd4048469d6772b:
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into staging (2022-02-20 15:05:41 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220221
for you to fetch changes up to d6333e2543fa41aed4d33f77c808168373e39bff:
ui/cocoa: Fix the leak of qemu_console_get_label (2022-02-21 09:12:18 +0000)
----------------------------------------------------------------
arm, cocoa and misc:
* MAINTAINERS file updates
* Mark remaining global TypeInfo instances as const
* checkpatch: Ensure that TypeInfos are const
* tests/qtest: add qtests for npcm7xx sdhci
* arm hvf: Handle unknown ID registers as RES0
* Make KVM -cpu max exactly like -cpu host
* Fix '-cpu max' for HVF
* Support PAuth extension for hvf
* Kconfig: Add I2C_DEVICES device group
* Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
* hw/arm/armv7m: Handle disconnected clock inputs
* osdep.h: pull out various things into new header files
* hw/timer: fix a9gtimer vmstate
* hw/arm: add initial mori-bmc board
* ui/cocoa: Remove allowedFileTypes restriction in SavePanel
* ui/cocoa: Do not alert even without block devices
* ui/cocoa: Fix the leak of qemu_console_get_label
----------------------------------------------------------------
Akihiko Odaki (3):
MAINTAINERS: Add Akihiko Odaki to macOS-relateds
ui/cocoa: Do not alert even without block devices
ui/cocoa: Fix the leak of qemu_console_get_label
Alexander Graf (2):
hvf: arm: Use macros for sysreg shift/masking
hvf: arm: Handle unknown ID registers as RES0
Ani Sinha (1):
MAINTAINERS: Adding myself as a reviewer of some components
Bernhard Beschow (2):
Mark remaining global TypeInfo instances as const
checkpatch: Ensure that TypeInfos are const
Patrick Venture (1):
hw/arm: add initial mori-bmc board
Pavel Dovgalyuk (1):
hw/timer: fix a9gtimer vmstate
Peter Maydell (14):
target/arm: Move '-cpu host' code to cpu64.c
target/arm: Use aarch64_cpu_register() for 'host' CPU type
target/arm: Make KVM -cpu max exactly like -cpu host
target/arm: Unindent unnecessary else-clause
target/arm: Fix '-cpu max' for HVF
target/arm: Support PAuth extension for hvf
Kconfig: Add I2C_DEVICES device group
Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
hw/arm/armv7m: Handle disconnected clock inputs
include: Move qemu_madvise() and related #defines to new qemu/madvise.h
include: Move qemu_mprotect_*() to new qemu/mprotect.h
include: Move QEMU_MAP_* constants to mmap-alloc.h
include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h
include: Move hardware version declarations to new qemu/hw-version.h
Philippe Mathieu-Daudé (1):
ui/cocoa: Remove allowedFileTypes restriction in SavePanel
Shengtan Mao (1):
tests/qtest: add qtests for npcm7xx sdhci
docs/devel/kconfig.rst | 8 +-
docs/system/arm/nuvoton.rst | 1 +
include/qemu/cacheinfo.h | 21 +++
include/qemu/hw-version.h | 27 ++++
include/qemu/madvise.h | 95 +++++++++++
include/qemu/mmap-alloc.h | 23 +++
include/qemu/mprotect.h | 14 ++
include/qemu/osdep.h | 132 ----------------
accel/tcg/translate-all.c | 1 +
backends/hostmem-file.c | 1 +
backends/hostmem.c | 1 +
hw/arm/armv7m.c | 26 ++-
hw/arm/npcm7xx_boards.c | 32 ++++
hw/arm/nseries.c | 1 +
hw/core/generic-loader.c | 2 +-
hw/core/guest-loader.c | 2 +-
hw/display/bcm2835_fb.c | 2 +-
hw/display/i2c-ddc.c | 2 +-
hw/display/macfb.c | 4 +-
hw/display/virtio-vga.c | 2 +-
hw/dma/bcm2835_dma.c | 2 +-
hw/i386/pc_piix.c | 2 +-
hw/i386/sgx-epc.c | 2 +-
hw/ide/core.c | 1 +
hw/intc/bcm2835_ic.c | 2 +-
hw/intc/bcm2836_control.c | 2 +-
hw/ipmi/ipmi.c | 4 +-
hw/mem/nvdimm.c | 2 +-
hw/mem/pc-dimm.c | 2 +-
hw/misc/bcm2835_mbox.c | 2 +-
hw/misc/bcm2835_powermgt.c | 2 +-
hw/misc/bcm2835_property.c | 2 +-
hw/misc/bcm2835_rng.c | 2 +-
hw/misc/pvpanic-isa.c | 2 +-
hw/misc/pvpanic-pci.c | 2 +-
hw/net/fsl_etsec/etsec.c | 2 +-
hw/ppc/prep_systemio.c | 2 +-
hw/ppc/spapr_iommu.c | 2 +-
hw/s390x/s390-pci-bus.c | 2 +-
hw/s390x/sclp.c | 2 +-
hw/s390x/tod-kvm.c | 2 +-
hw/s390x/tod-tcg.c | 2 +-
hw/s390x/tod.c | 2 +-
hw/scsi/lsi53c895a.c | 2 +-
hw/scsi/megasas.c | 1 +
hw/scsi/scsi-bus.c | 1 +
hw/scsi/scsi-disk.c | 1 +
hw/sd/allwinner-sdhost.c | 2 +-
hw/sd/aspeed_sdhci.c | 2 +-
hw/sd/bcm2835_sdhost.c | 2 +-
hw/sd/cadence_sdhci.c | 2 +-
hw/sd/npcm7xx_sdhci.c | 2 +-
hw/timer/a9gtimer.c | 21 +++
hw/usb/dev-mtp.c | 2 +-
hw/usb/host-libusb.c | 2 +-
hw/vfio/igd.c | 2 +-
hw/virtio/virtio-balloon.c | 1 +
hw/virtio/virtio-pmem.c | 2 +-
migration/postcopy-ram.c | 1 +
migration/qemu-file.c | 1 +
migration/ram.c | 1 +
plugins/loader.c | 1 +
qom/object.c | 4 +-
softmmu/physmem.c | 1 +
softmmu/vl.c | 1 +
target/arm/cpu.c | 30 ----
target/arm/cpu64.c | 331 +++++++++++++++++++++------------------
target/arm/hvf/hvf.c | 83 +++++++---
target/i386/cpu.c | 1 +
target/s390x/cpu_models.c | 1 +
tcg/region.c | 3 +
tcg/tcg.c | 1 +
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
util/atomic64.c | 1 +
util/cacheflush.c | 1 +
util/cacheinfo.c | 1 +
util/osdep.c | 3 +
util/oslib-posix.c | 1 +
MAINTAINERS | 5 +
hw/arm/Kconfig | 10 ++
hw/i2c/Kconfig | 5 +
hw/rtc/Kconfig | 2 +
hw/sensor/Kconfig | 5 +
scripts/checkpatch.pl | 1 +
tests/qtest/meson.build | 1 +
ui/cocoa.m | 15 +-
86 files changed, 822 insertions(+), 393 deletions(-)
create mode 100644 include/qemu/cacheinfo.h
create mode 100644 include/qemu/hw-version.h
create mode 100644 include/qemu/madvise.h
create mode 100644 include/qemu/mprotect.h
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2021-05-10 12:25 Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2021-05-10 12:25 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 4cc10cae64c51e17844dc4358481c393d7bf1ed4:
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-05-06 18:56:17 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210510
for you to fetch changes up to 8f96812baa53005f32aece3e30b140826c20aa19:
hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 (2021-05-10 13:24:09 +0100)
----------------------------------------------------------------
target-arm queue:
* docs: fix link in sbsa description
* linux-user/aarch64: Enable hwcap for RND, BTI, and MTE
* target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()
* target/arm: Split neon and vfp translation to their own
compilation units
* target/arm: Make WFI a NOP for userspace emulators
* hw/sd/omap_mmc: Use device_cold_reset() instead of
device_legacy_reset()
* include: More fixes for 'extern "C"' block use
* hw/arm/imx25_pdk: Fix error message for invalid RAM size
* hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
* hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9
----------------------------------------------------------------
Alex Bennée (1):
docs: fix link in sbsa description
Guenter Roeck (1):
hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9
Peter Maydell (22):
target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()
target/arm: Move constant expanders to translate.h
target/arm: Share unallocated_encoding() and gen_exception_insn()
target/arm: Make functions used by m-nocp global
target/arm: Split m-nocp trans functions into their own file
target/arm: Move gen_aa32 functions to translate-a32.h
target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc
target/arm: Make functions used by translate-vfp global
target/arm: Make translate-vfp.c.inc its own compilation unit
target/arm: Move vfp_reg_ptr() to translate-neon.c.inc
target/arm: Delete unused typedef
target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h
target/arm: Make functions used by translate-neon global
target/arm: Make translate-neon.c.inc its own compilation unit
target/arm: Make WFI a NOP for userspace emulators
hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset()
osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves
include/qemu/bswap.h: Handle being included outside extern "C" block
include/disas/dis-asm.h: Handle being included outside 'extern "C"'
hw/misc/mps2-scc: Add "QEMU interface" comment
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
Philippe Mathieu-Daudé (1):
hw/arm/imx25_pdk: Fix error message for invalid RAM size
Richard Henderson (1):
linux-user/aarch64: Enable hwcap for RND, BTI, and MTE
docs/system/arm/mps2.rst | 10 +
docs/system/arm/sbsa.rst | 2 +-
include/disas/dis-asm.h | 12 +-
include/hw/misc/mps2-scc.h | 21 ++
include/qemu/bswap.h | 26 ++-
include/qemu/osdep.h | 8 +-
include/sysemu/os-posix.h | 8 +
include/sysemu/os-win32.h | 8 +
target/arm/translate-a32.h | 144 +++++++++++++
target/arm/translate-a64.h | 2 -
target/arm/translate.h | 29 +++
hw/arm/imx25_pdk.c | 5 +-
hw/arm/mps2-tz.c | 108 +++++++++-
hw/arm/xilinx_zynq.c | 2 +-
hw/misc/mps2-scc.c | 13 +-
hw/sd/omap_mmc.c | 2 +-
linux-user/elfload.c | 13 ++
target/arm/helper.c | 2 +-
target/arm/op_helper.c | 12 ++
target/arm/translate-a64.c | 15 --
target/arm/translate-m-nocp.c | 221 ++++++++++++++++++++
.../arm/{translate-neon.c.inc => translate-neon.c} | 19 +-
.../arm/{translate-vfp.c.inc => translate-vfp.c} | 230 +++------------------
target/arm/translate.c | 200 ++++--------------
disas/arm-a64.cc | 2 -
disas/nanomips.cpp | 2 -
target/arm/meson.build | 15 +-
27 files changed, 718 insertions(+), 413 deletions(-)
create mode 100644 target/arm/translate-a32.h
create mode 100644 target/arm/translate-m-nocp.c
rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%)
rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (94%)
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PULL 00/26] target-arm queue
2020-11-02 17:09 Peter Maydell
@ 2020-11-03 11:36 ` Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2020-11-03 11:36 UTC (permalink / raw)
To: QEMU Developers
On Mon, 2 Nov 2020 at 17:10, Peter Maydell <peter.maydell@linaro.org> wrote:
>
>
> Small pile of bug fixes for rc1. I've included my patches to get
> our docs building with Sphinx 3, just for convenience...
>
> -- PMM
>
> The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
>
> Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
>
> for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
>
> tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * target/arm: Fix Neon emulation bugs on big-endian hosts
> * target/arm: fix handling of HCR.FB
> * target/arm: fix LORID_EL1 access check
> * disas/capstone: Fix monitor disassembly of >32 bytes
> * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
> * hw/arm/boot: fix SVE for EL3 direct kernel boot
> * hw/display/omap_lcdc: Fix potential NULL pointer dereference
> * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
> * target/arm: Get correct MMU index for other-security-state
> * configure: Test that gio libs from pkg-config work
> * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
> * docs: Fix building with Sphinx 3
> * tests/qtest/npcm7xx_rng-test: Disable randomness tests
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 00/26] target-arm queue
@ 2020-11-02 17:09 Peter Maydell
2020-11-03 11:36 ` Peter Maydell
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2020-11-02 17:09 UTC (permalink / raw)
To: qemu-devel
Small pile of bug fixes for rc1. I've included my patches to get
our docs building with Sphinx 3, just for convenience...
-- PMM
The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
----------------------------------------------------------------
target-arm queue:
* target/arm: Fix Neon emulation bugs on big-endian hosts
* target/arm: fix handling of HCR.FB
* target/arm: fix LORID_EL1 access check
* disas/capstone: Fix monitor disassembly of >32 bytes
* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
* hw/arm/boot: fix SVE for EL3 direct kernel boot
* hw/display/omap_lcdc: Fix potential NULL pointer dereference
* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
* target/arm: Get correct MMU index for other-security-state
* configure: Test that gio libs from pkg-config work
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
* docs: Fix building with Sphinx 3
* tests/qtest/npcm7xx_rng-test: Disable randomness tests
----------------------------------------------------------------
AlexChen (2):
hw/display/omap_lcdc: Fix potential NULL pointer dereference
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
Peter Maydell (9):
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
disas/capstone: Fix monitor disassembly of >32 bytes
target/arm: Get correct MMU index for other-security-state
configure: Test that gio libs from pkg-config work
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
qemu-option-trace.rst.inc: Don't use option:: markup
tests/qtest/npcm7xx_rng-test: Disable randomness tests
Philippe Mathieu-Daudé (1):
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
Richard Henderson (11):
target/arm: Introduce neon_full_reg_offset
target/arm: Move neon_element_offset to translate.c
target/arm: Use neon_element_offset in neon_load/store_reg
target/arm: Use neon_element_offset in vfp_reg_offset
target/arm: Add read/write_neon_element32
target/arm: Expand read/write_neon_element32 to all MemOp
target/arm: Rename neon_load_reg32 to vfp_load_reg32
target/arm: Add read/write_neon_element64
target/arm: Rename neon_load_reg64 to vfp_load_reg64
target/arm: Simplify do_long_3d and do_2scalar_long
target/arm: Improve do_prewiden_3d
Rémi Denis-Courmont (3):
target/arm: fix handling of HCR.FB
target/arm: fix LORID_EL1 access check
hw/arm/boot: fix SVE for EL3 direct kernel boot
docs/qemu-option-trace.rst.inc | 6 +-
configure | 10 +-
include/hw/intc/arm_gicv3_common.h | 1 -
disas/capstone.c | 2 +-
hw/arm/boot.c | 3 +
hw/arm/smmuv3.c | 3 +-
hw/display/exynos4210_fimd.c | 4 +-
hw/display/omap_lcdc.c | 10 +-
hw/intc/arm_gicv3_cpuif.c | 5 +-
target/arm/helper.c | 24 +-
target/arm/m_helper.c | 3 +-
target/arm/translate.c | 153 +++++++++---
target/arm/vec_helper.c | 12 +-
tests/qtest/npcm7xx_rng-test.c | 14 +-
scripts/kernel-doc | 18 +-
target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++-----------------
target/arm/translate-vfp.c.inc | 341 +++++++++++----------------
17 files changed, 588 insertions(+), 493 deletions(-)
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2023-09-11 15:20 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-30 16:15 [PULL 00/26] target-arm queue Peter Maydell
2020-01-30 16:15 ` [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES Peter Maydell
2020-01-30 16:15 ` [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr Peter Maydell
2020-01-30 16:15 ` [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Peter Maydell
2020-01-30 16:15 ` [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller Peter Maydell
2020-01-30 16:15 ` [PULL 05/26] ftgmac100: check RX and TX buffer alignment Peter Maydell
2020-01-30 16:15 ` [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 Peter Maydell
2020-01-30 16:15 ` [PULL 07/26] misc/pca9552: Add qom set and get Peter Maydell
2020-01-30 16:15 ` [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' Peter Maydell
2020-01-30 16:15 ` [PULL 09/26] add device_legacy_reset function to prepare for reset api change Peter Maydell
2020-01-30 16:15 ` [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition Peter Maydell
2020-01-30 16:15 ` [PULL 11/26] hw/core: create Resettable QOM interface Peter Maydell
2020-01-30 16:15 ` [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass Peter Maydell
2020-01-30 16:15 ` [PULL 13/26] hw/core/resettable: add support for changing parent Peter Maydell
2020-01-30 16:15 ` [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable Peter Maydell
2020-01-30 16:15 ` [PULL 15/26] hw/core/qdev: update hotplug reset " Peter Maydell
2020-01-30 16:15 ` [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones Peter Maydell
2020-01-30 16:15 ` [PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface Peter Maydell
2020-01-30 16:15 ` [PULL 18/26] vl: replace deprecated qbus_reset_all registration Peter Maydell
2020-01-30 16:15 ` [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration Peter Maydell
2020-01-30 16:15 ` [PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit Peter Maydell
2020-01-30 16:15 ` [PULL 21/26] target/arm/kvm: trivial: Clean up header documentation Peter Maydell
2020-01-30 16:15 ` [PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options Peter Maydell
2020-01-30 16:15 ` [PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers Peter Maydell
2020-01-30 16:15 ` [PULL 24/26] tests/arm-cpu-features: Check feature default values Peter Maydell
2020-01-30 16:15 ` [PULL 25/26] target/arm/kvm: Implement virtual time adjustment Peter Maydell
2020-01-30 16:15 ` [PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property Peter Maydell
2020-01-30 19:05 ` [PULL 00/26] target-arm queue Peter Maydell
2020-11-02 17:09 Peter Maydell
2020-11-03 11:36 ` Peter Maydell
2021-05-10 12:25 Peter Maydell
2022-02-21 9:27 Peter Maydell
2022-03-02 20:52 Peter Maydell
2022-03-03 19:57 ` Peter Maydell
2023-01-23 13:35 Peter Maydell
2023-01-23 15:17 ` Peter Maydell
2023-06-23 12:31 Peter Maydell
2023-06-25 8:25 ` Richard Henderson
2023-09-08 17:05 Peter Maydell
2023-09-11 15:19 ` Stefan Hajnoczi
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