From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PULL 00/11] target-arm queue
Date: Thu, 6 Jul 2023 12:35:06 +0100 [thread overview]
Message-ID: <CAFEAcA_dKacrOG+rTO2jfo=jkTg4e8CjdumsLa+PjPHRJA_+bg@mail.gmail.com> (raw)
In-Reply-To: <d73e2121-ee38-3245-8a3b-804931ea80a2@linaro.org>
On Wed, 5 Jul 2023 at 06:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/5/23 06:57, Richard Henderson wrote:
> > https://gitlab.com/qemu-project/qemu/-/jobs/4592433432#L3723
> >
> >> /tmp/ccASXpLo.s: Assembler messages:
> >> /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name
> >> 'id_aa64zfr0_el1'
> >> /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name
> >> 'id_aa64smfr0_el1'
> >> make[1]: *** [Makefile:119: sysregs] Error 1
> >
> > I guess it's the change to Makefile.target, as I don't see any other likely candidates.
>
> Ho hum, that's *my* patch 5, "Fix SME full tile indexing".
> I'll have a closer look tomorrow. Sorry about that.
I think we can fix this by using the S3_.... syntax
instead, and we can drop the #ifdef HAS_ARMV9_SME entirely:
these registers are in the ID register space so they will
read-as-zero and pass the test regardless of guest CPU type.
However, it doesn't look like I can run this CI job under
my personal gitlab account, so I'll have to do a blind
attempt at a fix and resubmit the pullreq for you to see...
thanks
-- PMM
next prev parent reply other threads:[~2023-07-06 11:35 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 16:36 [PULL 00/11] target-arm queue Peter Maydell
2023-07-04 16:36 ` [PULL 01/11] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Peter Maydell
2023-07-04 16:36 ` [PULL 02/11] hw/arm/sbsa-ref: use XHCI to replace EHCI Peter Maydell
2023-07-04 16:36 ` [PULL 03/11] target/arm: Avoid splitting Zregs across lines in dump Peter Maydell
2023-07-04 16:36 ` [PULL 04/11] target/arm: Dump ZA[] when active Peter Maydell
2023-07-04 16:36 ` [PULL 05/11] target/arm: Fix SME full tile indexing Peter Maydell
2023-07-04 16:36 ` [PULL 06/11] target/arm: Handle IC IVAU to improve compatibility with JITs Peter Maydell
2023-07-04 16:36 ` [PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code Peter Maydell
2023-07-05 4:53 ` Richard Henderson
2023-07-05 9:25 ` Philippe Mathieu-Daudé
2023-07-05 13:36 ` Richard Henderson
2023-07-06 12:26 ` Peter Maydell
2023-07-06 12:45 ` John Högberg
2023-07-06 12:54 ` Peter Maydell
2023-07-07 7:50 ` John Högberg
2023-07-04 16:36 ` [PULL 08/11] tests/qtest: xlnx-canfd-test: Fix code coverity issues Peter Maydell
2023-07-04 16:36 ` [PULL 09/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Peter Maydell
2023-07-04 16:36 ` [PULL 10/11] hw: arm: allwinner-sramc: Set class_size Peter Maydell
2023-07-04 16:36 ` [PULL 11/11] target/xtensa: Assert that interrupt level is within bounds Peter Maydell
2023-07-05 4:57 ` [PULL 00/11] target-arm queue Richard Henderson
2023-07-05 5:04 ` Richard Henderson
2023-07-06 11:35 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-04-06 10:11 Peter Maydell
2020-04-06 12:52 ` Peter Maydell
2020-03-17 11:40 Peter Maydell
2020-03-17 16:21 ` Peter Maydell
2019-11-01 8:51 Peter Maydell
2019-11-01 9:30 ` Peter Maydell
2019-11-01 9:54 ` Andrew Jones
2019-11-01 10:34 ` Peter Maydell
2019-11-01 12:53 ` Peter Maydell
2019-11-01 14:25 ` Andrew Jones
2019-11-02 17:57 ` Peter Maydell
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