From: Alistair Francis <alistair23@gmail.com>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Bin Meng" <bin.meng@windriver.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v5 08/18] target/riscv: moving some insns close to similar insns
Date: Tue, 23 Nov 2021 16:10:52 +1000 [thread overview]
Message-ID: <CAKmqyKM5-8uO55J6nNewRS9OwzQc7bWxDW+iXeih5egEe9rq1w@mail.gmail.com> (raw)
In-Reply-To: <20211112145902.205131-9-frederic.petrot@univ-grenoble-alpes.fr>
On Sat, Nov 13, 2021 at 1:17 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> lwu and ld are functionally close to the other loads, but were after the
> stores in the source file.
> Similarly, xor was away from or and and by two arithmetic functions, while
> the immediate versions were nicely put together.
> This patch moves the aforementioned loads after lhu, and xor above or,
> where they more logically belong.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
> meson | 2 +-
> 2 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 51607b3d40..710f5e6a85 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -176,6 +176,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
> return gen_load(ctx, a, MO_TEUW);
> }
>
> +static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
> +{
> + REQUIRE_64BIT(ctx);
> + return gen_load(ctx, a, MO_TEUL);
> +}
> +
> +static bool trans_ld(DisasContext *ctx, arg_ld *a)
> +{
> + REQUIRE_64BIT(ctx);
> + return gen_load(ctx, a, MO_TEUQ);
> +}
> +
> static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
> {
> TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
> return gen_store(ctx, a, MO_TESL);
> }
>
> -static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
> -{
> - REQUIRE_64BIT(ctx);
> - return gen_load(ctx, a, MO_TEUL);
> -}
> -
> -static bool trans_ld(DisasContext *ctx, arg_ld *a)
> -{
> - REQUIRE_64BIT(ctx);
> - return gen_load(ctx, a, MO_TEUQ);
> -}
> -
> static bool trans_sd(DisasContext *ctx, arg_sd *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -317,11 +317,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
> return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
> }
>
> -static bool trans_xor(DisasContext *ctx, arg_xor *a)
> -{
> - return gen_logic(ctx, a, tcg_gen_xor_tl);
> -}
> -
> static bool trans_srl(DisasContext *ctx, arg_srl *a)
> {
> return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
> @@ -332,6 +327,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
> }
>
> +static bool trans_xor(DisasContext *ctx, arg_xor *a)
> +{
> + return gen_logic(ctx, a, tcg_gen_xor_tl);
> +}
> +
> static bool trans_or(DisasContext *ctx, arg_or *a)
> {
> return gen_logic(ctx, a, tcg_gen_or_tl);
> diff --git a/meson b/meson
> index 12f9f04ba0..b25d94e7c7 160000
> --- a/meson
> +++ b/meson
> @@ -1 +1 @@
> -Subproject commit 12f9f04ba0decfda425dbbf9a501084c153a2d18
> +Subproject commit b25d94e7c77fda05a7fdfe8afe562cf9760d69da
This shouldn't be here
Alistair
> --
> 2.33.1
>
>
next prev parent reply other threads:[~2021-11-23 6:18 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 14:58 [PATCH v5 00/18] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions Frédéric Pétrot
2021-11-14 12:49 ` Richard Henderson
2021-11-12 14:58 ` [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines Frédéric Pétrot
2021-11-15 8:01 ` Richard Henderson
2021-11-22 5:24 ` Alistair Francis
2021-11-24 7:22 ` Philippe Mathieu-Daudé
2021-11-12 14:58 ` [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations Frédéric Pétrot
2021-11-23 6:04 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 04/18] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-11-23 6:11 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers Frédéric Pétrot
2021-11-23 6:07 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-11-23 6:09 ` Alistair Francis
2021-11-23 10:58 ` Frédéric Pétrot
2021-11-23 11:09 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-11-24 6:12 ` Alistair Francis
2021-11-24 6:55 ` Frédéric Pétrot
2021-11-24 7:33 ` Philippe Mathieu-Daudé
2021-11-25 11:47 ` Alistair Francis
2021-11-25 14:44 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 08/18] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-11-23 6:10 ` Alistair Francis [this message]
2021-11-12 14:58 ` [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot
2021-11-15 8:29 ` Richard Henderson
2021-11-16 16:08 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-11-15 8:30 ` Richard Henderson
2021-11-24 6:13 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-11-24 6:21 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 14/18] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 15/18] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-11-24 6:22 ` Alistair Francis
2021-11-12 14:59 ` [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
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