From: Alistair Francis <alistair23@gmail.com>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Bin Meng" <bin.meng@windriver.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v5 04/18] target/riscv: additional macros to check instruction support
Date: Tue, 23 Nov 2021 16:11:38 +1000 [thread overview]
Message-ID: <CAKmqyKMOQ-QE0BATfiQyW9gR69TJkmem3y0HbxB+uOktUNxNAA@mail.gmail.com> (raw)
In-Reply-To: <20211112145902.205131-5-frederic.petrot@univ-grenoble-alpes.fr>
On Sat, Nov 13, 2021 at 1:08 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> Given that the 128-bit version of the riscv spec adds new instructions, and
> that some instructions that were previously only available in 64-bit mode
> are now available for both 64-bit and 128-bit, we added new macros to check
> for the processor mode during translation.
> Although RV128 is a superset of RV64, we keep for now the RV64 only tests
> for extensions other than RVI and RVM.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1d57bc97b5..d98bde9b6b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -368,10 +368,22 @@ EX_SH(12)
> } \
> } while (0)
>
> -#define REQUIRE_64BIT(ctx) do { \
> - if (get_xl(ctx) < MXL_RV64) { \
> - return false; \
> - } \
> +#define REQUIRE_64BIT(ctx) do { \
> + if (get_xl(ctx) != MXL_RV64) { \
> + return false; \
> + } \
> +} while (0)
> +
> +#define REQUIRE_128BIT(ctx) do { \
> + if (get_xl(ctx) != MXL_RV128) { \
> + return false; \
> + } \
> +} while (0)
> +
> +#define REQUIRE_64_OR_128BIT(ctx) do { \
> + if (get_xl(ctx) == MXL_RV32) { \
> + return false; \
> + } \
> } while (0)
>
> static int ex_rvc_register(DisasContext *ctx, int reg)
> --
> 2.33.1
>
>
next prev parent reply other threads:[~2021-11-23 6:22 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 14:58 [PATCH v5 00/18] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions Frédéric Pétrot
2021-11-14 12:49 ` Richard Henderson
2021-11-12 14:58 ` [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines Frédéric Pétrot
2021-11-15 8:01 ` Richard Henderson
2021-11-22 5:24 ` Alistair Francis
2021-11-24 7:22 ` Philippe Mathieu-Daudé
2021-11-12 14:58 ` [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations Frédéric Pétrot
2021-11-23 6:04 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 04/18] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-11-23 6:11 ` Alistair Francis [this message]
2021-11-12 14:58 ` [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers Frédéric Pétrot
2021-11-23 6:07 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-11-23 6:09 ` Alistair Francis
2021-11-23 10:58 ` Frédéric Pétrot
2021-11-23 11:09 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-11-24 6:12 ` Alistair Francis
2021-11-24 6:55 ` Frédéric Pétrot
2021-11-24 7:33 ` Philippe Mathieu-Daudé
2021-11-25 11:47 ` Alistair Francis
2021-11-25 14:44 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 08/18] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-11-23 6:10 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot
2021-11-15 8:29 ` Richard Henderson
2021-11-16 16:08 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-11-15 8:30 ` Richard Henderson
2021-11-24 6:13 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-11-24 6:21 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 14/18] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 15/18] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-11-24 6:22 ` Alistair Francis
2021-11-12 14:59 ` [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
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