Re: [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions

[Alistair Francis <alistair23@gmail.com>]

On Sat, Nov 13, 2021 at 1:12 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> Adding the 128-bit version of lui and auipc, and introducing to that end
> a "set register with immediate" function to handle extension on 128 bits.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c                | 21 +++++++++++++++++++++
>  target/riscv/insn_trans/trans_rvi.c.inc |  8 ++++----
>  2 files changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 508ae87985..d2a2f1021d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -289,6 +289,27 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
>      }
>  }
>
> +static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
> +{
> +    if (reg_num != 0) {
> +        switch (get_ol(ctx)) {
> +        case MXL_RV32:
> +            tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
> +            break;
> +        case MXL_RV64:
> +        case MXL_RV128:
> +            tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
> +            break;
> +        default:
> +            g_assert_not_reached();
> +        }
> +
> +        if (get_xl_max(ctx) == MXL_RV128) {
> +            tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
> +        }
> +    }
> +}
> +
>  static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
>  {
>      assert(get_ol(ctx) == MXL_RV128);
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index fc73735b9e..0070fe606a 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -26,14 +26,14 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
>
>  static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
>  {
> -     REQUIRE_64BIT(ctx);
> -     return trans_illegal(ctx, a);
> +    REQUIRE_64_OR_128BIT(ctx);
> +    return trans_illegal(ctx, a);
>  }
>
>  static bool trans_lui(DisasContext *ctx, arg_lui *a)
>  {
>      if (a->rd != 0) {
> -        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
> +        gen_set_gpri(ctx, a->rd, a->imm);
>      }
>      return true;
>  }
> @@ -41,7 +41,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
>  static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
>  {
>      if (a->rd != 0) {
> -        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
> +        gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
>      }
>      return true;
>  }
> --
> 2.33.1
>
>