From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
Date: Thu, 22 Apr 2021 12:01:50 +1000 [thread overview]
Message-ID: <CAKmqyKPTB0+8fy5p3VwyZ7ke6cv4N8s-O7oOHKNkU+JSJV9T5g@mail.gmail.com> (raw)
In-Reply-To: <77d3d314-a03e-e081-04c0-a22447fd2658@linaro.org>
On Wed, Apr 14, 2021 at 1:42 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/13/21 4:34 PM, Alistair Francis wrote:
> > -#ifndef CONFIG_USER_ONLY
> > -# ifdef TARGET_RISCV32
> > -# define is_32bit(ctx) true
> > -# else
> > +#ifdef TARGET_RISCV32
> > +# define is_32bit(ctx) true
> > +#else
> > static inline bool is_32bit(DisasContext *ctx)
> > {
> > - return !(ctx->misa & RV64);
> > + return (ctx->misa & RV32) == RV32;
>
> Why the change here? Also note the previous comment about fixing this to false
> for TARGET_RISCV64 && CONFIG_USER_ONLY.
Whoops, I squashed this in to the original patch.
>
> > static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
> > {
> > REQUIRE_FPU;
> > REQUIRE_EXT(ctx, RVD);
> > + REQUIRE_64BIT(ctx);
>
> I think you should always put the 64-bit check first.
> That way, on TARGET_RISCV32, the entire function folds away.
Fixed
>
> >
> > - TCGv t0 = tcg_temp_new();
> > + TCGv_i64 t0 = tcg_temp_new_i64();
> > gen_set_rm(ctx, a->rm);
> > gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
> > - gen_set_gpr(a->rd, t0);
> > - tcg_temp_free(t0);
> > + gen_set_gpr(a->rd, (TCGv) t0);
>
> So... I really don't like the cast.
>
> This is fixable one of two ways.
> (1) Change the real helper to use target_ulong.
> (2) Use the gen_helper_* stubs that I talked about in reply to v1.
>
> > @@ -390,8 +390,9 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
> > {
> > REQUIRE_FPU;
> > REQUIRE_EXT(ctx, RVD);
> > + REQUIRE_64BIT(ctx);
> >
> > - gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
> > + gen_set_gpr(a->rd, (TCGv) cpu_fpr[a->rs1]);
>
> This one's different, and might be worth
>
> #ifdef TARGET_RISCV64
> gen_set_gpr
> #else
> qemu_build_not_reached
> #endif
I have changed the helpers to use target_ulong
>
> > +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> > @@ -303,11 +303,11 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
> >
> > TCGv t0 = tcg_temp_new();
> >
> > -#if defined(TARGET_RISCV64)
> > - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
> > -#else
> > - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
> > -#endif
> > + if (!is_32bit(ctx)) {
> > + tcg_gen_ext32s_tl((TCGv) t0, (TCGv) cpu_fpr[a->rs1]);
> > + } else {
> > + tcg_gen_extrl_i64_i32((TCGv_i32) t0, cpu_fpr[a->rs1]);
> > + }
>
> I think you should leave this ifdef alone. The ifdef has determined the size
> of target_ulong and thus the size of TCGv, and thus the correct move to use.
>
> If TARGET_RISCV64 and is_32bit, the high bits are ignored; the fact that they
> happen to be copies of the sign bit is irrelevant.
Dropped.
Alistair
>
>
> r~
next prev parent reply other threads:[~2021-04-22 2:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-13 23:32 [PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-13 23:33 ` [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-14 3:13 ` Richard Henderson
2021-04-13 23:34 ` [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-14 3:14 ` Richard Henderson
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-04-14 3:42 ` Richard Henderson
2021-04-22 2:01 ` Alistair Francis [this message]
2021-04-13 23:34 ` [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-04-14 3:57 ` Richard Henderson
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