From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
Date: Tue, 13 Apr 2021 20:14:32 -0700 [thread overview]
Message-ID: <ec8a710c-c38a-ca35-7f44-1caffd1987c2@linaro.org> (raw)
In-Reply-To: <ef02611060de1a918f148fef5773a68d336afc16.1618356725.git.alistair.francis@wdc.com>
On 4/13/21 4:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 11 -----------
> target/riscv/cpu_helper.c | 24 ++++++++++++++++++------
> target/riscv/csr.c | 20 ++++++++++++++++----
> target/riscv/monitor.c | 22 +++++++++++++++++-----
> 4 files changed, 51 insertions(+), 26 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-04-14 3:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-13 23:32 [PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-13 23:33 ` [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-14 7:59 ` Bin Meng
2021-04-13 23:33 ` [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-14 3:13 ` Richard Henderson
2021-04-13 23:34 ` [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-14 3:14 ` Richard Henderson [this message]
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-14 8:00 ` Bin Meng
2021-04-13 23:34 ` [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-04-14 3:42 ` Richard Henderson
2021-04-22 2:01 ` Alistair Francis
2021-04-13 23:34 ` [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-04-14 3:57 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ec8a710c-c38a-ca35-7f44-1caffd1987c2@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).