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From: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: "thuth@redhat.com" <thuth@redhat.com>,
	"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"dovgaluk@ispras.ru" <dovgaluk@ispras.ru>,
	"imammedo@redhat.com" <imammedo@redhat.com>,
	Michael Rolnik <mrolnik@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
Date: Fri, 11 Oct 2019 17:54:51 +0200
Message-ID: <CAL1e-=h1PV6djRgWXikjnU79Ca7Pjfw9=0u9__Nz00FJ4R49Hg@mail.gmail.com> (raw)
In-Reply-To: <949009b8-58ec-4a9e-cfd7-7d4611fad380@redhat.com>

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On Friday, October 11, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Hi Michael,
>
> On 9/2/19 4:01 PM, Michael Rolnik wrote:
>
>> This series of patches adds 8bit AVR cores to QEMU.
>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
>> tested yet.
>> However I was able to execute simple code with functions. e.g fibonacci
>> calculation.
>> This series of patches include a non real, sample board.
>> No fuses support yet. PC is set to 0 at reset.
>>
>> the patches include the following
>> 1. just a basic 8bit AVR CPU, without instruction decoding or translation
>> 2. CPU features which allow define the following 8bit AVR cores
>>       avr1
>>       avr2 avr25
>>       avr3 avr31 avr35
>>       avr4
>>       avr5 avr51
>>       avr6
>>       xmega2 xmega4 xmega5 xmega6 xmega7
>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows
>> to execute simple code
>> 4. encoding for all AVR instructions
>> 5. interrupt handling
>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
>> 7. a decoder which given an opcode decides what istruction it is
>> 8. translation of AVR instruction into TCG
>> 9. all features together
>>
>> [..]
>
>> Michael Rolnik (7):
>>    target/avr: Add outward facing interfaces and core CPU logic
>>    target/avr: Add instruction helpers
>>    target/avr: Add instruction decoding
>>    target/avr: Add instruction translation
>>    target/avr: Add example board configuration
>>    target/avr: Register AVR support with the rest of QEMU, the build
>>      system, and the MAINTAINERS file
>>    target/avr: Add tests
>>
>> Sarah Harris (1):
>>    target/avr: Add limited support for USART and 16 bit timer peripherals
>>
>
> Overall architecture patches look good, but I'd like some more time to
> review the hardware patches. Unfortunately I won't have time until November.
> There was a chat on IRC about your series,


>
>
I don't see the reason why do you initiate IRC communication on this topic,
if we have the mailing list for discussing such important issues as
introducing a new target (that should be definitely visible to all
participants).

Thanks, Aleksandar



>
>
>

> I suggested Richard we could merge patches 1-4 and 7. They are almost
> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS
> ones).
>
> Regards,
>
> Phil.
>
>

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<br><br>On Friday, October 11, 2019, Philippe Mathieu-Daudé &lt;<a href="mailto:philmd@redhat.com">philmd@redhat.com</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Michael,<br>
<br>
On 9/2/19 4:01 PM, Michael Rolnik wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
This series of patches adds 8bit AVR cores to QEMU.<br>
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet.<br>
However I was able to execute simple code with functions. e.g fibonacci calculation.<br>
This series of patches include a non real, sample board.<br>
No fuses support yet. PC is set to 0 at reset.<br>
<br>
the patches include the following<br>
1. just a basic 8bit AVR CPU, without instruction decoding or translation<br>
2. CPU features which allow define the following 8bit AVR cores<br>
      avr1<br>
      avr2 avr25<br>
      avr3 avr31 avr35<br>
      avr4<br>
      avr5 avr51<br>
      avr6<br>
      xmega2 xmega4 xmega5 xmega6 xmega7<br>
3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code<br>
4. encoding for all AVR instructions<br>
5. interrupt handling<br>
6. helpers for IN, OUT, SLEEP, WBR &amp; unsupported instructions<br>
7. a decoder which given an opcode decides what istruction it is<br>
8. translation of AVR instruction into TCG<br>
9. all features together<br>
<br>
</blockquote>
[..]<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Michael Rolnik (7):<br>
   target/avr: Add outward facing interfaces and core CPU logic<br>
   target/avr: Add instruction helpers<br>
   target/avr: Add instruction decoding<br>
   target/avr: Add instruction translation<br>
   target/avr: Add example board configuration<br>
   target/avr: Register AVR support with the rest of QEMU, the build<br>
     system, and the MAINTAINERS file<br>
   target/avr: Add tests<br>
<br>
Sarah Harris (1):<br>
   target/avr: Add limited support for USART and 16 bit timer peripherals<br>
</blockquote>
<br>
Overall architecture patches look good, but I&#39;d like some more time to review the hardware patches. Unfortunately I won&#39;t have time until November.<br>
There was a chat on IRC about your series, </blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><div><br></div><div>I don&#39;t see the reason why do you initiate IRC communication on this topic, if we have the mailing list for discussing such important issues as introducing a new target (that should be definitely visible to all participants).</div><div><br></div><div>Thanks, Aleksandar</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I suggested Richard we could merge patches 1-4 and 7. They are almost sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS ones).<br>
<br>
Regards,<br>
<br>
Phil.<br>
<br>
</blockquote>

  reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-02 14:01 Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
2019-10-11 14:13   ` Aleksandar Markovic
2019-10-12 16:33     ` Michael Rolnik
2019-10-12 17:47       ` Aleksandar Markovic
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
2019-10-11 14:20   ` Eric Blake
2019-10-11 15:25   ` Philippe Mathieu-Daudé
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests Michael Rolnik
2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
2019-10-11 15:54   ` Aleksandar Markovic [this message]
2019-10-11 16:11     ` [Qemu-devel] " Alex Bennée
2019-10-11 21:15       ` Aleksandar Markovic
2019-10-11 15:41 ` Philippe Mathieu-Daudé

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