* [PATCH] target/mips: add gdb xml files @ 2019-10-07 7:41 Mikhail Abakumov 2019-10-07 15:46 ` Alex Bennée 0 siblings, 1 reply; 5+ messages in thread From: Mikhail Abakumov @ 2019-10-07 7:41 UTC (permalink / raw) To: Qemu Devel; +Cc: arikalo, philmd, alex.bennee, amarkovic, aurelien From: Mikhail Abakumov <mikhail.abakumov@ispras> This patch add xml files with gdb registers for mips. Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras> --- configure | 3 ++ gdb-xml/mips-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ gdb-xml/mips64-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ target/mips/cpu.c | 11 ++++++ 4 files changed, 182 insertions(+) create mode 100644 gdb-xml/mips-core.xml create mode 100644 gdb-xml/mips64-core.xml diff --git a/configure b/configure index 8f8446f52b..5bb2c62194 100755 --- a/configure +++ b/configure @@ -7466,12 +7466,14 @@ case "$target_name" in mips|mipsel) mttcg="yes" TARGET_ARCH=mips + gdb_xml_files="mips-core.xml" echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak ;; mipsn32|mipsn32el) mttcg="yes" TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips + gdb_xml_files="mips64-core.xml" echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak echo "TARGET_ABI32=y" >> $config_target_mak ;; @@ -7479,6 +7481,7 @@ case "$target_name" in mttcg="yes" TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips + gdb_xml_files="mips64-core.xml" echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak ;; moxie) diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml new file mode 100644 index 0000000000..a46b2993eb --- /dev/null +++ b/gdb-xml/mips-core.xml @@ -0,0 +1,84 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.mips"> + <reg name="zero" bitsize="32"/> + <reg name="at" bitsize="32"/> + <reg name="v0" bitsize="32"/> + <reg name="v1" bitsize="32"/> + <reg name="a0" bitsize="32"/> + <reg name="a1" bitsize="32"/> + <reg name="a2" bitsize="32"/> + <reg name="a3" bitsize="32"/> + <reg name="t0" bitsize="32"/> + <reg name="t1" bitsize="32"/> + <reg name="t2" bitsize="32"/> + <reg name="t3" bitsize="32"/> + <reg name="t4" bitsize="32"/> + <reg name="t5" bitsize="32"/> + <reg name="t6" bitsize="32"/> + <reg name="t7" bitsize="32"/> + <reg name="s0" bitsize="32"/> + <reg name="s1" bitsize="32"/> + <reg name="s2" bitsize="32"/> + <reg name="s3" bitsize="32"/> + <reg name="s4" bitsize="32"/> + <reg name="s5" bitsize="32"/> + <reg name="s6" bitsize="32"/> + <reg name="s7" bitsize="32"/> + <reg name="t8" bitsize="32"/> + <reg name="t9" bitsize="32"/> + <reg name="k0" bitsize="32"/> + <reg name="k1" bitsize="32"/> + <reg name="gp" bitsize="32"/> + <reg name="sp" bitsize="32"/> + <reg name="s8" bitsize="32"/> + <reg name="ra" bitsize="32"/> + <reg name="sr" bitsize="32"/> + <reg name="lo" bitsize="32"/> + <reg name="hi" bitsize="32"/> + <reg name="bad" bitsize="32"/> + <reg name="cause" bitsize="32"/> + <reg name="pc" bitsize="32"/> + + <reg name="f0" bitsize="32" regnum="38"/> + <reg name="f1" bitsize="32"/> + <reg name="f2" bitsize="32"/> + <reg name="f3" bitsize="32"/> + <reg name="f4" bitsize="32"/> + <reg name="f5" bitsize="32"/> + <reg name="f6" bitsize="32"/> + <reg name="f7" bitsize="32"/> + <reg name="f8" bitsize="32"/> + <reg name="f9" bitsize="32"/> + <reg name="f10" bitsize="32"/> + <reg name="f11" bitsize="32"/> + <reg name="f12" bitsize="32"/> + <reg name="f13" bitsize="32"/> + <reg name="f14" bitsize="32"/> + <reg name="f15" bitsize="32"/> + <reg name="f16" bitsize="32"/> + <reg name="f17" bitsize="32"/> + <reg name="f18" bitsize="32"/> + <reg name="f19" bitsize="32"/> + <reg name="f20" bitsize="32"/> + <reg name="f21" bitsize="32"/> + <reg name="f22" bitsize="32"/> + <reg name="f23" bitsize="32"/> + <reg name="f24" bitsize="32"/> + <reg name="f25" bitsize="32"/> + <reg name="f26" bitsize="32"/> + <reg name="f27" bitsize="32"/> + <reg name="f28" bitsize="32"/> + <reg name="f29" bitsize="32"/> + <reg name="f30" bitsize="32"/> + <reg name="f31" bitsize="32"/> + <reg name="fsr" bitsize="32" group="float"/> + <reg name="fir" bitsize="32" group="float"/> + <reg name="fp" bitsize="32" group="float"/> +</feature> diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml new file mode 100644 index 0000000000..cc1a15ad56 --- /dev/null +++ b/gdb-xml/mips64-core.xml @@ -0,0 +1,84 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.mips64"> + <reg name="zero" bitsize="64"/> + <reg name="at" bitsize="64"/> + <reg name="v0" bitsize="64"/> + <reg name="v1" bitsize="64"/> + <reg name="a0" bitsize="64"/> + <reg name="a1" bitsize="64"/> + <reg name="a2" bitsize="64"/> + <reg name="a3" bitsize="64"/> + <reg name="t0" bitsize="64"/> + <reg name="t1" bitsize="64"/> + <reg name="t2" bitsize="64"/> + <reg name="t3" bitsize="64"/> + <reg name="t4" bitsize="64"/> + <reg name="t5" bitsize="64"/> + <reg name="t6" bitsize="64"/> + <reg name="t7" bitsize="64"/> + <reg name="s0" bitsize="64"/> + <reg name="s1" bitsize="64"/> + <reg name="s2" bitsize="64"/> + <reg name="s3" bitsize="64"/> + <reg name="s4" bitsize="64"/> + <reg name="s5" bitsize="64"/> + <reg name="s6" bitsize="64"/> + <reg name="s7" bitsize="64"/> + <reg name="t8" bitsize="64"/> + <reg name="t9" bitsize="64"/> + <reg name="k0" bitsize="64"/> + <reg name="k1" bitsize="64"/> + <reg name="gp" bitsize="64"/> + <reg name="sp" bitsize="64"/> + <reg name="s8" bitsize="64"/> + <reg name="ra" bitsize="64"/> + <reg name="sr" bitsize="64"/> + <reg name="lo" bitsize="64"/> + <reg name="hi" bitsize="64"/> + <reg name="bad" bitsize="64"/> + <reg name="cause" bitsize="64"/> + <reg name="pc" bitsize="64"/> + + <reg name="f0" bitsize="64" regnum="38"/> + <reg name="f1" bitsize="64"/> + <reg name="f2" bitsize="64"/> + <reg name="f3" bitsize="64"/> + <reg name="f4" bitsize="64"/> + <reg name="f5" bitsize="64"/> + <reg name="f6" bitsize="64"/> + <reg name="f7" bitsize="64"/> + <reg name="f8" bitsize="64"/> + <reg name="f9" bitsize="64"/> + <reg name="f10" bitsize="64"/> + <reg name="f11" bitsize="64"/> + <reg name="f12" bitsize="64"/> + <reg name="f13" bitsize="64"/> + <reg name="f14" bitsize="64"/> + <reg name="f15" bitsize="64"/> + <reg name="f16" bitsize="64"/> + <reg name="f17" bitsize="64"/> + <reg name="f18" bitsize="64"/> + <reg name="f19" bitsize="64"/> + <reg name="f20" bitsize="64"/> + <reg name="f21" bitsize="64"/> + <reg name="f22" bitsize="64"/> + <reg name="f23" bitsize="64"/> + <reg name="f24" bitsize="64"/> + <reg name="f25" bitsize="64"/> + <reg name="f26" bitsize="64"/> + <reg name="f27" bitsize="64"/> + <reg name="f28" bitsize="64"/> + <reg name="f29" bitsize="64"/> + <reg name="f30" bitsize="64"/> + <reg name="f31" bitsize="64"/> + <reg name="fsr" bitsize="64" group="float"/> + <reg name="fir" bitsize="64" group="float"/> + <reg name="fp" bitsize="64" group="float"/> +</feature> diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbcf7ca463..014f1db59e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) return oc; } +static gchar *mips_gdb_arch_name(CPUState *cs) +{ + return g_strdup("mips"); +} + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->tlb_fill = mips_cpu_tlb_fill; #endif + cc->gdb_arch_name = mips_gdb_arch_name; +#ifdef TARGET_MIPS64 + cc->gdb_core_xml_file = "mips64-core.xml"; +#else + cc->gdb_core_xml_file = "mips-core.xml"; +#endif cc->gdb_num_core_regs = 73; cc->gdb_stop_before_watchpoint = true; } -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] target/mips: add gdb xml files 2019-10-07 7:41 [PATCH] target/mips: add gdb xml files Mikhail Abakumov @ 2019-10-07 15:46 ` Alex Bennée 2019-10-08 13:37 ` Aleksandar Markovic 0 siblings, 1 reply; 5+ messages in thread From: Alex Bennée @ 2019-10-07 15:46 UTC (permalink / raw) To: Mikhail Abakumov; +Cc: arikalo, amarkovic, philmd, Qemu Devel, aurelien Mikhail Abakumov <mikhail.abakumov@ispras.ru> writes: > From: Mikhail Abakumov <mikhail.abakumov@ispras> Hmm the email got truncated here. > > This patch add xml files with gdb registers for mips. > > Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras> > --- > configure | 3 ++ > gdb-xml/mips-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ > gdb-xml/mips64-core.xml | 84 > +++++++++++++++++++++++++++++++++++++++++ Otherwise for the configure/xml: Acked-by: Alex Bennée <alex.bennee@linaro.org> I assume the changes will go in via a MIPS tree. > target/mips/cpu.c | 11 ++++++ > 4 files changed, 182 insertions(+) > create mode 100644 gdb-xml/mips-core.xml > create mode 100644 gdb-xml/mips64-core.xml > > diff --git a/configure b/configure > index 8f8446f52b..5bb2c62194 100755 > --- a/configure > +++ b/configure > @@ -7466,12 +7466,14 @@ case "$target_name" in > mips|mipsel) > mttcg="yes" > TARGET_ARCH=mips > + gdb_xml_files="mips-core.xml" > echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak > ;; > mipsn32|mipsn32el) > mttcg="yes" > TARGET_ARCH=mips64 > TARGET_BASE_ARCH=mips > + gdb_xml_files="mips64-core.xml" > echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak > echo "TARGET_ABI32=y" >> $config_target_mak > ;; > @@ -7479,6 +7481,7 @@ case "$target_name" in > mttcg="yes" > TARGET_ARCH=mips64 > TARGET_BASE_ARCH=mips > + gdb_xml_files="mips64-core.xml" > echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak > ;; > moxie) > diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml > new file mode 100644 > index 0000000000..a46b2993eb > --- /dev/null > +++ b/gdb-xml/mips-core.xml > @@ -0,0 +1,84 @@ > +<?xml version="1.0"?> > +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. > + > + Copying and distribution of this file, with or without > modification, > + are permitted in any medium without royalty provided the copyright > + notice and this notice are preserved. --> > + > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > +<feature name="org.gnu.gdb.mips"> > + <reg name="zero" bitsize="32"/> > + <reg name="at" bitsize="32"/> > + <reg name="v0" bitsize="32"/> > + <reg name="v1" bitsize="32"/> > + <reg name="a0" bitsize="32"/> > + <reg name="a1" bitsize="32"/> > + <reg name="a2" bitsize="32"/> > + <reg name="a3" bitsize="32"/> > + <reg name="t0" bitsize="32"/> > + <reg name="t1" bitsize="32"/> > + <reg name="t2" bitsize="32"/> > + <reg name="t3" bitsize="32"/> > + <reg name="t4" bitsize="32"/> > + <reg name="t5" bitsize="32"/> > + <reg name="t6" bitsize="32"/> > + <reg name="t7" bitsize="32"/> > + <reg name="s0" bitsize="32"/> > + <reg name="s1" bitsize="32"/> > + <reg name="s2" bitsize="32"/> > + <reg name="s3" bitsize="32"/> > + <reg name="s4" bitsize="32"/> > + <reg name="s5" bitsize="32"/> > + <reg name="s6" bitsize="32"/> > + <reg name="s7" bitsize="32"/> > + <reg name="t8" bitsize="32"/> > + <reg name="t9" bitsize="32"/> > + <reg name="k0" bitsize="32"/> > + <reg name="k1" bitsize="32"/> > + <reg name="gp" bitsize="32"/> > + <reg name="sp" bitsize="32"/> > + <reg name="s8" bitsize="32"/> > + <reg name="ra" bitsize="32"/> > + <reg name="sr" bitsize="32"/> > + <reg name="lo" bitsize="32"/> > + <reg name="hi" bitsize="32"/> > + <reg name="bad" bitsize="32"/> > + <reg name="cause" bitsize="32"/> > + <reg name="pc" bitsize="32"/> > + > + <reg name="f0" bitsize="32" regnum="38"/> > + <reg name="f1" bitsize="32"/> > + <reg name="f2" bitsize="32"/> > + <reg name="f3" bitsize="32"/> > + <reg name="f4" bitsize="32"/> > + <reg name="f5" bitsize="32"/> > + <reg name="f6" bitsize="32"/> > + <reg name="f7" bitsize="32"/> > + <reg name="f8" bitsize="32"/> > + <reg name="f9" bitsize="32"/> > + <reg name="f10" bitsize="32"/> > + <reg name="f11" bitsize="32"/> > + <reg name="f12" bitsize="32"/> > + <reg name="f13" bitsize="32"/> > + <reg name="f14" bitsize="32"/> > + <reg name="f15" bitsize="32"/> > + <reg name="f16" bitsize="32"/> > + <reg name="f17" bitsize="32"/> > + <reg name="f18" bitsize="32"/> > + <reg name="f19" bitsize="32"/> > + <reg name="f20" bitsize="32"/> > + <reg name="f21" bitsize="32"/> > + <reg name="f22" bitsize="32"/> > + <reg name="f23" bitsize="32"/> > + <reg name="f24" bitsize="32"/> > + <reg name="f25" bitsize="32"/> > + <reg name="f26" bitsize="32"/> > + <reg name="f27" bitsize="32"/> > + <reg name="f28" bitsize="32"/> > + <reg name="f29" bitsize="32"/> > + <reg name="f30" bitsize="32"/> > + <reg name="f31" bitsize="32"/> > + <reg name="fsr" bitsize="32" group="float"/> > + <reg name="fir" bitsize="32" group="float"/> > + <reg name="fp" bitsize="32" group="float"/> > +</feature> > diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml > new file mode 100644 > index 0000000000..cc1a15ad56 > --- /dev/null > +++ b/gdb-xml/mips64-core.xml > @@ -0,0 +1,84 @@ > +<?xml version="1.0"?> > +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. > + > + Copying and distribution of this file, with or without > modification, > + are permitted in any medium without royalty provided the copyright > + notice and this notice are preserved. --> > + > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > +<feature name="org.gnu.gdb.mips64"> > + <reg name="zero" bitsize="64"/> > + <reg name="at" bitsize="64"/> > + <reg name="v0" bitsize="64"/> > + <reg name="v1" bitsize="64"/> > + <reg name="a0" bitsize="64"/> > + <reg name="a1" bitsize="64"/> > + <reg name="a2" bitsize="64"/> > + <reg name="a3" bitsize="64"/> > + <reg name="t0" bitsize="64"/> > + <reg name="t1" bitsize="64"/> > + <reg name="t2" bitsize="64"/> > + <reg name="t3" bitsize="64"/> > + <reg name="t4" bitsize="64"/> > + <reg name="t5" bitsize="64"/> > + <reg name="t6" bitsize="64"/> > + <reg name="t7" bitsize="64"/> > + <reg name="s0" bitsize="64"/> > + <reg name="s1" bitsize="64"/> > + <reg name="s2" bitsize="64"/> > + <reg name="s3" bitsize="64"/> > + <reg name="s4" bitsize="64"/> > + <reg name="s5" bitsize="64"/> > + <reg name="s6" bitsize="64"/> > + <reg name="s7" bitsize="64"/> > + <reg name="t8" bitsize="64"/> > + <reg name="t9" bitsize="64"/> > + <reg name="k0" bitsize="64"/> > + <reg name="k1" bitsize="64"/> > + <reg name="gp" bitsize="64"/> > + <reg name="sp" bitsize="64"/> > + <reg name="s8" bitsize="64"/> > + <reg name="ra" bitsize="64"/> > + <reg name="sr" bitsize="64"/> > + <reg name="lo" bitsize="64"/> > + <reg name="hi" bitsize="64"/> > + <reg name="bad" bitsize="64"/> > + <reg name="cause" bitsize="64"/> > + <reg name="pc" bitsize="64"/> > + > + <reg name="f0" bitsize="64" regnum="38"/> > + <reg name="f1" bitsize="64"/> > + <reg name="f2" bitsize="64"/> > + <reg name="f3" bitsize="64"/> > + <reg name="f4" bitsize="64"/> > + <reg name="f5" bitsize="64"/> > + <reg name="f6" bitsize="64"/> > + <reg name="f7" bitsize="64"/> > + <reg name="f8" bitsize="64"/> > + <reg name="f9" bitsize="64"/> > + <reg name="f10" bitsize="64"/> > + <reg name="f11" bitsize="64"/> > + <reg name="f12" bitsize="64"/> > + <reg name="f13" bitsize="64"/> > + <reg name="f14" bitsize="64"/> > + <reg name="f15" bitsize="64"/> > + <reg name="f16" bitsize="64"/> > + <reg name="f17" bitsize="64"/> > + <reg name="f18" bitsize="64"/> > + <reg name="f19" bitsize="64"/> > + <reg name="f20" bitsize="64"/> > + <reg name="f21" bitsize="64"/> > + <reg name="f22" bitsize="64"/> > + <reg name="f23" bitsize="64"/> > + <reg name="f24" bitsize="64"/> > + <reg name="f25" bitsize="64"/> > + <reg name="f26" bitsize="64"/> > + <reg name="f27" bitsize="64"/> > + <reg name="f28" bitsize="64"/> > + <reg name="f29" bitsize="64"/> > + <reg name="f30" bitsize="64"/> > + <reg name="f31" bitsize="64"/> > + <reg name="fsr" bitsize="64" group="float"/> > + <reg name="fir" bitsize="64" group="float"/> > + <reg name="fp" bitsize="64" group="float"/> > +</feature> > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index bbcf7ca463..014f1db59e 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const > char *cpu_model) > return oc; > } > > +static gchar *mips_gdb_arch_name(CPUState *cs) > +{ > + return g_strdup("mips"); > +} > + > static void mips_cpu_class_init(ObjectClass *c, void *data) > { > MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); > @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass *c, > void *data) > cc->tlb_fill = mips_cpu_tlb_fill; > #endif > > + cc->gdb_arch_name = mips_gdb_arch_name; > +#ifdef TARGET_MIPS64 > + cc->gdb_core_xml_file = "mips64-core.xml"; > +#else > + cc->gdb_core_xml_file = "mips-core.xml"; > +#endif > cc->gdb_num_core_regs = 73; > cc->gdb_stop_before_watchpoint = true; > } -- Alex Bennée ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] target/mips: add gdb xml files 2019-10-07 15:46 ` Alex Bennée @ 2019-10-08 13:37 ` Aleksandar Markovic 2019-10-09 8:42 ` Mikhail Abakumov 0 siblings, 1 reply; 5+ messages in thread From: Aleksandar Markovic @ 2019-10-08 13:37 UTC (permalink / raw) To: Alex Bennée Cc: arikalo, Qemu Devel, Mikhail Abakumov, amarkovic, philmd, aurelien [-- Attachment #1: Type: text/plain, Size: 10160 bytes --] On Monday, October 7, 2019, Alex Bennée <alex.bennee@linaro.org> wrote: > > Mikhail Abakumov <mikhail.abakumov@ispras.ru> writes: > > > From: Mikhail Abakumov <mikhail.abakumov@ispras> > > Hmm the email got truncated here. > > > > > This patch add xml files with gdb registers for mips. > > > > Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras> > > --- > > configure | 3 ++ > > gdb-xml/mips-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ > > gdb-xml/mips64-core.xml | 84 > > +++++++++++++++++++++++++++++++++++++++++ > > Otherwise for the configure/xml: > > Acked-by: Alex Bennée <alex.bennee@linaro.org> > > I assume the changes will go in via a MIPS tree. > > Yes, this should go via mips tree. Thanks for taking a look. Mikhail, thanks for this effort. Is there any way to include MSA registers, possibly in a separate file, and in a separate patch? What about a separate file for FPU registers? Can you take a look at corresponding solutions for other architectures? Yours, Aleksandar > > target/mips/cpu.c | 11 ++++++ > > 4 files changed, 182 insertions(+) > > create mode 100644 gdb-xml/mips-core.xml > > create mode 100644 gdb-xml/mips64-core.xml > > > > diff --git a/configure b/configure > > index 8f8446f52b..5bb2c62194 100755 > > --- a/configure > > +++ b/configure > > @@ -7466,12 +7466,14 @@ case "$target_name" in > > mips|mipsel) > > mttcg="yes" > > TARGET_ARCH=mips > > + gdb_xml_files="mips-core.xml" > > echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak > > ;; > > mipsn32|mipsn32el) > > mttcg="yes" > > TARGET_ARCH=mips64 > > TARGET_BASE_ARCH=mips > > + gdb_xml_files="mips64-core.xml" > > echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak > > echo "TARGET_ABI32=y" >> $config_target_mak > > ;; > > @@ -7479,6 +7481,7 @@ case "$target_name" in > > mttcg="yes" > > TARGET_ARCH=mips64 > > TARGET_BASE_ARCH=mips > > + gdb_xml_files="mips64-core.xml" > > echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak > > ;; > > moxie) > > diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml > > new file mode 100644 > > index 0000000000..a46b2993eb > > --- /dev/null > > +++ b/gdb-xml/mips-core.xml > > @@ -0,0 +1,84 @@ > > +<?xml version="1.0"?> > > +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. > > + > > + Copying and distribution of this file, with or without > > modification, > > + are permitted in any medium without royalty provided the copyright > > + notice and this notice are preserved. --> > > + > > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > > +<feature name="org.gnu.gdb.mips"> > > + <reg name="zero" bitsize="32"/> > > + <reg name="at" bitsize="32"/> > > + <reg name="v0" bitsize="32"/> > > + <reg name="v1" bitsize="32"/> > > + <reg name="a0" bitsize="32"/> > > + <reg name="a1" bitsize="32"/> > > + <reg name="a2" bitsize="32"/> > > + <reg name="a3" bitsize="32"/> > > + <reg name="t0" bitsize="32"/> > > + <reg name="t1" bitsize="32"/> > > + <reg name="t2" bitsize="32"/> > > + <reg name="t3" bitsize="32"/> > > + <reg name="t4" bitsize="32"/> > > + <reg name="t5" bitsize="32"/> > > + <reg name="t6" bitsize="32"/> > > + <reg name="t7" bitsize="32"/> > > + <reg name="s0" bitsize="32"/> > > + <reg name="s1" bitsize="32"/> > > + <reg name="s2" bitsize="32"/> > > + <reg name="s3" bitsize="32"/> > > + <reg name="s4" bitsize="32"/> > > + <reg name="s5" bitsize="32"/> > > + <reg name="s6" bitsize="32"/> > > + <reg name="s7" bitsize="32"/> > > + <reg name="t8" bitsize="32"/> > > + <reg name="t9" bitsize="32"/> > > + <reg name="k0" bitsize="32"/> > > + <reg name="k1" bitsize="32"/> > > + <reg name="gp" bitsize="32"/> > > + <reg name="sp" bitsize="32"/> > > + <reg name="s8" bitsize="32"/> > > + <reg name="ra" bitsize="32"/> > > + <reg name="sr" bitsize="32"/> > > + <reg name="lo" bitsize="32"/> > > + <reg name="hi" bitsize="32"/> > > + <reg name="bad" bitsize="32"/> > > + <reg name="cause" bitsize="32"/> > > + <reg name="pc" bitsize="32"/> > > + > > + <reg name="f0" bitsize="32" regnum="38"/> > > + <reg name="f1" bitsize="32"/> > > + <reg name="f2" bitsize="32"/> > > + <reg name="f3" bitsize="32"/> > > + <reg name="f4" bitsize="32"/> > > + <reg name="f5" bitsize="32"/> > > + <reg name="f6" bitsize="32"/> > > + <reg name="f7" bitsize="32"/> > > + <reg name="f8" bitsize="32"/> > > + <reg name="f9" bitsize="32"/> > > + <reg name="f10" bitsize="32"/> > > + <reg name="f11" bitsize="32"/> > > + <reg name="f12" bitsize="32"/> > > + <reg name="f13" bitsize="32"/> > > + <reg name="f14" bitsize="32"/> > > + <reg name="f15" bitsize="32"/> > > + <reg name="f16" bitsize="32"/> > > + <reg name="f17" bitsize="32"/> > > + <reg name="f18" bitsize="32"/> > > + <reg name="f19" bitsize="32"/> > > + <reg name="f20" bitsize="32"/> > > + <reg name="f21" bitsize="32"/> > > + <reg name="f22" bitsize="32"/> > > + <reg name="f23" bitsize="32"/> > > + <reg name="f24" bitsize="32"/> > > + <reg name="f25" bitsize="32"/> > > + <reg name="f26" bitsize="32"/> > > + <reg name="f27" bitsize="32"/> > > + <reg name="f28" bitsize="32"/> > > + <reg name="f29" bitsize="32"/> > > + <reg name="f30" bitsize="32"/> > > + <reg name="f31" bitsize="32"/> > > + <reg name="fsr" bitsize="32" group="float"/> > > + <reg name="fir" bitsize="32" group="float"/> > > + <reg name="fp" bitsize="32" group="float"/> > > +</feature> > > diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml > > new file mode 100644 > > index 0000000000..cc1a15ad56 > > --- /dev/null > > +++ b/gdb-xml/mips64-core.xml > > @@ -0,0 +1,84 @@ > > +<?xml version="1.0"?> > > +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. > > + > > + Copying and distribution of this file, with or without > > modification, > > + are permitted in any medium without royalty provided the copyright > > + notice and this notice are preserved. --> > > + > > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > > +<feature name="org.gnu.gdb.mips64"> > > + <reg name="zero" bitsize="64"/> > > + <reg name="at" bitsize="64"/> > > + <reg name="v0" bitsize="64"/> > > + <reg name="v1" bitsize="64"/> > > + <reg name="a0" bitsize="64"/> > > + <reg name="a1" bitsize="64"/> > > + <reg name="a2" bitsize="64"/> > > + <reg name="a3" bitsize="64"/> > > + <reg name="t0" bitsize="64"/> > > + <reg name="t1" bitsize="64"/> > > + <reg name="t2" bitsize="64"/> > > + <reg name="t3" bitsize="64"/> > > + <reg name="t4" bitsize="64"/> > > + <reg name="t5" bitsize="64"/> > > + <reg name="t6" bitsize="64"/> > > + <reg name="t7" bitsize="64"/> > > + <reg name="s0" bitsize="64"/> > > + <reg name="s1" bitsize="64"/> > > + <reg name="s2" bitsize="64"/> > > + <reg name="s3" bitsize="64"/> > > + <reg name="s4" bitsize="64"/> > > + <reg name="s5" bitsize="64"/> > > + <reg name="s6" bitsize="64"/> > > + <reg name="s7" bitsize="64"/> > > + <reg name="t8" bitsize="64"/> > > + <reg name="t9" bitsize="64"/> > > + <reg name="k0" bitsize="64"/> > > + <reg name="k1" bitsize="64"/> > > + <reg name="gp" bitsize="64"/> > > + <reg name="sp" bitsize="64"/> > > + <reg name="s8" bitsize="64"/> > > + <reg name="ra" bitsize="64"/> > > + <reg name="sr" bitsize="64"/> > > + <reg name="lo" bitsize="64"/> > > + <reg name="hi" bitsize="64"/> > > + <reg name="bad" bitsize="64"/> > > + <reg name="cause" bitsize="64"/> > > + <reg name="pc" bitsize="64"/> > > + > > + <reg name="f0" bitsize="64" regnum="38"/> > > + <reg name="f1" bitsize="64"/> > > + <reg name="f2" bitsize="64"/> > > + <reg name="f3" bitsize="64"/> > > + <reg name="f4" bitsize="64"/> > > + <reg name="f5" bitsize="64"/> > > + <reg name="f6" bitsize="64"/> > > + <reg name="f7" bitsize="64"/> > > + <reg name="f8" bitsize="64"/> > > + <reg name="f9" bitsize="64"/> > > + <reg name="f10" bitsize="64"/> > > + <reg name="f11" bitsize="64"/> > > + <reg name="f12" bitsize="64"/> > > + <reg name="f13" bitsize="64"/> > > + <reg name="f14" bitsize="64"/> > > + <reg name="f15" bitsize="64"/> > > + <reg name="f16" bitsize="64"/> > > + <reg name="f17" bitsize="64"/> > > + <reg name="f18" bitsize="64"/> > > + <reg name="f19" bitsize="64"/> > > + <reg name="f20" bitsize="64"/> > > + <reg name="f21" bitsize="64"/> > > + <reg name="f22" bitsize="64"/> > > + <reg name="f23" bitsize="64"/> > > + <reg name="f24" bitsize="64"/> > > + <reg name="f25" bitsize="64"/> > > + <reg name="f26" bitsize="64"/> > > + <reg name="f27" bitsize="64"/> > > + <reg name="f28" bitsize="64"/> > > + <reg name="f29" bitsize="64"/> > > + <reg name="f30" bitsize="64"/> > > + <reg name="f31" bitsize="64"/> > > + <reg name="fsr" bitsize="64" group="float"/> > > + <reg name="fir" bitsize="64" group="float"/> > > + <reg name="fp" bitsize="64" group="float"/> > > +</feature> > > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > > index bbcf7ca463..014f1db59e 100644 > > --- a/target/mips/cpu.c > > +++ b/target/mips/cpu.c > > @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const > > char *cpu_model) > > return oc; > > } > > > > +static gchar *mips_gdb_arch_name(CPUState *cs) > > +{ > > + return g_strdup("mips"); > > +} > > + > > static void mips_cpu_class_init(ObjectClass *c, void *data) > > { > > MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); > > @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass *c, > > void *data) > > cc->tlb_fill = mips_cpu_tlb_fill; > > #endif > > > > + cc->gdb_arch_name = mips_gdb_arch_name; > > +#ifdef TARGET_MIPS64 > > + cc->gdb_core_xml_file = "mips64-core.xml"; > > +#else > > + cc->gdb_core_xml_file = "mips-core.xml"; > > +#endif > > cc->gdb_num_core_regs = 73; > > cc->gdb_stop_before_watchpoint = true; > > } > > > -- > Alex Bennée > > [-- Attachment #2: Type: text/html, Size: 16515 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] target/mips: add gdb xml files 2019-10-08 13:37 ` Aleksandar Markovic @ 2019-10-09 8:42 ` Mikhail Abakumov 2019-10-09 10:09 ` Aleksandar Markovic 0 siblings, 1 reply; 5+ messages in thread From: Mikhail Abakumov @ 2019-10-09 8:42 UTC (permalink / raw) To: Aleksandar Markovic Cc: arikalo, Alex Bennée, Qemu Devel, amarkovic, philmd, aurelien Aleksandar Markovic писал 2019-10-08 16:37: > On Monday, October 7, 2019, Alex Bennée <alex.bennee@linaro.org> > wrote: > >> Mikhail Abakumov <mikhail.abakumov@ispras.ru> writes: >> >>> From: Mikhail Abakumov <mikhail.abakumov@ispras> >> >> Hmm the email got truncated here. >> >>> >>> This patch add xml files with gdb registers for mips. >>> >>> Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras> >>> --- >>> configure | 3 ++ >>> gdb-xml/mips-core.xml | 84 >> +++++++++++++++++++++++++++++++++++++++++ >>> gdb-xml/mips64-core.xml | 84 >>> +++++++++++++++++++++++++++++++++++++++++ >> >> Otherwise for the configure/xml: >> >> Acked-by: Alex Bennée <alex.bennee@linaro.org> >> >> I assume the changes will go in via a MIPS tree. > > Yes, this should go via mips tree. Thanks for taking a look. > > Mikhail, thanks for this effort. > > Is there any way to include MSA registers, possibly in a separate > file, and in a separate patch? What about a separate file for FPU > registers? Can you take a look at corresponding solutions for other > architectures? Thanks for the feedback. Yes, I did it initially. But looking at other architectures, redid it. Everywhere, one main xml-file is used for registers, described in the target/gdbstub. And additional ones are appended through 'gdb_register_coprocessor'. In the current patch, I made a description of the registers described only in the target/gdbstub. In the future, I think FPU registers can be moved to a separate file, but then need to move them from the mips/gdbstub. > > Yours, > Aleksandar > >>> target/mips/cpu.c | 11 ++++++ >>> 4 files changed, 182 insertions(+) >>> create mode 100644 gdb-xml/mips-core.xml >>> create mode 100644 gdb-xml/mips64-core.xml >>> >>> diff --git a/configure b/configure >>> index 8f8446f52b..5bb2c62194 100755 >>> --- a/configure >>> +++ b/configure >>> @@ -7466,12 +7466,14 @@ case "$target_name" in >>> mips|mipsel) >>> mttcg="yes" >>> TARGET_ARCH=mips >>> + gdb_xml_files="mips-core.xml" >>> echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak >>> ;; >>> mipsn32|mipsn32el) >>> mttcg="yes" >>> TARGET_ARCH=mips64 >>> TARGET_BASE_ARCH=mips >>> + gdb_xml_files="mips64-core.xml" >>> echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak >>> echo "TARGET_ABI32=y" >> $config_target_mak >>> ;; >>> @@ -7479,6 +7481,7 @@ case "$target_name" in >>> mttcg="yes" >>> TARGET_ARCH=mips64 >>> TARGET_BASE_ARCH=mips >>> + gdb_xml_files="mips64-core.xml" >>> echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak >>> ;; >>> moxie) >>> diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml >>> new file mode 100644 >>> index 0000000000..a46b2993eb >>> --- /dev/null >>> +++ b/gdb-xml/mips-core.xml >>> @@ -0,0 +1,84 @@ >>> +<?xml version="1.0"?> >>> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. >>> + >>> + Copying and distribution of this file, with or without >>> modification, >>> + are permitted in any medium without royalty provided the >> copyright >>> + notice and this notice are preserved. --> >>> + >>> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> >>> +<feature name="org.gnu.gdb.mips"> >>> + <reg name="zero" bitsize="32"/> >>> + <reg name="at" bitsize="32"/> >>> + <reg name="v0" bitsize="32"/> >>> + <reg name="v1" bitsize="32"/> >>> + <reg name="a0" bitsize="32"/> >>> + <reg name="a1" bitsize="32"/> >>> + <reg name="a2" bitsize="32"/> >>> + <reg name="a3" bitsize="32"/> >>> + <reg name="t0" bitsize="32"/> >>> + <reg name="t1" bitsize="32"/> >>> + <reg name="t2" bitsize="32"/> >>> + <reg name="t3" bitsize="32"/> >>> + <reg name="t4" bitsize="32"/> >>> + <reg name="t5" bitsize="32"/> >>> + <reg name="t6" bitsize="32"/> >>> + <reg name="t7" bitsize="32"/> >>> + <reg name="s0" bitsize="32"/> >>> + <reg name="s1" bitsize="32"/> >>> + <reg name="s2" bitsize="32"/> >>> + <reg name="s3" bitsize="32"/> >>> + <reg name="s4" bitsize="32"/> >>> + <reg name="s5" bitsize="32"/> >>> + <reg name="s6" bitsize="32"/> >>> + <reg name="s7" bitsize="32"/> >>> + <reg name="t8" bitsize="32"/> >>> + <reg name="t9" bitsize="32"/> >>> + <reg name="k0" bitsize="32"/> >>> + <reg name="k1" bitsize="32"/> >>> + <reg name="gp" bitsize="32"/> >>> + <reg name="sp" bitsize="32"/> >>> + <reg name="s8" bitsize="32"/> >>> + <reg name="ra" bitsize="32"/> >>> + <reg name="sr" bitsize="32"/> >>> + <reg name="lo" bitsize="32"/> >>> + <reg name="hi" bitsize="32"/> >>> + <reg name="bad" bitsize="32"/> >>> + <reg name="cause" bitsize="32"/> >>> + <reg name="pc" bitsize="32"/> >>> + >>> + <reg name="f0" bitsize="32" regnum="38"/> >>> + <reg name="f1" bitsize="32"/> >>> + <reg name="f2" bitsize="32"/> >>> + <reg name="f3" bitsize="32"/> >>> + <reg name="f4" bitsize="32"/> >>> + <reg name="f5" bitsize="32"/> >>> + <reg name="f6" bitsize="32"/> >>> + <reg name="f7" bitsize="32"/> >>> + <reg name="f8" bitsize="32"/> >>> + <reg name="f9" bitsize="32"/> >>> + <reg name="f10" bitsize="32"/> >>> + <reg name="f11" bitsize="32"/> >>> + <reg name="f12" bitsize="32"/> >>> + <reg name="f13" bitsize="32"/> >>> + <reg name="f14" bitsize="32"/> >>> + <reg name="f15" bitsize="32"/> >>> + <reg name="f16" bitsize="32"/> >>> + <reg name="f17" bitsize="32"/> >>> + <reg name="f18" bitsize="32"/> >>> + <reg name="f19" bitsize="32"/> >>> + <reg name="f20" bitsize="32"/> >>> + <reg name="f21" bitsize="32"/> >>> + <reg name="f22" bitsize="32"/> >>> + <reg name="f23" bitsize="32"/> >>> + <reg name="f24" bitsize="32"/> >>> + <reg name="f25" bitsize="32"/> >>> + <reg name="f26" bitsize="32"/> >>> + <reg name="f27" bitsize="32"/> >>> + <reg name="f28" bitsize="32"/> >>> + <reg name="f29" bitsize="32"/> >>> + <reg name="f30" bitsize="32"/> >>> + <reg name="f31" bitsize="32"/> >>> + <reg name="fsr" bitsize="32" group="float"/> >>> + <reg name="fir" bitsize="32" group="float"/> >>> + <reg name="fp" bitsize="32" group="float"/> >>> +</feature> >>> diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml >>> new file mode 100644 >>> index 0000000000..cc1a15ad56 >>> --- /dev/null >>> +++ b/gdb-xml/mips64-core.xml >>> @@ -0,0 +1,84 @@ >>> +<?xml version="1.0"?> >>> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. >>> + >>> + Copying and distribution of this file, with or without >>> modification, >>> + are permitted in any medium without royalty provided the >> copyright >>> + notice and this notice are preserved. --> >>> + >>> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> >>> +<feature name="org.gnu.gdb.mips64"> >>> + <reg name="zero" bitsize="64"/> >>> + <reg name="at" bitsize="64"/> >>> + <reg name="v0" bitsize="64"/> >>> + <reg name="v1" bitsize="64"/> >>> + <reg name="a0" bitsize="64"/> >>> + <reg name="a1" bitsize="64"/> >>> + <reg name="a2" bitsize="64"/> >>> + <reg name="a3" bitsize="64"/> >>> + <reg name="t0" bitsize="64"/> >>> + <reg name="t1" bitsize="64"/> >>> + <reg name="t2" bitsize="64"/> >>> + <reg name="t3" bitsize="64"/> >>> + <reg name="t4" bitsize="64"/> >>> + <reg name="t5" bitsize="64"/> >>> + <reg name="t6" bitsize="64"/> >>> + <reg name="t7" bitsize="64"/> >>> + <reg name="s0" bitsize="64"/> >>> + <reg name="s1" bitsize="64"/> >>> + <reg name="s2" bitsize="64"/> >>> + <reg name="s3" bitsize="64"/> >>> + <reg name="s4" bitsize="64"/> >>> + <reg name="s5" bitsize="64"/> >>> + <reg name="s6" bitsize="64"/> >>> + <reg name="s7" bitsize="64"/> >>> + <reg name="t8" bitsize="64"/> >>> + <reg name="t9" bitsize="64"/> >>> + <reg name="k0" bitsize="64"/> >>> + <reg name="k1" bitsize="64"/> >>> + <reg name="gp" bitsize="64"/> >>> + <reg name="sp" bitsize="64"/> >>> + <reg name="s8" bitsize="64"/> >>> + <reg name="ra" bitsize="64"/> >>> + <reg name="sr" bitsize="64"/> >>> + <reg name="lo" bitsize="64"/> >>> + <reg name="hi" bitsize="64"/> >>> + <reg name="bad" bitsize="64"/> >>> + <reg name="cause" bitsize="64"/> >>> + <reg name="pc" bitsize="64"/> >>> + >>> + <reg name="f0" bitsize="64" regnum="38"/> >>> + <reg name="f1" bitsize="64"/> >>> + <reg name="f2" bitsize="64"/> >>> + <reg name="f3" bitsize="64"/> >>> + <reg name="f4" bitsize="64"/> >>> + <reg name="f5" bitsize="64"/> >>> + <reg name="f6" bitsize="64"/> >>> + <reg name="f7" bitsize="64"/> >>> + <reg name="f8" bitsize="64"/> >>> + <reg name="f9" bitsize="64"/> >>> + <reg name="f10" bitsize="64"/> >>> + <reg name="f11" bitsize="64"/> >>> + <reg name="f12" bitsize="64"/> >>> + <reg name="f13" bitsize="64"/> >>> + <reg name="f14" bitsize="64"/> >>> + <reg name="f15" bitsize="64"/> >>> + <reg name="f16" bitsize="64"/> >>> + <reg name="f17" bitsize="64"/> >>> + <reg name="f18" bitsize="64"/> >>> + <reg name="f19" bitsize="64"/> >>> + <reg name="f20" bitsize="64"/> >>> + <reg name="f21" bitsize="64"/> >>> + <reg name="f22" bitsize="64"/> >>> + <reg name="f23" bitsize="64"/> >>> + <reg name="f24" bitsize="64"/> >>> + <reg name="f25" bitsize="64"/> >>> + <reg name="f26" bitsize="64"/> >>> + <reg name="f27" bitsize="64"/> >>> + <reg name="f28" bitsize="64"/> >>> + <reg name="f29" bitsize="64"/> >>> + <reg name="f30" bitsize="64"/> >>> + <reg name="f31" bitsize="64"/> >>> + <reg name="fsr" bitsize="64" group="float"/> >>> + <reg name="fir" bitsize="64" group="float"/> >>> + <reg name="fp" bitsize="64" group="float"/> >>> +</feature> >>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>> index bbcf7ca463..014f1db59e 100644 >>> --- a/target/mips/cpu.c >>> +++ b/target/mips/cpu.c >>> @@ -181,6 +181,11 @@ static ObjectClass >> *mips_cpu_class_by_name(const >>> char *cpu_model) >>> return oc; >>> } >>> >>> +static gchar *mips_gdb_arch_name(CPUState *cs) >>> +{ >>> + return g_strdup("mips"); >>> +} >>> + >>> static void mips_cpu_class_init(ObjectClass *c, void *data) >>> { >>> MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); >>> @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass >> *c, >>> void *data) >>> cc->tlb_fill = mips_cpu_tlb_fill; >>> #endif >>> >>> + cc->gdb_arch_name = mips_gdb_arch_name; >>> +#ifdef TARGET_MIPS64 >>> + cc->gdb_core_xml_file = "mips64-core.xml"; >>> +#else >>> + cc->gdb_core_xml_file = "mips-core.xml"; >>> +#endif >>> cc->gdb_num_core_regs = 73; >>> cc->gdb_stop_before_watchpoint = true; >>> } >> >> -- >> Alex Bennée -- Mikhail Abakumov ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] target/mips: add gdb xml files 2019-10-09 8:42 ` Mikhail Abakumov @ 2019-10-09 10:09 ` Aleksandar Markovic 0 siblings, 0 replies; 5+ messages in thread From: Aleksandar Markovic @ 2019-10-09 10:09 UTC (permalink / raw) To: Mikhail Abakumov Cc: arikalo, Alex Bennée, Qemu Devel, amarkovic, philmd, aurelien [-- Attachment #1: Type: text/plain, Size: 11575 bytes --] On Wednesday, October 9, 2019, Mikhail Abakumov <mikhail.abakumov@ispras.ru> wrote: > Aleksandar Markovic писал 2019-10-08 16:37: > >> On Monday, October 7, 2019, Alex Bennée <alex.bennee@linaro.org> >> wrote: >> >> Mikhail Abakumov <mikhail.abakumov@ispras.ru> writes: >>> >>> From: Mikhail Abakumov <mikhail.abakumov@ispras> >>>> >>> >>> Hmm the email got truncated here. >>> >>> >>>> This patch add xml files with gdb registers for mips. >>>> >>>> Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras> >>>> --- >>>> configure | 3 ++ >>>> gdb-xml/mips-core.xml | 84 >>>> >>> +++++++++++++++++++++++++++++++++++++++++ >>> >>>> gdb-xml/mips64-core.xml | 84 >>>> +++++++++++++++++++++++++++++++++++++++++ >>>> >>> >>> Otherwise for the configure/xml: >>> >>> Acked-by: Alex Bennée <alex.bennee@linaro.org> >>> >>> I assume the changes will go in via a MIPS tree. >>> >> >> Yes, this should go via mips tree. Thanks for taking a look. >> >> Mikhail, thanks for this effort. >> >> Is there any way to include MSA registers, possibly in a separate >> file, and in a separate patch? What about a separate file for FPU >> registers? Can you take a look at corresponding solutions for other >> architectures? >> > > Thanks for the feedback. > > Yes, I did it initially. But looking at other architectures, redid it. > Everywhere, one main xml-file is used for registers, described > in the target/gdbstub. And additional ones are appended through > 'gdb_register_coprocessor'. > In the current patch, I made a description of the registers described > only in the target/gdbstub. In the future, I think FPU registers > can be moved to a separate file, but then need to move them from > the mips/gdbstub. Mikhail, Your implementation assumes that 64-bit CPU always has 64-bit FPU, and 32-bit CPU - 32-bit FPU. However, that is not always true. Please see related patch for RISC-V: https://patchew.org/QEMU/20190821162831.27811-1-georg.kotheimer@kernkonzept.com/ ... and correct your solution in a similar way. Keep also in mind that, in general, gdb xml support should work for all (or at least, almost all) QEMU-supported MIPS CPUs, not just the most common. For example, is your solution correct for R4000 CPU? Is the register layout the same for, for example, "ancient" R4000 and "moderm" I6400? Thanks again! Aleksandar > >> Yours, >> Aleksandar >> >> target/mips/cpu.c | 11 ++++++ >>>> 4 files changed, 182 insertions(+) >>>> create mode 100644 gdb-xml/mips-core.xml >>>> create mode 100644 gdb-xml/mips64-core.xml >>>> >>>> diff --git a/configure b/configure >>>> index 8f8446f52b..5bb2c62194 100755 >>>> --- a/configure >>>> +++ b/configure >>>> @@ -7466,12 +7466,14 @@ case "$target_name" in >>>> mips|mipsel) >>>> mttcg="yes" >>>> TARGET_ARCH=mips >>>> + gdb_xml_files="mips-core.xml" >>>> echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak >>>> ;; >>>> mipsn32|mipsn32el) >>>> mttcg="yes" >>>> TARGET_ARCH=mips64 >>>> TARGET_BASE_ARCH=mips >>>> + gdb_xml_files="mips64-core.xml" >>>> echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak >>>> echo "TARGET_ABI32=y" >> $config_target_mak >>>> ;; >>>> @@ -7479,6 +7481,7 @@ case "$target_name" in >>>> mttcg="yes" >>>> TARGET_ARCH=mips64 >>>> TARGET_BASE_ARCH=mips >>>> + gdb_xml_files="mips64-core.xml" >>>> echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak >>>> ;; >>>> moxie) >>>> diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml >>>> new file mode 100644 >>>> index 0000000000..a46b2993eb >>>> --- /dev/null >>>> +++ b/gdb-xml/mips-core.xml >>>> @@ -0,0 +1,84 @@ >>>> +<?xml version="1.0"?> >>>> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. >>>> + >>>> + Copying and distribution of this file, with or without >>>> modification, >>>> + are permitted in any medium without royalty provided the >>>> >>> copyright >>> >>>> + notice and this notice are preserved. --> >>>> + >>>> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> >>>> +<feature name="org.gnu.gdb.mips"> >>>> + <reg name="zero" bitsize="32"/> >>>> + <reg name="at" bitsize="32"/> >>>> + <reg name="v0" bitsize="32"/> >>>> + <reg name="v1" bitsize="32"/> >>>> + <reg name="a0" bitsize="32"/> >>>> + <reg name="a1" bitsize="32"/> >>>> + <reg name="a2" bitsize="32"/> >>>> + <reg name="a3" bitsize="32"/> >>>> + <reg name="t0" bitsize="32"/> >>>> + <reg name="t1" bitsize="32"/> >>>> + <reg name="t2" bitsize="32"/> >>>> + <reg name="t3" bitsize="32"/> >>>> + <reg name="t4" bitsize="32"/> >>>> + <reg name="t5" bitsize="32"/> >>>> + <reg name="t6" bitsize="32"/> >>>> + <reg name="t7" bitsize="32"/> >>>> + <reg name="s0" bitsize="32"/> >>>> + <reg name="s1" bitsize="32"/> >>>> + <reg name="s2" bitsize="32"/> >>>> + <reg name="s3" bitsize="32"/> >>>> + <reg name="s4" bitsize="32"/> >>>> + <reg name="s5" bitsize="32"/> >>>> + <reg name="s6" bitsize="32"/> >>>> + <reg name="s7" bitsize="32"/> >>>> + <reg name="t8" bitsize="32"/> >>>> + <reg name="t9" bitsize="32"/> >>>> + <reg name="k0" bitsize="32"/> >>>> + <reg name="k1" bitsize="32"/> >>>> + <reg name="gp" bitsize="32"/> >>>> + <reg name="sp" bitsize="32"/> >>>> + <reg name="s8" bitsize="32"/> >>>> + <reg name="ra" bitsize="32"/> >>>> + <reg name="sr" bitsize="32"/> >>>> + <reg name="lo" bitsize="32"/> >>>> + <reg name="hi" bitsize="32"/> >>>> + <reg name="bad" bitsize="32"/> >>>> + <reg name="cause" bitsize="32"/> >>>> + <reg name="pc" bitsize="32"/> >>>> + >>>> + <reg name="f0" bitsize="32" regnum="38"/> >>>> + <reg name="f1" bitsize="32"/> >>>> + <reg name="f2" bitsize="32"/> >>>> + <reg name="f3" bitsize="32"/> >>>> + <reg name="f4" bitsize="32"/> >>>> + <reg name="f5" bitsize="32"/> >>>> + <reg name="f6" bitsize="32"/> >>>> + <reg name="f7" bitsize="32"/> >>>> + <reg name="f8" bitsize="32"/> >>>> + <reg name="f9" bitsize="32"/> >>>> + <reg name="f10" bitsize="32"/> >>>> + <reg name="f11" bitsize="32"/> >>>> + <reg name="f12" bitsize="32"/> >>>> + <reg name="f13" bitsize="32"/> >>>> + <reg name="f14" bitsize="32"/> >>>> + <reg name="f15" bitsize="32"/> >>>> + <reg name="f16" bitsize="32"/> >>>> + <reg name="f17" bitsize="32"/> >>>> + <reg name="f18" bitsize="32"/> >>>> + <reg name="f19" bitsize="32"/> >>>> + <reg name="f20" bitsize="32"/> >>>> + <reg name="f21" bitsize="32"/> >>>> + <reg name="f22" bitsize="32"/> >>>> + <reg name="f23" bitsize="32"/> >>>> + <reg name="f24" bitsize="32"/> >>>> + <reg name="f25" bitsize="32"/> >>>> + <reg name="f26" bitsize="32"/> >>>> + <reg name="f27" bitsize="32"/> >>>> + <reg name="f28" bitsize="32"/> >>>> + <reg name="f29" bitsize="32"/> >>>> + <reg name="f30" bitsize="32"/> >>>> + <reg name="f31" bitsize="32"/> >>>> + <reg name="fsr" bitsize="32" group="float"/> >>>> + <reg name="fir" bitsize="32" group="float"/> >>>> + <reg name="fp" bitsize="32" group="float"/> >>>> +</feature> >>>> diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml >>>> new file mode 100644 >>>> index 0000000000..cc1a15ad56 >>>> --- /dev/null >>>> +++ b/gdb-xml/mips64-core.xml >>>> @@ -0,0 +1,84 @@ >>>> +<?xml version="1.0"?> >>>> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc. >>>> + >>>> + Copying and distribution of this file, with or without >>>> modification, >>>> + are permitted in any medium without royalty provided the >>>> >>> copyright >>> >>>> + notice and this notice are preserved. --> >>>> + >>>> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> >>>> +<feature name="org.gnu.gdb.mips64"> >>>> + <reg name="zero" bitsize="64"/> >>>> + <reg name="at" bitsize="64"/> >>>> + <reg name="v0" bitsize="64"/> >>>> + <reg name="v1" bitsize="64"/> >>>> + <reg name="a0" bitsize="64"/> >>>> + <reg name="a1" bitsize="64"/> >>>> + <reg name="a2" bitsize="64"/> >>>> + <reg name="a3" bitsize="64"/> >>>> + <reg name="t0" bitsize="64"/> >>>> + <reg name="t1" bitsize="64"/> >>>> + <reg name="t2" bitsize="64"/> >>>> + <reg name="t3" bitsize="64"/> >>>> + <reg name="t4" bitsize="64"/> >>>> + <reg name="t5" bitsize="64"/> >>>> + <reg name="t6" bitsize="64"/> >>>> + <reg name="t7" bitsize="64"/> >>>> + <reg name="s0" bitsize="64"/> >>>> + <reg name="s1" bitsize="64"/> >>>> + <reg name="s2" bitsize="64"/> >>>> + <reg name="s3" bitsize="64"/> >>>> + <reg name="s4" bitsize="64"/> >>>> + <reg name="s5" bitsize="64"/> >>>> + <reg name="s6" bitsize="64"/> >>>> + <reg name="s7" bitsize="64"/> >>>> + <reg name="t8" bitsize="64"/> >>>> + <reg name="t9" bitsize="64"/> >>>> + <reg name="k0" bitsize="64"/> >>>> + <reg name="k1" bitsize="64"/> >>>> + <reg name="gp" bitsize="64"/> >>>> + <reg name="sp" bitsize="64"/> >>>> + <reg name="s8" bitsize="64"/> >>>> + <reg name="ra" bitsize="64"/> >>>> + <reg name="sr" bitsize="64"/> >>>> + <reg name="lo" bitsize="64"/> >>>> + <reg name="hi" bitsize="64"/> >>>> + <reg name="bad" bitsize="64"/> >>>> + <reg name="cause" bitsize="64"/> >>>> + <reg name="pc" bitsize="64"/> >>>> + >>>> + <reg name="f0" bitsize="64" regnum="38"/> >>>> + <reg name="f1" bitsize="64"/> >>>> + <reg name="f2" bitsize="64"/> >>>> + <reg name="f3" bitsize="64"/> >>>> + <reg name="f4" bitsize="64"/> >>>> + <reg name="f5" bitsize="64"/> >>>> + <reg name="f6" bitsize="64"/> >>>> + <reg name="f7" bitsize="64"/> >>>> + <reg name="f8" bitsize="64"/> >>>> + <reg name="f9" bitsize="64"/> >>>> + <reg name="f10" bitsize="64"/> >>>> + <reg name="f11" bitsize="64"/> >>>> + <reg name="f12" bitsize="64"/> >>>> + <reg name="f13" bitsize="64"/> >>>> + <reg name="f14" bitsize="64"/> >>>> + <reg name="f15" bitsize="64"/> >>>> + <reg name="f16" bitsize="64"/> >>>> + <reg name="f17" bitsize="64"/> >>>> + <reg name="f18" bitsize="64"/> >>>> + <reg name="f19" bitsize="64"/> >>>> + <reg name="f20" bitsize="64"/> >>>> + <reg name="f21" bitsize="64"/> >>>> + <reg name="f22" bitsize="64"/> >>>> + <reg name="f23" bitsize="64"/> >>>> + <reg name="f24" bitsize="64"/> >>>> + <reg name="f25" bitsize="64"/> >>>> + <reg name="f26" bitsize="64"/> >>>> + <reg name="f27" bitsize="64"/> >>>> + <reg name="f28" bitsize="64"/> >>>> + <reg name="f29" bitsize="64"/> >>>> + <reg name="f30" bitsize="64"/> >>>> + <reg name="f31" bitsize="64"/> >>>> + <reg name="fsr" bitsize="64" group="float"/> >>>> + <reg name="fir" bitsize="64" group="float"/> >>>> + <reg name="fp" bitsize="64" group="float"/> >>>> +</feature> >>>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>>> index bbcf7ca463..014f1db59e 100644 >>>> --- a/target/mips/cpu.c >>>> +++ b/target/mips/cpu.c >>>> @@ -181,6 +181,11 @@ static ObjectClass >>>> >>> *mips_cpu_class_by_name(const >>> >>>> char *cpu_model) >>>> return oc; >>>> } >>>> >>>> +static gchar *mips_gdb_arch_name(CPUState *cs) >>>> +{ >>>> + return g_strdup("mips"); >>>> +} >>>> + >>>> static void mips_cpu_class_init(ObjectClass *c, void *data) >>>> { >>>> MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); >>>> @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass >>>> >>> *c, >>> >>>> void *data) >>>> cc->tlb_fill = mips_cpu_tlb_fill; >>>> #endif >>>> >>>> + cc->gdb_arch_name = mips_gdb_arch_name; >>>> +#ifdef TARGET_MIPS64 >>>> + cc->gdb_core_xml_file = "mips64-core.xml"; >>>> +#else >>>> + cc->gdb_core_xml_file = "mips-core.xml"; >>>> +#endif >>>> cc->gdb_num_core_regs = 73; >>>> cc->gdb_stop_before_watchpoint = true; >>>> } >>>> >>> >>> -- >>> Alex Bennée >>> >> > -- > Mikhail Abakumov > [-- Attachment #2: Type: text/html, Size: 17798 bytes --] ^ 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end of thread, other threads:[~2019-10-09 18:08 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-07 7:41 [PATCH] target/mips: add gdb xml files Mikhail Abakumov 2019-10-07 15:46 ` Alex Bennée 2019-10-08 13:37 ` Aleksandar Markovic 2019-10-09 8:42 ` Mikhail Abakumov 2019-10-09 10:09 ` Aleksandar Markovic
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