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From: Paolo Bonzini <pbonzini@redhat.com>
To: Gan Qixin <ganqixin@huawei.com>,
	qemu-devel@nongnu.org, qemu-trivial@nongnu.org
Cc: kuhn.chenqun@huawei.com,
	Richard Henderson <richard.henderson@linaro.org>,
	zhang.zhanghailiang@huawei.com,
	Euler Robot <euler.robot@huawei.com>
Subject: Re: [PATCH] util/cacheflush: Fix error generated by clang
Date: Sun, 17 Jan 2021 17:43:12 +0100	[thread overview]
Message-ID: <ba0fdc6d-8efa-cbeb-6ebb-8589cd129d64@redhat.com> (raw)
In-Reply-To: <20210115075656.717957-1-ganqixin@huawei.com>

On 15/01/21 08:56, Gan Qixin wrote:
> When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
> error:
> 
> ../util/cacheflush.c:38:44: error: value size does not match register size
> specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
>      asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                                             ^
> ../util/cacheflush.c:38:24: note: use constraint modifier "w"
>      asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                         ^~
>                         %w0
> 
> Modify the type of save_ctr_el0 to uint64_t to fix it.
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Gan Qixin <ganqixin@huawei.com>
> ---
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   util/cacheflush.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/util/cacheflush.c b/util/cacheflush.c
> index 6a20723902..933355b0c9 100644
> --- a/util/cacheflush.c
> +++ b/util/cacheflush.c
> @@ -32,7 +32,7 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
>    * We want to save the whole contents of CTR_EL0, so that we
>    * have more than the linesize, but also IDC and DIC.
>    */
> -static unsigned int save_ctr_el0;
> +static uint64_t save_ctr_el0;
>   static void __attribute__((constructor)) init_ctr_el0(void)
>   {
>       asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
> @@ -46,9 +46,9 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
>   {
>       const unsigned CTR_IDC = 1u << 28;
>       const unsigned CTR_DIC = 1u << 29;
> -    const unsigned int ctr_el0 = save_ctr_el0;
> -    const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4);
> -    const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4);
> +    const uint64_t ctr_el0 = save_ctr_el0;
> +    const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4);
> +    const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4);
>       uintptr_t p;
>   
>       /*
> 

Queued, thanks.



      parent reply	other threads:[~2021-01-17 16:44 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15  7:56 [PATCH] util/cacheflush: Fix error generated by clang Gan Qixin
2021-01-15 16:39 ` Richard Henderson
2021-01-17 16:43 ` Paolo Bonzini [this message]

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