* Re: [PATCH v2 0/2] TM field check failed
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
@ 2019-11-19 11:05 ` Michael S. Tsirkin
2019-11-19 16:21 ` Peter Xu
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
` (2 subsequent siblings)
3 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2019-11-19 11:05 UTC (permalink / raw)
To: qi1.zhang; +Cc: ehabkost, qemu-devel, peterx, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
>
> spilt the reserved fields arrays and remove TM field from reserved
> bits
Looks good to me.
Also Cc Peter Xu.
Also I wonder - do we need to version this change
with the machine type? Peter what's your take?
Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
and add everyone involved, this way people will
remember to CC you?
> Changelog V1:
> add descriptons
> Changelog V2:
> refine
>
> Zhang, Qi (2):
> intel_iommu: split the resevred fields arrays into two ones
> intel_iommu: TM field should not be in reserved bits
>
> hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
> hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
> 2 files changed, 34 insertions(+), 18 deletions(-)
>
> --
> 2.20.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
@ 2019-11-19 11:06 ` Michael S. Tsirkin
2019-11-19 12:27 ` [PATCH " qi1.zhang
1 sibling, 0 replies; 14+ messages in thread
From: Michael S. Tsirkin @ 2019-11-19 11:06 UTC (permalink / raw)
To: qi1.zhang; +Cc: ehabkost, qemu-devel, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 08:28:14PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
>
> When dt is supported, TM field should not be Reserved(0).
>
> Refer to VT-d Spec 9.8
>
> Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
> Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
OK and we want to CC stable on this I guess?
> ---
> hw/i386/intel_iommu.c | 12 ++++++++----
> hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
> 2 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index a118efaeaf..d62604ece3 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
> * Rsvd field masks for spte
> */
> vtd_spte_rsvd[0] = ~0ULL;
> - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
>
> vtd_spte_rsvd_large[0] = ~0ULL;
> - vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
>
> if (x86_iommu_ir_supported(x86_iommu)) {
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index c1235a7063..3a839a8925 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
> #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
>
> /* Rsvd field masks for spte */
> -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
> +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
> (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
> (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
> #define VTD_SL_W (1ULL << 1)
> #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
> #define VTD_SL_IGN_COM 0xbff0000000000000ULL
> +#define VTD_SL_TM (1ULL << 62)
>
> #endif
> --
> 2.20.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 0/2] TM field check failed
@ 2019-11-19 12:27 qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:27 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
spilt the reserved fields arrays and remove TM field from reserved
bits
Changelog V1:
add descriptons
Changelog V2:
refine
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 34 insertions(+), 18 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
@ 2019-11-19 12:27 ` qi1.zhang
2019-11-19 12:28 ` [PATCH v2 " qi1.zhang
2019-11-19 16:06 ` Peter Xu
2019-11-19 12:28 ` [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
3 siblings, 2 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:27 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
---
hw/i386/intel_iommu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..a118efaeaf 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
/* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
+ return slpte & vtd_spte_rsvd_large[level];
} else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ return slpte & vtd_spte_rsvd[level];
}
}
@@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[0] = ~0ULL;
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/2] intel_iommu: TM field should not be in reserved bits
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-11-19 11:06 ` Michael S. Tsirkin
@ 2019-11-19 12:27 ` qi1.zhang
1 sibling, 0 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:27 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 12 ++++++++----
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a118efaeaf..d62604ece3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd_large[0] = ~0ULL;
- vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..3a839a8925 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 0/2] TM field check failed
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
@ 2019-11-19 12:28 ` qi1.zhang
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
3 siblings, 0 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:28 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
spilt the reserved fields arrays and remove TM field from reserved
bits
Changelog V1:
add descriptons
Changelog V2:
refine
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 34 insertions(+), 18 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/2] intel_iommu: split the resevred fields arrays into two ones
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
@ 2019-11-19 12:28 ` qi1.zhang
2019-11-19 16:06 ` Peter Xu
1 sibling, 0 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:28 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
---
hw/i386/intel_iommu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..a118efaeaf 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
/* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
+ return slpte & vtd_spte_rsvd_large[level];
} else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ return slpte & vtd_spte_rsvd[level];
}
}
@@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[0] = ~0ULL;
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
` (2 preceding siblings ...)
2019-11-19 12:28 ` [PATCH v2 0/2] TM field check failed qi1.zhang
@ 2019-11-19 12:28 ` qi1.zhang
2019-11-19 11:06 ` Michael S. Tsirkin
2019-11-19 12:27 ` [PATCH " qi1.zhang
3 siblings, 2 replies; 14+ messages in thread
From: qi1.zhang @ 2019-11-19 12:28 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 12 ++++++++----
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a118efaeaf..d62604ece3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd_large[0] = ~0ULL;
- vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..3a839a8925 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/2] intel_iommu: split the resevred fields arrays into two ones
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-11-19 12:28 ` [PATCH v2 " qi1.zhang
@ 2019-11-19 16:06 ` Peter Xu
2019-11-22 8:10 ` Qi, Yadong
1 sibling, 1 reply; 14+ messages in thread
From: Peter Xu @ 2019-11-19 16:06 UTC (permalink / raw)
To: qi1.zhang; +Cc: ehabkost, mst, qemu-devel, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 08:28:13PM +0800, qi1.zhang@intel.com wrote:
> @@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
> /*
> * Rsvd field masks for spte
> */
> - vtd_paging_entry_rsvd_field[0] = ~0ULL;
> - vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> - vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[0] = ~0ULL;
> + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> +
> + vtd_spte_rsvd_large[0] = ~0ULL;
> + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
This looks good to me in general, but... Since we're at it, do you
think we can directly drop VTD_SPTE_LPAGE_L1_RSVD_MASK and
VTD_SPTE_LPAGE_L4_RSVD_MASK? Are they really useful?
I think I'm using the latest vt-d spec now (June, 2019) and it only
supports 2M/1G huge pages, corresponds to VTD_SPTE_LPAGE_L2_RSVD_MASK
and VTD_SPTE_LPAGE_L3_RSVD_MASK.
--
Peter Xu
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/2] TM field check failed
2019-11-19 11:05 ` Michael S. Tsirkin
@ 2019-11-19 16:21 ` Peter Xu
2019-11-19 16:39 ` Michael S. Tsirkin
0 siblings, 1 reply; 14+ messages in thread
From: Peter Xu @ 2019-11-19 16:21 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qi1.zhang, ehabkost, qemu-devel, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > From: "Zhang, Qi" <qi1.zhang@intel.com>
> >
> > spilt the reserved fields arrays and remove TM field from reserved
> > bits
>
> Looks good to me.
> Also Cc Peter Xu.
> Also I wonder - do we need to version this change
> with the machine type? Peter what's your take?
It should be a bugfix to me. With the patchset we check even less
reserved bits, then imho it shouldn't break any existing good users.
So we can probably skip versioning this change.
> Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
> and add everyone involved, this way people will
> remember to CC you?
Sure, I'll be fine with either way.
Thanks,
--
Peter Xu
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/2] TM field check failed
2019-11-19 16:21 ` Peter Xu
@ 2019-11-19 16:39 ` Michael S. Tsirkin
2019-11-19 17:01 ` Peter Xu
0 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2019-11-19 16:39 UTC (permalink / raw)
To: Peter Xu; +Cc: qi1.zhang, ehabkost, qemu-devel, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > >
> > > spilt the reserved fields arrays and remove TM field from reserved
> > > bits
> >
> > Looks good to me.
> > Also Cc Peter Xu.
> > Also I wonder - do we need to version this change
> > with the machine type? Peter what's your take?
>
> It should be a bugfix to me. With the patchset we check even less
> reserved bits, then imho it shouldn't break any existing good users.
> So we can probably skip versioning this change.
Can you ack this patch then?
> > Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
> > and add everyone involved, this way people will
> > remember to CC you?
>
> Sure, I'll be fine with either way.
>
> Thanks,
>
> --
> Peter Xu
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/2] TM field check failed
2019-11-19 16:39 ` Michael S. Tsirkin
@ 2019-11-19 17:01 ` Peter Xu
0 siblings, 0 replies; 14+ messages in thread
From: Peter Xu @ 2019-11-19 17:01 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qi1.zhang, ehabkost, qemu-devel, pbonzini, yadong.qi, rth
On Tue, Nov 19, 2019 at 11:39:04AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> > On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > > > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > > >
> > > > spilt the reserved fields arrays and remove TM field from reserved
> > > > bits
> > >
> > > Looks good to me.
> > > Also Cc Peter Xu.
> > > Also I wonder - do we need to version this change
> > > with the machine type? Peter what's your take?
> >
> > It should be a bugfix to me. With the patchset we check even less
> > reserved bits, then imho it shouldn't break any existing good users.
> > So we can probably skip versioning this change.
>
>
> Can you ack this patch then?
I've commented. I'll wait for a reply from Qi or a new version before
I ack it. Thanks,
--
Peter Xu
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH v2 1/2] intel_iommu: split the resevred fields arrays into two ones
2019-11-19 16:06 ` Peter Xu
@ 2019-11-22 8:10 ` Qi, Yadong
0 siblings, 0 replies; 14+ messages in thread
From: Qi, Yadong @ 2019-11-22 8:10 UTC (permalink / raw)
To: Peter Xu, Zhang, Qi1; +Cc: pbonzini, rth, mst, qemu-devel, ehabkost
> -----Original Message-----
> From: Peter Xu <peterx@redhat.com>
> Sent: Wednesday, November 20, 2019 12:06 AM
> To: Zhang, Qi1 <qi1.zhang@intel.com>
> Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com;
> pbonzini@redhat.com; Qi, Yadong <yadong.qi@intel.com>; rth@twiddle.net
> Subject: Re: [PATCH v2 1/2] intel_iommu: split the resevred fields arrays into
> two ones
>
> On Tue, Nov 19, 2019 at 08:28:13PM +0800, qi1.zhang@intel.com wrote:
> > @@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
> > /*
> > * Rsvd field masks for spte
> > */
> > - vtd_paging_entry_rsvd_field[0] = ~0ULL;
> > - vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s-
> >aw_bits);
> > - vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s-
> >aw_bits);
> > + vtd_spte_rsvd[0] = ~0ULL;
> > + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> > +
> > + vtd_spte_rsvd_large[0] = ~0ULL;
> > + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> > + vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
>
> This looks good to me in general, but... Since we're at it, do you think we can
> directly drop VTD_SPTE_LPAGE_L1_RSVD_MASK and
> VTD_SPTE_LPAGE_L4_RSVD_MASK? Are they really useful?
Yes, the LPAGE_L1 and LPAGE_L4 are useless. I will try to make the change.
Best Regard
Yadong
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones
2019-10-08 1:39 [PATCH 0/2] TM field check failed qi1.zhang
@ 2019-10-08 1:39 ` qi1.zhang
0 siblings, 0 replies; 14+ messages in thread
From: qi1.zhang @ 2019-10-08 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
---
hw/i386/intel_iommu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..a118efaeaf 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
/* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
+ return slpte & vtd_spte_rsvd_large[level];
} else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ return slpte & vtd_spte_rsvd[level];
}
}
@@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[0] = ~0ULL;
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
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2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
2019-11-19 16:21 ` Peter Xu
2019-11-19 16:39 ` Michael S. Tsirkin
2019-11-19 17:01 ` Peter Xu
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-11-19 12:28 ` [PATCH v2 " qi1.zhang
2019-11-19 16:06 ` Peter Xu
2019-11-22 8:10 ` Qi, Yadong
2019-11-19 12:28 ` [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-11-19 11:06 ` Michael S. Tsirkin
2019-11-19 12:27 ` [PATCH " qi1.zhang
-- strict thread matches above, loose matches on Subject: below --
2019-10-08 1:39 [PATCH 0/2] TM field check failed qi1.zhang
2019-10-08 1:39 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
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