* [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
@ 2021-03-31 15:00 Alistair Francis
2021-04-06 8:32 ` Bin Meng
2021-04-07 14:25 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Alistair Francis @ 2021-03-31 15:00 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 16 ++++++++--------
hw/intc/ibex_plic.c | 20 ++++++++++----------
hw/riscv/opentitan.c | 8 ++++----
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index a5ea3a5e4e..aab9bc9245 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -82,14 +82,14 @@ enum {
};
enum {
- IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
- IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
- IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
- IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
- IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
- IBEX_UART_TX_EMPTY_IRQ = 0x23,
- IBEX_UART_RX_WATERMARK_IRQ = 0x22,
- IBEX_UART_TX_WATERMARK_IRQ = 0x21,
+ IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+ IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+ IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+ IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+ IBEX_UART0_RX_OVERFLOW_IRQ = 4,
+ IBEX_UART0_TX_EMPTY_IRQ = 3,
+ IBEX_UART0_RX_WATERMARK_IRQ = 2,
+ IBEX_UART0_TX_WATERMARK_IRQ = 1,
};
#endif
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index c1b72fcab0..edf76e4f61 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
static Property ibex_plic_properties[] = {
DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+ DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+ DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+ DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
+ DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+ DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
+ DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+ DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
+ DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
+ DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+ DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e168bffe69..30dca1ee91 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -149,16 +149,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_WATERMARK_IRQ));
+ IBEX_UART0_TX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_WATERMARK_IRQ));
+ IBEX_UART0_RX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_EMPTY_IRQ));
+ IBEX_UART0_TX_EMPTY_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_OVERFLOW_IRQ));
+ IBEX_UART0_RX_OVERFLOW_IRQ));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
--
2.31.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
2021-03-31 15:00 [PATCH v1 1/1] hw/opentitan: Update the interrupt layout Alistair Francis
@ 2021-04-06 8:32 ` Bin Meng
2021-04-07 14:25 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Bin Meng @ 2021-04-06 8:32 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Wed, Mar 31, 2021 at 11:02 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Update the OpenTitan interrupt layout to match the latest OpenTitan
> bitstreams. This involves changing the Ibex PLIC memory layout and the
> UART interrupts.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 16 ++++++++--------
> hw/intc/ibex_plic.c | 20 ++++++++++----------
> hw/riscv/opentitan.c | 8 ++++----
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
LGTM
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
2021-03-31 15:00 [PATCH v1 1/1] hw/opentitan: Update the interrupt layout Alistair Francis
2021-04-06 8:32 ` Bin Meng
@ 2021-04-07 14:25 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-04-07 14:25 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Mar 31, 2021 at 11:02 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Update the OpenTitan interrupt layout to match the latest OpenTitan
> bitstreams. This involves changing the Ibex PLIC memory layout and the
> UART interrupts.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> include/hw/riscv/opentitan.h | 16 ++++++++--------
> hw/intc/ibex_plic.c | 20 ++++++++++----------
> hw/riscv/opentitan.c | 8 ++++----
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index a5ea3a5e4e..aab9bc9245 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -82,14 +82,14 @@ enum {
> };
>
> enum {
> - IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
> - IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
> - IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
> - IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
> - IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
> - IBEX_UART_TX_EMPTY_IRQ = 0x23,
> - IBEX_UART_RX_WATERMARK_IRQ = 0x22,
> - IBEX_UART_TX_WATERMARK_IRQ = 0x21,
> + IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
> + IBEX_UART0_RX_TIMEOUT_IRQ = 7,
> + IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
> + IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
> + IBEX_UART0_RX_OVERFLOW_IRQ = 4,
> + IBEX_UART0_TX_EMPTY_IRQ = 3,
> + IBEX_UART0_RX_WATERMARK_IRQ = 2,
> + IBEX_UART0_TX_WATERMARK_IRQ = 1,
> };
>
> #endif
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index c1b72fcab0..edf76e4f61 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
>
> static Property ibex_plic_properties[] = {
> DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
> - DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
> + DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
>
> DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
> - DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
> + DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
>
> - DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
> - DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
> + DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
> + DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
>
> - DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
> - DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
> + DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
> + DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
>
> - DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
> - DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
> + DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
> + DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
>
> - DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
> + DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
>
> - DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
> + DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index e168bffe69..30dca1ee91 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -149,16 +149,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
> 0, qdev_get_gpio_in(DEVICE(&s->plic),
> - IBEX_UART_TX_WATERMARK_IRQ));
> + IBEX_UART0_TX_WATERMARK_IRQ));
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
> 1, qdev_get_gpio_in(DEVICE(&s->plic),
> - IBEX_UART_RX_WATERMARK_IRQ));
> + IBEX_UART0_RX_WATERMARK_IRQ));
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
> 2, qdev_get_gpio_in(DEVICE(&s->plic),
> - IBEX_UART_TX_EMPTY_IRQ));
> + IBEX_UART0_TX_EMPTY_IRQ));
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
> 3, qdev_get_gpio_in(DEVICE(&s->plic),
> - IBEX_UART_RX_OVERFLOW_IRQ));
> + IBEX_UART0_RX_OVERFLOW_IRQ));
>
> create_unimplemented_device("riscv.lowrisc.ibex.gpio",
> memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
> --
> 2.31.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-04-07 14:31 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-31 15:00 [PATCH v1 1/1] hw/opentitan: Update the interrupt layout Alistair Francis
2021-04-06 8:32 ` Bin Meng
2021-04-07 14:25 ` Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).