From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
Date: Thu, 23 Jan 2020 10:43:37 -0800 (PST) [thread overview]
Message-ID: <mhng-ea4d4047-6dfa-4be0-8ce7-424b1d17560a@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <CAFEAcA9YoAjASu4F1hZRjbq5S+h8GtBUVb9dgecMdaWb9YENEw@mail.gmail.com>
On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote:
> On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>>
>> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>>
>> ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>>
>> are available in the Git repository at:
>>
>> git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>>
>> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>>
>> target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>>
>> ----------------------------------------------------------------
>> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>>
>> This patch set contains a handful of collected fixes that I'd like to target
>> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
>> else to call these):
>>
>> * A fix for a memory leak initializing the sifive_u board.
>> * Fixes to privilege mode emulation related to interrupts and fstatus.
>>
>> Notably absent is the H extension implementation. That's pretty much reviewed,
>> but not quite ready to go yet and I didn't want to hold back these important
>> fixes. This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
>> and passes "make check".
>
> Hi. This pull request doesn't seem to be signed with the GPG
> key that I have on record for you...
When I moved to Google I got a Yubikey and made new subkeys for it. If I
understand correctly the new subkeys should be signed by my main key, but maybe
that didn't make it to your keyring? I see
$ gpg --list-keys palmer@dabbelt.com
pub rsa4096 2017-06-06 [SC] [expires: 2027-11-13]
00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
uid [ultimate] Palmer Dabbelt <palmer@dabbelt.com>
uid [ultimate] Palmer Dabbelt <palmerdabbelt@google.com>
sub rsa4096 2017-06-06 [E]
sub rsa4096 2019-11-26 [S] [expires: 2024-11-24]
sub rsa4096 2019-11-26 [A] [expires: 2024-11-24]
sub rsa4096 2019-11-26 [E] [expires: 2024-11-24]
I have the master key at home, so if I didn't do this right I can re-spin
things tonight.
>
> thanks
> -- PMM
next prev parent reply other threads:[~2020-01-23 19:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-21 22:56 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Palmer Dabbelt
2020-01-21 22:56 ` [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize() Palmer Dabbelt
2020-01-21 22:56 ` [PULL 2/5] riscv: Set xPIE to 1 after xRET Palmer Dabbelt
2020-01-21 22:57 ` [PULL 3/5] target/riscv: Fix tb->flags FS status Palmer Dabbelt
2020-01-21 22:57 ` [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state Palmer Dabbelt
2020-01-21 22:57 ` [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty Palmer Dabbelt
2020-01-23 14:38 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Peter Maydell
2020-01-23 18:43 ` Palmer Dabbelt [this message]
2020-01-24 12:35 ` Peter Maydell
2020-01-27 19:23 ` Palmer Dabbelt
2020-01-24 13:22 ` Peter Maydell
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