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From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH 2/8] drm/i915: move dp_m_n computation to dp_encoder->compute_config
Date: Fri, 22 Feb 2013 01:04:59 +0100	[thread overview]
Message-ID: <1361491513-14231-5-git-send-email-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <1361491513-14231-1-git-send-email-daniel.vetter@ffwll.ch>

We need a flag to designate dp encoders and the dp link m_n parameters
in the pipe config for that. And now that the pipe bpp computations
have been moved up and stored in the pipe config, too, we can do this
without losing our sanity.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++-----------
 drivers/gpu/drm/i915/intel_dp.c      | 49 +++++++-----------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  3 ---
 3 files changed, 25 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8335fd5..ab4e52c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4125,6 +4125,14 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	}
 }
 
+static void intel_dp_set_m_n(struct intel_crtc *crtc)
+{
+	if (crtc->config.has_pch_encoder)
+		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+	else
+		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+}
+
 static void vlv_update_pll(struct drm_crtc *crtc,
 			   intel_clock_t *clock, intel_clock_t *reduced_clock,
 			   int num_connectors)
@@ -4132,9 +4140,6 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_display_mode *adjusted_mode =
-		&intel_crtc->config.adjusted_mode;
-	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
 	int pipe = intel_crtc->pipe;
 	u32 dpll, mdiv, pdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4190,8 +4195,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 
 	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
 
 	I915_WRITE(DPLL(pipe), dpll);
 
@@ -4237,9 +4242,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_display_mode *adjusted_mode =
-		&intel_crtc->config.adjusted_mode;
-	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	u32 dpll;
@@ -4314,8 +4316,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
 
 	I915_WRITE(DPLL(pipe), dpll);
 
@@ -5529,8 +5531,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	} else
 		intel_put_pch_pll(intel_crtc);
 
-	if (is_dp)
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_pll_enable)
@@ -5674,8 +5676,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
 	drm_mode_debug_printmodeline(mode);
 
-	if (is_dp)
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
 
 	intel_crtc->lowfreq_avail = false;
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a4caf1e..1920fae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -193,6 +193,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
 
 		if (mode->vdisplay > fixed_mode->vdisplay)
 			return MODE_PANEL;
+
+		target_clock = fixed_mode->clock;
 	}
 
 	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
@@ -688,6 +690,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (HAS_PCH_SPLIT(dev) && !IS_HASWELL(dev) && !is_cpu_edp(intel_dp))
 		pipe_config->has_pch_encoder = true;
 
+	pipe_config->has_dp_encoder = true;
+
 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 				       adjusted_mode);
@@ -707,7 +711,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 	 * bpc in between. */
-	bpp = 8*3;
+	bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 	if (is_edp(intel_dp) && dev_priv->edp.bpp)
 		bpp = min_t(int, bpp, dev_priv->edp.bpp);
 
@@ -756,46 +760,11 @@ found:
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
 
-	return true;
-}
-
-void
-intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
-		 struct drm_display_mode *adjusted_mode)
-{
-	struct drm_device *dev = crtc->dev;
-	struct intel_encoder *intel_encoder;
-	struct intel_dp *intel_dp;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int lane_count = 4;
-	struct intel_link_m_n m_n;
+	intel_link_compute_m_n(bpp, lane_count,
+			       target_clock, adjusted_mode->clock,
+			       &pipe_config->dp_m_n);
 
-	/*
-	 * Find the lane count in the intel_encoder private
-	 */
-	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
-		intel_dp = enc_to_intel_dp(&intel_encoder->base);
-
-		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
-		    intel_encoder->type == INTEL_OUTPUT_EDP)
-		{
-			lane_count = intel_dp->lane_count;
-			break;
-		}
-	}
-
-	/*
-	 * Compute the GMCH and Link ratios. The '3' here is
-	 * the number of bytes_per_pixel post-LUT, which we always
-	 * set up for 8-bits of R/G/B, or 3 bytes total.
-	 */
-	intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
-			       mode->clock, adjusted_mode->clock, &m_n);
-
-	if (intel_crtc->config.has_pch_encoder)
-		intel_pch_transcoder_set_m_n(intel_crtc, &m_n);
-	else
-		intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
+	return true;
 }
 
 void intel_dp_init_link_config(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index aa4dee4..76c5273 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -468,9 +468,6 @@ extern void intel_dp_init(struct drm_device *dev, int output_reg,
 			  enum port port);
 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 				    struct intel_connector *intel_connector);
-void
-intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
-		 struct drm_display_mode *adjusted_mode);
 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
-- 
1.7.11.4

  parent reply	other threads:[~2013-02-22  0:05 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-22  0:04 [PATCH 00/10] bpc handling fixes Daniel Vetter
2013-02-22  0:04 ` [PATCH 1/8] drm/i915: clear up the fdi/dp set_m_n confusion Daniel Vetter
2013-02-22  0:04 ` [PATCH 01/10] drm/i915: use pipe_config for lvds dithering Daniel Vetter
2013-02-22  0:04 ` [PATCH 02/10] drm/i915: consolidate pch pll computations a bit Daniel Vetter
2013-02-22  0:04 ` Daniel Vetter [this message]
2013-02-22  0:05 ` [PATCH 03/10] drm/i915: fixup 12bpc hdmi dotclock handling Daniel Vetter
2013-02-22  0:05 ` [PATCH 3/8] drm/i915: track dp target_clock in pipe_config Daniel Vetter
2013-02-22  0:05 ` [PATCH 04/10] drm/i915: Disable high-bpc on pre-1.4 EDID screens Daniel Vetter
2013-02-22  0:05 ` [PATCH 4/8] drm/i915: rip out superflous is_dp&is_cpu_edp tracking Daniel Vetter
2013-02-22  0:05 ` [PATCH 5/8] drm/i915: add hw state readout/checking for pipe_config Daniel Vetter
2013-02-22  0:05 ` [PATCH 05/10] drm/i915: force bpp for eDP panels Daniel Vetter
2013-02-22  6:50   ` Jani Nikula
2013-02-22 11:10     ` [PATCH] " Daniel Vetter
2013-02-22  0:05 ` [PATCH 06/10] drm/i915: extract i9xx_set_pipeconf Daniel Vetter
2013-02-22  0:05 ` [PATCH 6/8] drm/i915: hw readout support for ->has_pch_encoders Daniel Vetter
2013-02-22  0:05 ` [PATCH 7/8] drm/i915: create pipe_config->dpll for clock state Daniel Vetter
2013-02-22  0:05 ` [PATCH 07/10] drm/i915: drop adjusted_mode from *_set_pipeconf functions Daniel Vetter
2013-02-22  0:05 ` [PATCH 08/10] drm/i915: implement high-bpc + pipeconf-dither support for g4x/vlv Daniel Vetter
2013-02-22  0:05 ` [PATCH 8/8] drm/i915: move dp clock computations to encoder->compute_config Daniel Vetter
2013-02-22  0:05 ` [PATCH 09/10] drm/i915: allow high-bpc modes on DP Daniel Vetter
2013-02-22  0:05 ` [PATCH 10/10] drm/i915: Fixup non-24bpp support for VGA screens on Haswell Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2013-03-28  9:41 [PATCH 0/8] dp/fdi m/n rework + basic pipe_config readout Daniel Vetter
2013-03-28  9:41 ` [PATCH 2/8] drm/i915: move dp_m_n computation to dp_encoder->compute_config Daniel Vetter
2013-04-02 20:51   ` Jesse Barnes
2013-02-22  0:00 [PATCH 0/8] fdi/dp m_n reorg and a few other clock changes Daniel Vetter
2013-02-22  0:00 ` [PATCH 2/8] drm/i915: move dp_m_n computation to dp_encoder->compute_config Daniel Vetter

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