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From: Chen-Yu Tsai <wens@csie.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Samuel Ortiz <sameo@linux.intel.com>,
	Lee Jones <lee.jones@linaro.org>,
	Maxime Ripard <maxime.ripard@free-electrons.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mike Turquette <mturquette@linaro.org>,
	Emilio Lopez <emilio@elopez.com.ar>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
	linux-serial@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
	Boris BREZILLON <boris.brezillon@free-electrons.com>,
	Luc Verhaegen <libv@skynet.be>
Subject: [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Date: Fri, 23 May 2014 15:51:12 +0800	[thread overview]
Message-ID: <1400831485-28576-10-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.

This behavior is consistent with previous SoC's by Allwinner.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6857c6e..339cabc 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -496,6 +496,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
+	.name = "pll6",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
@@ -969,6 +970,14 @@ static const struct divs_data pll6_divs_data __initconst = {
 	}
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+	.factors = &sun6i_a31_pll6_data,
+	.ndivs = 1,
+	.div = {
+		{ .fixed = 2 }, /* P, other */
+	}
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -1108,7 +1117,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
 	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
@@ -1128,6 +1136,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
 	{}
 };
 
-- 
2.0.0.rc2


WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Samuel Ortiz <sameo@linux.intel.com>,
	Lee Jones <lee.jones@linaro.org>,
	Maxime Ripard <maxime.ripard@free-electrons.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mike Turquette <mturquette@linaro.org>,
	Emilio Lopez <emilio@elopez.com.ar>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org,
	Boris BREZILLON <boris.brezillon@free-electrons.com>,
	Luc Verhaegen <libv@skynet.be>,
	linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
	Chen-Yu Tsai <wens@csie.org>,
	linux-serial@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Date: Fri, 23 May 2014 15:51:12 +0800	[thread overview]
Message-ID: <1400831485-28576-10-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.

This behavior is consistent with previous SoC's by Allwinner.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6857c6e..339cabc 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -496,6 +496,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
+	.name = "pll6",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
@@ -969,6 +970,14 @@ static const struct divs_data pll6_divs_data __initconst = {
 	}
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+	.factors = &sun6i_a31_pll6_data,
+	.ndivs = 1,
+	.div = {
+		{ .fixed = 2 }, /* P, other */
+	}
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -1108,7 +1117,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
 	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
@@ -1128,6 +1136,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
 	{}
 };
 
-- 
2.0.0.rc2

WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Date: Fri, 23 May 2014 15:51:12 +0800	[thread overview]
Message-ID: <1400831485-28576-10-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.

This behavior is consistent with previous SoC's by Allwinner.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6857c6e..339cabc 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -496,6 +496,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
+	.name = "pll6",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
@@ -969,6 +970,14 @@ static const struct divs_data pll6_divs_data __initconst = {
 	}
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+	.factors = &sun6i_a31_pll6_data,
+	.ndivs = 1,
+	.div = {
+		{ .fixed = 2 }, /* P, other */
+	}
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -1108,7 +1117,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
 	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
@@ -1128,6 +1136,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
 	{}
 };
 
-- 
2.0.0.rc2

  parent reply	other threads:[~2014-05-23  8:27 UTC|newest]

Thread overview: 153+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-23  7:51 [PATCH 00/21] ARM: sunxi: Introduce Allwinner A23 (sun8i) support Chen-Yu Tsai
2014-05-23  7:51 ` Chen-Yu Tsai
2014-05-23  7:51 ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 01/22] serial: 8250_dw: Add optional reset control support Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  8:19   ` Arnd Bergmann
2014-05-23  8:19     ` Arnd Bergmann
2014-05-23  7:51 ` [PATCH 02/22] clk: sunxi: register clock gates with clkdev Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:47   ` Maxime Ripard
2014-05-25 18:47     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 03/22] clk: sunxi: add "pll6" to sun6i protected clock list Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:48   ` Maxime Ripard
2014-05-25 18:48     ` Maxime Ripard
2014-05-26  4:47     ` Chen-Yu Tsai
2014-05-26  4:47       ` Chen-Yu Tsai
2014-05-26  4:47       ` Chen-Yu Tsai
2014-05-27  8:32       ` Maxime Ripard
2014-05-27  8:32         ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 04/22] clk: sunxi: move "ahb_sdram" to " Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:51   ` Maxime Ripard
2014-05-25 18:51     ` Maxime Ripard
2014-05-26  9:43     ` Chen-Yu Tsai
2014-05-26  9:43       ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 05/22] clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 06/22] clk: sunxi: Support factor clocks with N multiplier factor starting from 1 Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:43   ` Maxime Ripard
2014-05-25 18:43     ` Maxime Ripard
2014-05-25 18:43     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 07/22] clk: sunxi: Fix PLL6 calculation on sun6i Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23 13:09   ` Emilio López
2014-05-23 13:09     ` Emilio López
2014-05-23 13:09     ` Emilio López
2014-05-23 14:43     ` Chen-Yu Tsai
2014-05-23 14:43       ` Chen-Yu Tsai
2014-05-23 14:43       ` Chen-Yu Tsai
2014-05-25 18:43   ` Maxime Ripard
2014-05-25 18:43     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 08/22] clk: sunxi: Specify number of child clocks for divs clocks Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51 ` Chen-Yu Tsai [this message]
2014-05-23  7:51   ` [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:56   ` Maxime Ripard
2014-05-25 18:56     ` Maxime Ripard
2014-05-25 18:56     ` Maxime Ripard
2014-05-26  3:47     ` Chen-Yu Tsai
2014-05-26  3:47       ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 10/22] clk: sunxi: Add support for PLL6 pre-divider on AHB1 clock Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:02   ` Maxime Ripard
2014-05-25 19:02     ` Maxime Ripard
2014-05-25 19:02     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 11/22] ARM: sun6i: DT: Add PLL6 multiple outputs Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:59   ` Maxime Ripard
2014-05-25 18:59     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 12/22] ARM: sun6i: DT: Add PLL6 pre-divider clock for AHB1 mux input Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 13/22] clk: sunxi: Add A23 clocks support Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:05   ` Maxime Ripard
2014-05-25 19:05     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 14/22] clk: sunxi: Add A23 APB0 support to sun6i-a31-apb0-clk Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 15/22] pinctrl: sunxi: Add A23 PIO controller support Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:08   ` Maxime Ripard
2014-05-25 19:08     ` Maxime Ripard
2014-06-17 10:25     ` Chen-Yu Tsai
2014-06-17 10:25       ` Chen-Yu Tsai
2014-06-17 10:25       ` Chen-Yu Tsai
2014-06-17 14:18       ` Maxime Ripard
2014-06-17 14:18         ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 16/22] pinctrl: sunxi: Add A23 R_PIO " Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:11   ` Maxime Ripard
2014-05-25 19:11     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 17/22] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:14   ` Maxime Ripard
2014-05-25 19:14     ` Maxime Ripard
2014-05-26  4:36     ` Chen-Yu Tsai
2014-05-26  4:36       ` Chen-Yu Tsai
2014-05-27  8:30       ` Maxime Ripard
2014-05-27  8:30         ` Maxime Ripard
2014-05-29  4:23         ` Chen-Yu Tsai
2014-05-29  4:23           ` Chen-Yu Tsai
2014-05-29 19:31           ` Maxime Ripard
2014-05-29 19:31             ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 18/22] ARM: sunxi: Introduce Allwinner A23 support Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:22   ` Maxime Ripard
2014-05-25 19:22     ` Maxime Ripard
2014-05-25 19:22     ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 19/22] ARM: sunxi: Add earlyprintk support using R_UART (sun6i/sun8i) Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 18:46   ` Maxime Ripard
2014-05-25 18:46     ` Maxime Ripard
2014-05-26  9:25     ` Chen-Yu Tsai
2014-05-26  9:25       ` Chen-Yu Tsai
2014-05-27  8:34       ` Maxime Ripard
2014-05-27  8:34         ` Maxime Ripard
2014-05-23  7:51 ` [PATCH 20/22] ARM: sun8i: Add SMP support for the Allwinner A23 Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:26   ` Maxime Ripard
2014-05-25 19:26     ` Maxime Ripard
2014-05-26  3:57     ` Chen-Yu Tsai
2014-05-26  3:57       ` Chen-Yu Tsai
2014-05-27  8:09       ` Marc Zyngier
2014-05-27  8:09         ` Marc Zyngier
2014-05-27  8:09         ` Marc Zyngier
2014-05-23  7:51 ` [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:38   ` Maxime Ripard
2014-05-25 19:38     ` Maxime Ripard
2014-05-26  4:02     ` Chen-Yu Tsai
2014-05-26  4:02       ` Chen-Yu Tsai
2014-05-23  7:51 ` [PATCH 22/22] ARM: sun8i: dt: Add Ippo-q8h v5 support Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-23  7:51   ` Chen-Yu Tsai
2014-05-25 19:39   ` Maxime Ripard
2014-05-25 19:39     ` Maxime Ripard
2014-05-26  4:23     ` Chen-Yu Tsai
2014-05-26  4:23       ` Chen-Yu Tsai
2014-05-26  4:23       ` Chen-Yu Tsai
2014-05-27  8:22       ` Maxime Ripard
2014-05-27  8:22         ` Maxime Ripard

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