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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu
Subject: [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 23 Mar 2015 17:05:41 +0000	[thread overview]
Message-ID: <1427130344-27986-4-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>

As there is logic to deal with the difference between edge and level
triggered interrupts in the kernel we must ensure it knows the
configuration of the IRQs before we restore the pending state.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 0d20750..e2512f1 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
      * the appropriate CPU interfaces in the kernel) */
     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 
+    /* irq_state[n].trigger -> GICD_ICFGRn
+     * (restore targets before pending IRQs so we treat level/edge
+     * correctly */
+    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
+
     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
@@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 
-    /* irq_state[n].trigger -> GICD_ICFRn */
-    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 
     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
-- 
2.3.2

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WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com,
	linux-arm-kernel@lists.infradead.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org
Subject: [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 23 Mar 2015 17:05:41 +0000	[thread overview]
Message-ID: <1427130344-27986-4-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>

As there is logic to deal with the difference between edge and level
triggered interrupts in the kernel we must ensure it knows the
configuration of the IRQs before we restore the pending state.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 0d20750..e2512f1 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
      * the appropriate CPU interfaces in the kernel) */
     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 
+    /* irq_state[n].trigger -> GICD_ICFGRn
+     * (restore targets before pending IRQs so we treat level/edge
+     * correctly */
+    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
+
     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
@@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 
-    /* irq_state[n].trigger -> GICD_ICFRn */
-    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 
     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
-- 
2.3.2

WARNING: multiple messages have this Message-ID (diff)
From: alex.bennee@linaro.org (Alex Bennée)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 23 Mar 2015 17:05:41 +0000	[thread overview]
Message-ID: <1427130344-27986-4-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>

As there is logic to deal with the difference between edge and level
triggered interrupts in the kernel we must ensure it knows the
configuration of the IRQs before we restore the pending state.

Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 0d20750..e2512f1 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
      * the appropriate CPU interfaces in the kernel) */
     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 
+    /* irq_state[n].trigger -> GICD_ICFGRn
+     * (restore targets before pending IRQs so we treat level/edge
+     * correctly */
+    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
+
     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
@@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 
-    /* irq_state[n].trigger -> GICD_ICFRn */
-    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 
     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
-- 
2.3.2

  parent reply	other threads:[~2015-03-23 17:05 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-23 17:05 [PATCH v5 0/6] QEMU ARM64 Migration Fixes Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-23 17:05 ` [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) Alex Bennée
2015-03-23 17:05   ` Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-24 14:32   ` Greg Bellows
2015-03-24 14:32     ` Greg Bellows
2015-03-24 14:32     ` Greg Bellows
2015-03-24 14:37     ` Peter Maydell
2015-03-24 14:37       ` Peter Maydell
2015-03-24 14:37       ` Peter Maydell
2015-03-23 17:05 ` [PATCH v5 2/6] target-arm: kvm: save/restore mp state Alex Bennée
2015-03-23 17:05   ` Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-26 17:11   ` Peter Maydell
2015-03-26 17:11     ` Peter Maydell
2015-03-26 17:11     ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` Alex Bennée [this message]
2015-03-23 17:05   ` [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-26 17:12   ` Peter Maydell
2015-03-26 17:12     ` Peter Maydell
2015-03-26 17:12     ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 4/6] target-arm: kvm64 sync FP register state Alex Bennée
2015-03-23 17:05   ` Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-26 17:20   ` Peter Maydell
2015-03-26 17:20     ` Peter Maydell
2015-03-26 17:20     ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 5/6] target-arm: kvm64 fix save/restore of SPSR regs Alex Bennée
2015-03-23 17:05   ` Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-26 17:25   ` Peter Maydell
2015-03-26 17:25     ` Peter Maydell
2015-03-26 17:25     ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists Alex Bennée
2015-03-23 17:05   ` Alex Bennée
2015-03-23 17:05   ` [Qemu-devel] " Alex Bennée
2015-03-26 17:26   ` Peter Maydell
2015-03-26 17:26     ` Peter Maydell
2015-03-26 17:26     ` [Qemu-devel] " Peter Maydell

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