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From: Zhi Wang <zhi.a.wang@intel.com>
To: chris@chris-wilson.co.uk, zhiyuan.lv@intel.com,
	kevin.tian@intel.com, tvrtko.ursulin@linux.intel.com,
	intel-gfx@lists.freedesktop.org
Subject: [PATCH v8 07/10] drm/i915: Make addressing mode bits in context descriptor configurable
Date: Wed,  8 Jun 2016 11:30:25 -0400	[thread overview]
Message-ID: <1465399828-17082-8-git-send-email-zhi.a.wang@intel.com> (raw)
In-Reply-To: <1465399828-17082-1-git-send-email-zhi.a.wang@intel.com>

Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.

GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a LRC context should be configurable under this case.

v8:

- Rename the data memeber in struct i915_gem_context. (Chris)

v7:

- Move context addressing mode bit into i915_reg.h. (Joonas/Chris)
- Add prefix "INTEL_" for related definitions. (Joonas)

v6:

- Directly save the addressing mode bits inside i915_gem_context. (Chris)
- Move the LRC context addressing mode bits into intel_lrc.h. (Chris)

v5:

- Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c |  2 ++
 drivers/gpu/drm/i915/i915_reg.h         | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c        | 13 +------------
 4 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66fdb8d..6a79c8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -879,6 +879,7 @@ struct i915_gem_context {
 		bool initialised;
 	} engine[I915_NUM_ENGINES];
 	u32 ring_size;
+	u32 addressing_mode;
 
 	struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b722fa1..821f550 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -296,6 +296,8 @@ __create_hw_context(struct drm_device *dev,
 
 	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
 	ctx->ring_size = 4 * PAGE_SIZE;
+	ctx->addressing_mode = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
+		GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
 	return ctx;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f0129d..4a6fe6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3022,6 +3022,18 @@ enum skl_disp_power_wells {
 /* Same as Haswell, but 72064 bytes now. */
 #define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
 
+enum {
+	INTEL_ADVANCED_CONTEXT = 0,
+	INTEL_LEGACY_32B_CONTEXT,
+	INTEL_ADVANCED_AD_CONTEXT,
+	INTEL_LEGACY_64B_CONTEXT
+};
+
+#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\
+		INTEL_LEGACY_64B_CONTEXT : \
+		INTEL_LEGACY_32B_CONTEXT)
+
 #define CHV_CLK_CTL1			_MMIO(0x101100)
 #define VLV_CLK_CTL2			_MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 344b5d3..0652132 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -208,16 +208,6 @@
 } while (0)
 
 enum {
-	ADVANCED_CONTEXT = 0,
-	LEGACY_32B_CONTEXT,
-	ADVANCED_AD_CONTEXT,
-	LEGACY_64B_CONTEXT
-};
-#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
-#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
-		LEGACY_64B_CONTEXT :\
-		LEGACY_32B_CONTEXT)
-enum {
 	FAULT_AND_HANG = 0,
 	FAULT_AND_HALT, /* Debug only */
 	FAULT_AND_STREAM,
@@ -281,8 +271,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
 					(engine->id == VCS || engine->id == VCS2);
 
 	engine->ctx_desc_template = GEN8_CTX_VALID;
-	engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
-				   GEN8_CTX_ADDRESSING_MODE_SHIFT;
 	if (IS_GEN8(dev_priv))
 		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
 	engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -326,6 +314,7 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
 
 	desc = engine->ctx_desc_template;			/* bits  0-11 */
+	desc |= ctx->addressing_mode;				/* bits  3-4  */
 	desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
 								/* bits 12-31 */
 	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
-- 
1.9.1

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  parent reply	other threads:[~2016-06-08 15:30 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-08 15:30 [PATCH v8 00/10] Introduce the implementation of GVT context Zhi Wang
2016-06-08 15:30 ` [PATCH v8 01/10] drm/i915: Factor out i915_pvinfo.h Zhi Wang
2016-06-08 15:30 ` [PATCH v8 02/10] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page Zhi Wang
2016-06-08 15:30 ` [PATCH v8 03/10] drm/i915: Fold vGPU active check into inner functions Zhi Wang
2016-06-08 15:30 ` [PATCH v8 04/10] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-06-08 15:30 ` [PATCH v8 05/10] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
2016-06-08 15:30 ` [PATCH v8 06/10] drm/i915: Make ring buffer size of a LRC context configurable Zhi Wang
2016-06-08 16:03   ` Chris Wilson
2016-06-08 15:30 ` Zhi Wang [this message]
2016-06-08 16:08   ` [PATCH v8 07/10] drm/i915: Make addressing mode bits in context descriptor configurable Chris Wilson
2016-06-08 16:13     ` Wang, Zhi A
2016-06-08 15:30 ` [PATCH v8 08/10] drm/i915: Introduce execlist context status change notification Zhi Wang
2016-06-08 15:30 ` [PATCH v8 09/10] drm/i915: Support LRC context single submission Zhi Wang
2016-06-08 15:30 ` [PATCH v8 10/10] drm/i915: Introduce GVT context creation API Zhi Wang
2016-06-08 16:00 ` ✗ Ro.CI.BAT: warning for Introduce the implementation of GVT context (rev6) Patchwork
2016-06-08 16:00 ` [PATCH v8 00/10] Introduce the implementation of GVT context Chris Wilson
2016-06-08 16:05   ` Wang, Zhi A

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