From: Douglas Anderson <dianders@chromium.org>
To: ulf.hansson@linaro.org, Heiko Stuebner <heiko@sntech.de>
Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com,
xzy.xu@rock-chips.com, briannorris@chromium.org,
adrian.hunter@intel.com, linux-rockchip@lists.infradead.org,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
groeck@chromium.org, Douglas Anderson <dianders@chromium.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions
Date: Mon, 20 Jun 2016 10:56:43 -0700 [thread overview]
Message-ID: <1466445414-11974-5-git-send-email-dianders@chromium.org> (raw)
In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org>
From: Brian Norris <briannorris@chromium.org>
Some of the spacing was wrong (spaces instead of tabs), and due to
longer entries added later, the columns weren't aligned. Let's get
everything consistent.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v3:
- Add Brian's PHY patches into my series
Changes in v2: None
drivers/phy/phy-rockchip-emmc.c | 76 ++++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
index a0b87cc6c818..a69f53630e67 100644
--- a/drivers/phy/phy-rockchip-emmc.c
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -31,44 +31,44 @@
((val) << (shift) | (mask) << ((shift) + 16))
/* Register definition */
-#define GRF_EMMCPHY_CON0 0x0
-#define GRF_EMMCPHY_CON1 0x4
-#define GRF_EMMCPHY_CON2 0x8
-#define GRF_EMMCPHY_CON3 0xc
-#define GRF_EMMCPHY_CON4 0x10
-#define GRF_EMMCPHY_CON5 0x14
-#define GRF_EMMCPHY_CON6 0x18
-#define GRF_EMMCPHY_STATUS 0x20
-
-#define PHYCTRL_PDB_MASK 0x1
-#define PHYCTRL_PDB_SHIFT 0x0
-#define PHYCTRL_PDB_PWR_ON 0x1
-#define PHYCTRL_PDB_PWR_OFF 0x0
-#define PHYCTRL_ENDLL_MASK 0x1
-#define PHYCTRL_ENDLL_SHIFT 0x1
-#define PHYCTRL_ENDLL_ENABLE 0x1
-#define PHYCTRL_ENDLL_DISABLE 0x0
-#define PHYCTRL_CALDONE_MASK 0x1
-#define PHYCTRL_CALDONE_SHIFT 0x6
-#define PHYCTRL_CALDONE_DONE 0x1
-#define PHYCTRL_CALDONE_GOING 0x0
-#define PHYCTRL_DLLRDY_MASK 0x1
-#define PHYCTRL_DLLRDY_SHIFT 0x5
-#define PHYCTRL_DLLRDY_DONE 0x1
-#define PHYCTRL_DLLRDY_GOING 0x0
-#define PHYCTRL_FREQSEL_200M 0x0
-#define PHYCTRL_FREQSEL_50M 0x1
-#define PHYCTRL_FREQSEL_100M 0x2
-#define PHYCTRL_FREQSEL_150M 0x3
-#define PHYCTRL_FREQSEL_MASK 0x3
-#define PHYCTRL_FREQSEL_SHIFT 0xc
-#define PHYCTRL_DR_MASK 0x7
-#define PHYCTRL_DR_SHIFT 0x4
-#define PHYCTRL_DR_50OHM 0x0
-#define PHYCTRL_DR_33OHM 0x1
-#define PHYCTRL_DR_66OHM 0x2
-#define PHYCTRL_DR_100OHM 0x3
-#define PHYCTRL_DR_40OHM 0x4
+#define GRF_EMMCPHY_CON0 0x0
+#define GRF_EMMCPHY_CON1 0x4
+#define GRF_EMMCPHY_CON2 0x8
+#define GRF_EMMCPHY_CON3 0xc
+#define GRF_EMMCPHY_CON4 0x10
+#define GRF_EMMCPHY_CON5 0x14
+#define GRF_EMMCPHY_CON6 0x18
+#define GRF_EMMCPHY_STATUS 0x20
+
+#define PHYCTRL_PDB_MASK 0x1
+#define PHYCTRL_PDB_SHIFT 0x0
+#define PHYCTRL_PDB_PWR_ON 0x1
+#define PHYCTRL_PDB_PWR_OFF 0x0
+#define PHYCTRL_ENDLL_MASK 0x1
+#define PHYCTRL_ENDLL_SHIFT 0x1
+#define PHYCTRL_ENDLL_ENABLE 0x1
+#define PHYCTRL_ENDLL_DISABLE 0x0
+#define PHYCTRL_CALDONE_MASK 0x1
+#define PHYCTRL_CALDONE_SHIFT 0x6
+#define PHYCTRL_CALDONE_DONE 0x1
+#define PHYCTRL_CALDONE_GOING 0x0
+#define PHYCTRL_DLLRDY_MASK 0x1
+#define PHYCTRL_DLLRDY_SHIFT 0x5
+#define PHYCTRL_DLLRDY_DONE 0x1
+#define PHYCTRL_DLLRDY_GOING 0x0
+#define PHYCTRL_FREQSEL_200M 0x0
+#define PHYCTRL_FREQSEL_50M 0x1
+#define PHYCTRL_FREQSEL_100M 0x2
+#define PHYCTRL_FREQSEL_150M 0x3
+#define PHYCTRL_FREQSEL_MASK 0x3
+#define PHYCTRL_FREQSEL_SHIFT 0xc
+#define PHYCTRL_DR_MASK 0x7
+#define PHYCTRL_DR_SHIFT 0x4
+#define PHYCTRL_DR_50OHM 0x0
+#define PHYCTRL_DR_33OHM 0x1
+#define PHYCTRL_DR_66OHM 0x2
+#define PHYCTRL_DR_100OHM 0x3
+#define PHYCTRL_DR_40OHM 0x4
#define PHYCTRL_OTAPDLYENA 0x1
#define PHYCTRL_OTAPDLYENA_MASK 0x1
#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
--
2.8.0.rc3.226.g39d4020
WARNING: multiple messages have this Message-ID (diff)
From: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: Douglas Anderson
<dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
kishon-l0cyMroinI0@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
groeck-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions
Date: Mon, 20 Jun 2016 10:56:43 -0700 [thread overview]
Message-ID: <1466445414-11974-5-git-send-email-dianders@chromium.org> (raw)
In-Reply-To: <1466445414-11974-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Some of the spacing was wrong (spaces instead of tabs), and due to
longer entries added later, the columns weren't aligned. Let's get
everything consistent.
Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Acked-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
Changes in v3:
- Add Brian's PHY patches into my series
Changes in v2: None
drivers/phy/phy-rockchip-emmc.c | 76 ++++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
index a0b87cc6c818..a69f53630e67 100644
--- a/drivers/phy/phy-rockchip-emmc.c
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -31,44 +31,44 @@
((val) << (shift) | (mask) << ((shift) + 16))
/* Register definition */
-#define GRF_EMMCPHY_CON0 0x0
-#define GRF_EMMCPHY_CON1 0x4
-#define GRF_EMMCPHY_CON2 0x8
-#define GRF_EMMCPHY_CON3 0xc
-#define GRF_EMMCPHY_CON4 0x10
-#define GRF_EMMCPHY_CON5 0x14
-#define GRF_EMMCPHY_CON6 0x18
-#define GRF_EMMCPHY_STATUS 0x20
-
-#define PHYCTRL_PDB_MASK 0x1
-#define PHYCTRL_PDB_SHIFT 0x0
-#define PHYCTRL_PDB_PWR_ON 0x1
-#define PHYCTRL_PDB_PWR_OFF 0x0
-#define PHYCTRL_ENDLL_MASK 0x1
-#define PHYCTRL_ENDLL_SHIFT 0x1
-#define PHYCTRL_ENDLL_ENABLE 0x1
-#define PHYCTRL_ENDLL_DISABLE 0x0
-#define PHYCTRL_CALDONE_MASK 0x1
-#define PHYCTRL_CALDONE_SHIFT 0x6
-#define PHYCTRL_CALDONE_DONE 0x1
-#define PHYCTRL_CALDONE_GOING 0x0
-#define PHYCTRL_DLLRDY_MASK 0x1
-#define PHYCTRL_DLLRDY_SHIFT 0x5
-#define PHYCTRL_DLLRDY_DONE 0x1
-#define PHYCTRL_DLLRDY_GOING 0x0
-#define PHYCTRL_FREQSEL_200M 0x0
-#define PHYCTRL_FREQSEL_50M 0x1
-#define PHYCTRL_FREQSEL_100M 0x2
-#define PHYCTRL_FREQSEL_150M 0x3
-#define PHYCTRL_FREQSEL_MASK 0x3
-#define PHYCTRL_FREQSEL_SHIFT 0xc
-#define PHYCTRL_DR_MASK 0x7
-#define PHYCTRL_DR_SHIFT 0x4
-#define PHYCTRL_DR_50OHM 0x0
-#define PHYCTRL_DR_33OHM 0x1
-#define PHYCTRL_DR_66OHM 0x2
-#define PHYCTRL_DR_100OHM 0x3
-#define PHYCTRL_DR_40OHM 0x4
+#define GRF_EMMCPHY_CON0 0x0
+#define GRF_EMMCPHY_CON1 0x4
+#define GRF_EMMCPHY_CON2 0x8
+#define GRF_EMMCPHY_CON3 0xc
+#define GRF_EMMCPHY_CON4 0x10
+#define GRF_EMMCPHY_CON5 0x14
+#define GRF_EMMCPHY_CON6 0x18
+#define GRF_EMMCPHY_STATUS 0x20
+
+#define PHYCTRL_PDB_MASK 0x1
+#define PHYCTRL_PDB_SHIFT 0x0
+#define PHYCTRL_PDB_PWR_ON 0x1
+#define PHYCTRL_PDB_PWR_OFF 0x0
+#define PHYCTRL_ENDLL_MASK 0x1
+#define PHYCTRL_ENDLL_SHIFT 0x1
+#define PHYCTRL_ENDLL_ENABLE 0x1
+#define PHYCTRL_ENDLL_DISABLE 0x0
+#define PHYCTRL_CALDONE_MASK 0x1
+#define PHYCTRL_CALDONE_SHIFT 0x6
+#define PHYCTRL_CALDONE_DONE 0x1
+#define PHYCTRL_CALDONE_GOING 0x0
+#define PHYCTRL_DLLRDY_MASK 0x1
+#define PHYCTRL_DLLRDY_SHIFT 0x5
+#define PHYCTRL_DLLRDY_DONE 0x1
+#define PHYCTRL_DLLRDY_GOING 0x0
+#define PHYCTRL_FREQSEL_200M 0x0
+#define PHYCTRL_FREQSEL_50M 0x1
+#define PHYCTRL_FREQSEL_100M 0x2
+#define PHYCTRL_FREQSEL_150M 0x3
+#define PHYCTRL_FREQSEL_MASK 0x3
+#define PHYCTRL_FREQSEL_SHIFT 0xc
+#define PHYCTRL_DR_MASK 0x7
+#define PHYCTRL_DR_SHIFT 0x4
+#define PHYCTRL_DR_50OHM 0x0
+#define PHYCTRL_DR_33OHM 0x1
+#define PHYCTRL_DR_66OHM 0x2
+#define PHYCTRL_DR_100OHM 0x3
+#define PHYCTRL_DR_40OHM 0x4
#define PHYCTRL_OTAPDLYENA 0x1
#define PHYCTRL_OTAPDLYENA_MASK 0x1
#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
--
2.8.0.rc3.226.g39d4020
WARNING: multiple messages have this Message-ID (diff)
From: dianders@chromium.org (Douglas Anderson)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions
Date: Mon, 20 Jun 2016 10:56:43 -0700 [thread overview]
Message-ID: <1466445414-11974-5-git-send-email-dianders@chromium.org> (raw)
In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org>
From: Brian Norris <briannorris@chromium.org>
Some of the spacing was wrong (spaces instead of tabs), and due to
longer entries added later, the columns weren't aligned. Let's get
everything consistent.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v3:
- Add Brian's PHY patches into my series
Changes in v2: None
drivers/phy/phy-rockchip-emmc.c | 76 ++++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
index a0b87cc6c818..a69f53630e67 100644
--- a/drivers/phy/phy-rockchip-emmc.c
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -31,44 +31,44 @@
((val) << (shift) | (mask) << ((shift) + 16))
/* Register definition */
-#define GRF_EMMCPHY_CON0 0x0
-#define GRF_EMMCPHY_CON1 0x4
-#define GRF_EMMCPHY_CON2 0x8
-#define GRF_EMMCPHY_CON3 0xc
-#define GRF_EMMCPHY_CON4 0x10
-#define GRF_EMMCPHY_CON5 0x14
-#define GRF_EMMCPHY_CON6 0x18
-#define GRF_EMMCPHY_STATUS 0x20
-
-#define PHYCTRL_PDB_MASK 0x1
-#define PHYCTRL_PDB_SHIFT 0x0
-#define PHYCTRL_PDB_PWR_ON 0x1
-#define PHYCTRL_PDB_PWR_OFF 0x0
-#define PHYCTRL_ENDLL_MASK 0x1
-#define PHYCTRL_ENDLL_SHIFT 0x1
-#define PHYCTRL_ENDLL_ENABLE 0x1
-#define PHYCTRL_ENDLL_DISABLE 0x0
-#define PHYCTRL_CALDONE_MASK 0x1
-#define PHYCTRL_CALDONE_SHIFT 0x6
-#define PHYCTRL_CALDONE_DONE 0x1
-#define PHYCTRL_CALDONE_GOING 0x0
-#define PHYCTRL_DLLRDY_MASK 0x1
-#define PHYCTRL_DLLRDY_SHIFT 0x5
-#define PHYCTRL_DLLRDY_DONE 0x1
-#define PHYCTRL_DLLRDY_GOING 0x0
-#define PHYCTRL_FREQSEL_200M 0x0
-#define PHYCTRL_FREQSEL_50M 0x1
-#define PHYCTRL_FREQSEL_100M 0x2
-#define PHYCTRL_FREQSEL_150M 0x3
-#define PHYCTRL_FREQSEL_MASK 0x3
-#define PHYCTRL_FREQSEL_SHIFT 0xc
-#define PHYCTRL_DR_MASK 0x7
-#define PHYCTRL_DR_SHIFT 0x4
-#define PHYCTRL_DR_50OHM 0x0
-#define PHYCTRL_DR_33OHM 0x1
-#define PHYCTRL_DR_66OHM 0x2
-#define PHYCTRL_DR_100OHM 0x3
-#define PHYCTRL_DR_40OHM 0x4
+#define GRF_EMMCPHY_CON0 0x0
+#define GRF_EMMCPHY_CON1 0x4
+#define GRF_EMMCPHY_CON2 0x8
+#define GRF_EMMCPHY_CON3 0xc
+#define GRF_EMMCPHY_CON4 0x10
+#define GRF_EMMCPHY_CON5 0x14
+#define GRF_EMMCPHY_CON6 0x18
+#define GRF_EMMCPHY_STATUS 0x20
+
+#define PHYCTRL_PDB_MASK 0x1
+#define PHYCTRL_PDB_SHIFT 0x0
+#define PHYCTRL_PDB_PWR_ON 0x1
+#define PHYCTRL_PDB_PWR_OFF 0x0
+#define PHYCTRL_ENDLL_MASK 0x1
+#define PHYCTRL_ENDLL_SHIFT 0x1
+#define PHYCTRL_ENDLL_ENABLE 0x1
+#define PHYCTRL_ENDLL_DISABLE 0x0
+#define PHYCTRL_CALDONE_MASK 0x1
+#define PHYCTRL_CALDONE_SHIFT 0x6
+#define PHYCTRL_CALDONE_DONE 0x1
+#define PHYCTRL_CALDONE_GOING 0x0
+#define PHYCTRL_DLLRDY_MASK 0x1
+#define PHYCTRL_DLLRDY_SHIFT 0x5
+#define PHYCTRL_DLLRDY_DONE 0x1
+#define PHYCTRL_DLLRDY_GOING 0x0
+#define PHYCTRL_FREQSEL_200M 0x0
+#define PHYCTRL_FREQSEL_50M 0x1
+#define PHYCTRL_FREQSEL_100M 0x2
+#define PHYCTRL_FREQSEL_150M 0x3
+#define PHYCTRL_FREQSEL_MASK 0x3
+#define PHYCTRL_FREQSEL_SHIFT 0xc
+#define PHYCTRL_DR_MASK 0x7
+#define PHYCTRL_DR_SHIFT 0x4
+#define PHYCTRL_DR_50OHM 0x0
+#define PHYCTRL_DR_33OHM 0x1
+#define PHYCTRL_DR_66OHM 0x2
+#define PHYCTRL_DR_100OHM 0x3
+#define PHYCTRL_DR_40OHM 0x4
#define PHYCTRL_OTAPDLYENA 0x1
#define PHYCTRL_OTAPDLYENA_MASK 0x1
#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
--
2.8.0.rc3.226.g39d4020
next prev parent reply other threads:[~2016-06-20 18:32 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-20 17:56 [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 01/15] phy: rockchip-emmc: give DLL some extra time to be ready Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 19:23 ` Guenter Roeck
2016-06-20 19:23 ` Guenter Roeck
2016-06-20 19:23 ` Guenter Roeck
2016-06-20 19:30 ` Doug Anderson
2016-06-20 19:30 ` Doug Anderson
2016-06-20 19:30 ` Doug Anderson
2016-06-20 19:36 ` Guenter Roeck
2016-06-20 19:36 ` Guenter Roeck
2016-06-20 19:36 ` Guenter Roeck
2016-06-20 19:38 ` Doug Anderson
2016-06-20 19:38 ` Doug Anderson
2016-06-20 19:38 ` Doug Anderson
2016-06-20 17:56 ` [PATCH v3 02/15] phy: rockchip-emmc: configure frequency range and drive impedance Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 03/15] phy: rockchip-emmc: configure default output tap delay Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson [this message]
2016-06-20 17:56 ` [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 05/15] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 19:29 ` Guenter Roeck
2016-06-20 19:29 ` Guenter Roeck
2016-06-20 19:29 ` Guenter Roeck
2016-06-20 19:36 ` Doug Anderson
2016-06-20 19:36 ` Doug Anderson
2016-06-20 19:36 ` Doug Anderson
2016-06-20 19:38 ` Guenter Roeck
2016-06-20 19:38 ` Guenter Roeck
2016-06-20 19:38 ` Guenter Roeck
2016-06-20 17:56 ` [PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-22 12:34 ` Adrian Hunter
2016-06-22 12:34 ` Adrian Hunter
2016-06-22 12:34 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 07/15] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 08/15] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-22 12:34 ` Adrian Hunter
2016-06-22 12:34 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 09/15] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-22 16:30 ` Heiko Stübner
2016-06-22 16:30 ` Heiko Stübner
2016-06-20 17:56 ` [PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 11/15] " Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-22 12:35 ` Adrian Hunter
2016-06-22 12:35 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 12/15] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 13/15] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off() Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 18:14 ` Heiko Stübner
2016-06-20 18:14 ` Heiko Stübner
2016-06-20 17:56 ` [PATCH v3 15/15] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-20 17:56 ` Douglas Anderson
2016-06-22 16:31 ` Heiko Stübner
2016-06-22 16:31 ` Heiko Stübner
2016-06-22 16:31 ` Heiko Stübner
2016-06-20 18:17 ` [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Heiko Stübner
2016-06-20 18:17 ` Heiko Stübner
2016-06-22 15:23 ` Ulf Hansson
2016-06-22 15:23 ` Ulf Hansson
2016-06-22 15:23 ` Ulf Hansson
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