From: Rajan Vaja <rajan.vaja@xilinx.com> To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, m.tretter@pengutronix.de, gustavo@embeddedor.com, dan.carpenter@oracle.com, tejas.patel@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>, Rajan Vaja <rajan.vaja@xilinx.com> Subject: [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Date: Fri, 22 Nov 2019 01:43:34 -0800 [thread overview] Message-ID: <1574415814-19797-7-git-send-email-rajan.vaja@xilinx.com> (raw) In-Reply-To: <1574415814-19797-1-git-send-email-rajan.vaja@xilinx.com> From: Tejas Patel <tejas.patel@xilinx.com> Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> --- drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e0d49cc..1d5a416 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC Divider support * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Adjustable divider clock implementation */ @@ -45,9 +45,26 @@ struct zynqmp_clk_divider { }; static inline int zynqmp_divider_get_val(unsigned long parent_rate, - unsigned long rate) + unsigned long rate, u16 flags) { - return DIV_ROUND_CLOSEST(parent_rate, rate); + int up, down; + unsigned long up_rate, down_rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { + up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); + + up = __roundup_pow_of_two(up); + down = __rounddown_pow_of_two(down); + + up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); + down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); + + return (rate - up_rate) <= (down_rate - rate) ? up : down; + + } else { + return DIV_ROUND_CLOSEST(parent_rate, rate); + } } /** @@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, else value = div >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + value = 1 << value; + if (!value) { WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", @@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, else bestdiv = bestdiv >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + bestdiv = 1 << bestdiv; + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate); + bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); /* * In case of two divisors, compute best divider values and return @@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, int ret; const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - value = zynqmp_divider_get_val(parent_rate, rate); + value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { div = value & 0xFFFF; div |= 0xffff << 16; @@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, div |= value << 16; } + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + div = __ffs(div); + ret = eemi_ops->clock_setdivider(clk_id, div); if (ret) -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Rajan Vaja <rajan.vaja@xilinx.com> To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, m.tretter@pengutronix.de, gustavo@embeddedor.com, dan.carpenter@oracle.com, tejas.patel@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org Cc: devicetree@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Date: Fri, 22 Nov 2019 01:43:34 -0800 [thread overview] Message-ID: <1574415814-19797-7-git-send-email-rajan.vaja@xilinx.com> (raw) In-Reply-To: <1574415814-19797-1-git-send-email-rajan.vaja@xilinx.com> From: Tejas Patel <tejas.patel@xilinx.com> Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> --- drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e0d49cc..1d5a416 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC Divider support * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Adjustable divider clock implementation */ @@ -45,9 +45,26 @@ struct zynqmp_clk_divider { }; static inline int zynqmp_divider_get_val(unsigned long parent_rate, - unsigned long rate) + unsigned long rate, u16 flags) { - return DIV_ROUND_CLOSEST(parent_rate, rate); + int up, down; + unsigned long up_rate, down_rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { + up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); + + up = __roundup_pow_of_two(up); + down = __rounddown_pow_of_two(down); + + up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); + down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); + + return (rate - up_rate) <= (down_rate - rate) ? up : down; + + } else { + return DIV_ROUND_CLOSEST(parent_rate, rate); + } } /** @@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, else value = div >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + value = 1 << value; + if (!value) { WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", @@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, else bestdiv = bestdiv >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + bestdiv = 1 << bestdiv; + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate); + bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); /* * In case of two divisors, compute best divider values and return @@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, int ret; const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - value = zynqmp_divider_get_val(parent_rate, rate); + value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { div = value & 0xFFFF; div |= 0xffff << 16; @@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, div |= value << 16; } + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + div = __ffs(div); + ret = eemi_ops->clock_setdivider(clk_id, div); if (ret) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-22 9:46 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-12 13:16 [PATCH 0/7] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 1/7] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 22:51 ` Stephen Boyd 2019-11-12 22:51 ` Stephen Boyd 2019-11-18 17:30 ` Rob Herring 2019-11-18 17:30 ` Rob Herring 2019-11-12 13:16 ` [PATCH 2/7] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 3/7] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:31 ` Michael Tretter 2019-11-21 14:31 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 4/7] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:33 ` Michael Tretter 2019-11-21 14:33 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 5/7] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 6/7] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 7/7] clk: zynqmp: Fix fractional clock check Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:41 ` Michael Tretter 2019-11-21 14:41 ` Michael Tretter 2019-11-22 9:43 ` [PATCH v2 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-12-04 19:53 ` Rob Herring 2019-12-04 19:53 ` Rob Herring 2019-11-22 9:43 ` [PATCH v2 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja [this message] 2019-11-22 9:43 ` [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:59 ` Stephen Boyd 2020-01-23 22:59 ` Stephen Boyd 2019-12-12 15:20 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Michal Simek 2019-12-12 15:20 ` Michal Simek 2020-01-16 11:41 ` Rajan Vaja 2020-01-16 11:41 ` Rajan Vaja
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