From: Rajan Vaja <rajan.vaja@xilinx.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, michal.simek@xilinx.com,
jolly.shah@xilinx.com, m.tretter@pengutronix.de,
gustavo@embeddedor.com, tejas.patel@xilinx.com,
nava.manne@xilinx.com, mdf@kernel.org
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Rajan Vaja <rajan.vaja@xilinx.com>
Subject: [PATCH v3 2/6] clk: zynqmp: Extend driver for versal
Date: Wed, 4 Dec 2019 22:35:55 -0800 [thread overview]
Message-ID: <1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com> (raw)
In-Reply-To: <1575527759-26452-1-git-send-email-rajan.vaja@xilinx.com>
Add Versal compatible string to support Versal
binding.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
---
drivers/clk/zynqmp/clkc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index a11f93e..10e89f2 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC clock controller
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
+ {.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Rajan Vaja <rajan.vaja@xilinx.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, michal.simek@xilinx.com,
jolly.shah@xilinx.com, m.tretter@pengutronix.de,
gustavo@embeddedor.com, tejas.patel@xilinx.com,
nava.manne@xilinx.com, mdf@kernel.org
Cc: devicetree@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 2/6] clk: zynqmp: Extend driver for versal
Date: Wed, 4 Dec 2019 22:35:55 -0800 [thread overview]
Message-ID: <1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com> (raw)
In-Reply-To: <1575527759-26452-1-git-send-email-rajan.vaja@xilinx.com>
Add Versal compatible string to support Versal
binding.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
---
drivers/clk/zynqmp/clkc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index a11f93e..10e89f2 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC clock controller
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
+ {.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
--
2.7.4
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next prev parent reply other threads:[~2019-12-05 6:37 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-12 13:16 [PATCH 0/7] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-12 13:16 ` [PATCH 1/7] dt-bindings: clock: Add bindings for versal " Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-12 22:51 ` Stephen Boyd
2019-11-12 22:51 ` Stephen Boyd
2019-11-18 17:30 ` Rob Herring
2019-11-18 17:30 ` Rob Herring
2019-11-12 13:16 ` [PATCH 2/7] clk: zynqmp: Extend driver for versal Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-12 13:16 ` [PATCH 3/7] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-21 14:31 ` Michael Tretter
2019-11-21 14:31 ` Michael Tretter
2019-11-12 13:16 ` [PATCH 4/7] clk: zynqmp: Add support for get max divider Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-21 14:33 ` Michael Tretter
2019-11-21 14:33 ` Michael Tretter
2019-11-12 13:16 ` [PATCH 5/7] clk: zynqmp: Fix divider calculation Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-12 13:16 ` [PATCH 6/7] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-12 13:16 ` [PATCH 7/7] clk: zynqmp: Fix fractional clock check Rajan Vaja
2019-11-12 13:16 ` Rajan Vaja
2019-11-21 14:41 ` Michael Tretter
2019-11-21 14:41 ` Michael Tretter
2019-11-22 9:43 ` [PATCH v2 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-11-22 9:43 ` [PATCH v2 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-12-04 19:53 ` Rob Herring
2019-12-04 19:53 ` Rob Herring
2019-11-22 9:43 ` [PATCH v2 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-11-22 9:43 ` [PATCH v2 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-11-22 9:43 ` [PATCH v2 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-11-22 9:43 ` [PATCH v2 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-11-22 9:43 ` [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja
2019-11-22 9:43 ` Rajan Vaja
2019-12-05 6:35 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2019-12-05 6:35 ` [PATCH v3 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2020-01-23 22:58 ` Stephen Boyd
2020-01-23 22:58 ` Stephen Boyd
2019-12-05 6:35 ` Rajan Vaja [this message]
2019-12-05 6:35 ` [PATCH v3 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja
2020-01-23 22:58 ` Stephen Boyd
2020-01-23 22:58 ` Stephen Boyd
2019-12-05 6:35 ` [PATCH v3 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2020-01-23 22:58 ` Stephen Boyd
2020-01-23 22:58 ` Stephen Boyd
2019-12-05 6:35 ` [PATCH v3 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2020-01-23 22:58 ` Stephen Boyd
2020-01-23 22:58 ` Stephen Boyd
2019-12-05 6:35 ` [PATCH v3 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2020-01-23 22:58 ` Stephen Boyd
2020-01-23 22:58 ` Stephen Boyd
2019-12-05 6:35 ` [PATCH v3 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja
2019-12-05 6:35 ` Rajan Vaja
2020-01-23 22:59 ` Stephen Boyd
2020-01-23 22:59 ` Stephen Boyd
2019-12-12 15:20 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Michal Simek
2019-12-12 15:20 ` Michal Simek
2020-01-16 11:41 ` Rajan Vaja
2020-01-16 11:41 ` Rajan Vaja
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