From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com Subject: [PATCH v2 45/59] drm/kmb: Enable LCD interrupts Date: Tue, 14 Jul 2020 13:57:31 -0700 [thread overview] Message-ID: <1594760265-11618-46-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> Enabled vblank interrupts for LCD. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 36 +++++++++++++++--------------------- drivers/gpu/drm/kmb/kmb_drv.c | 41 +++++++++++++++++++++-------------------- drivers/gpu/drm/kmb/kmb_plane.c | 6 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 2 +- 4 files changed, 40 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 1987185e..589a841 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -41,7 +41,8 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ - kmb_write_lcd(dev_p, LCD_INT_ENABLE, LCD_INT_VERT_COMP); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); return 0; } @@ -53,13 +54,8 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) /*clear interrupt */ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ - kmb_write_lcd(dev_p, LCD_INT_ENABLE, 0); - -/* TBD - * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register - * set the required bit LCD_VSTATUS_COMPARE register - * Not sure if anything needs to be done in the ICB - */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); } static const struct drm_crtc_funcs kmb_crtc_funcs = { @@ -82,7 +78,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) int vsync_start_offset; int vsync_end_offset; struct kmb_drm_private *dev_p = to_kmb(dev); -#endif + /* initialize mipi */ kmb_dsi_hw_init(dev, m); DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", @@ -92,7 +88,6 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) m->crtc_hsync_start - m->crtc_hdisplay, m->crtc_htotal - m->crtc_hsync_end, m->crtc_hsync_end - m->crtc_hsync_start); -#ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; @@ -156,7 +151,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, clk_prepare_enable(lcd->clk); kmb_crtc_mode_set_nofb(crtc); -// drm_crtc_vblank_on(crtc); + drm_crtc_vblank_on(crtc); } static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -167,33 +162,32 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, /* always disable planes on the CRTC that is being turned off */ drm_atomic_helper_disable_planes_on_crtc(old_state, false); -// drm_crtc_vblank_off(crtc); + drm_crtc_vblank_off(crtc); clk_disable_unprepare(lcd->clk); } static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*disable vblank interrupts here - * clear BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); } static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*enable vblank interrupts after - * set BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) drm_crtc_send_vblank_event(crtc, crtc->state->event); crtc->state->event = NULL; spin_unlock_irq(&crtc->dev->event_lock); - } static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index bbf3e649..e6aa32c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -127,10 +127,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = to_kmb(drm); struct platform_device *pdev = to_platform_device(drm->dev); -#ifdef WIP /*u32 version;*/ - int irq_lcd, irq_mipi; -#endif + int irq_lcd;// irq_mipi; int ret = 0; unsigned long clk; @@ -266,10 +264,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); #endif //KMB_CLOCKS -#ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - - * firmware has to redirect it to A53 + * firmware has redirected 79 to A53 IRQ 33 */ DRM_INFO("platform_get_irq_byname %pOF\n", drm->dev->of_node); @@ -279,14 +276,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); if (irq_lcd < 0) { DRM_ERROR("irq_lcd not found"); - return irq_lcd; + goto setup_fail; } pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); - ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); - dev_p->irq_lcd = irq_lcd; - +#ifdef WIP /* Allocate MIPI interrupt resources, enable interrupt line, * and setup IRQ handling */ @@ -322,19 +317,16 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } -#ifdef WIP - ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); + ret = drm_irq_install(drm, irq_lcd); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); goto irq_fail; } -#endif + dev_p->irq_lcd = irq_lcd; return 0; -#ifdef WIP irq_fail: drm_crtc_cleanup(&dev_p->crtc); -#endif setup_fail: of_reserved_mem_device_release(drm->dev); @@ -381,6 +373,11 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP); } + if (status & LCD_INT_LAYER) { + /* clear layer interrupts */ + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); + } + if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ val = kmb_read_lcd(dev_p, LCD_VSTATUS); @@ -400,23 +397,20 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) return IRQ_HANDLED; } +#ifdef MIPI_IRQ static irqreturn_t handle_mipi_irq(struct drm_device *dev) { mipi_tx_handle_irqs(to_kmb(dev)); return IRQ_HANDLED; } +#endif static irqreturn_t kmb_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; - struct kmb_drm_private *dev_p = to_kmb(dev); irqreturn_t ret = IRQ_NONE; - if (irq == dev_p->irq_lcd) - ret = handle_lcd_irq(dev); - else if (irq == dev_p->irq_mipi) - ret = handle_mipi_irq(dev); - + ret = handle_lcd_irq(dev); return ret; } @@ -552,6 +546,12 @@ static int kmb_probe(struct platform_device *pdev) /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); + ret = drm_vblank_init(drm, drm->mode_config.num_crtc); + DRM_INFO("mode_config.num_crtc=%d\n", drm->mode_config.num_crtc); + if (ret < 0) { + DRM_ERROR("failed to initialize vblank\n"); + goto err_vblank; + } drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); @@ -568,6 +568,7 @@ static int kmb_probe(struct platform_device *pdev) err_register: drm_kms_helper_poll_fini(drm); +err_vblank: pm_runtime_disable(drm->dev); err_free: drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index f6dfe24..3245ec7 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -155,9 +155,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, break; } - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - ~LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_CONTROL, ~ctrl); + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index e95891a..f5c1c4d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -87,7 +87,7 @@ #define LAYER3_DMA_IDLE (1<<24) #define LAYER3_DMA_FIFO_OVERFLOW (1<<25) #define LAYER3_DMA_FIFO_UNDERFLOW (1<<26) - +#define LCD_INT_LAYER (0x07fffff8) #define LCD_INT_ENABLE (0x4 * 0x002) #define LCD_INT_CLEAR (0x4 * 0x003) #define LCD_LINE_COUNT (0x4 * 0x004) -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 45/59] drm/kmb: Enable LCD interrupts Date: Tue, 14 Jul 2020 13:57:31 -0700 [thread overview] Message-ID: <1594760265-11618-46-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> Enabled vblank interrupts for LCD. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 36 +++++++++++++++--------------------- drivers/gpu/drm/kmb/kmb_drv.c | 41 +++++++++++++++++++++-------------------- drivers/gpu/drm/kmb/kmb_plane.c | 6 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 2 +- 4 files changed, 40 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 1987185e..589a841 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -41,7 +41,8 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ - kmb_write_lcd(dev_p, LCD_INT_ENABLE, LCD_INT_VERT_COMP); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); return 0; } @@ -53,13 +54,8 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) /*clear interrupt */ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ - kmb_write_lcd(dev_p, LCD_INT_ENABLE, 0); - -/* TBD - * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register - * set the required bit LCD_VSTATUS_COMPARE register - * Not sure if anything needs to be done in the ICB - */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); } static const struct drm_crtc_funcs kmb_crtc_funcs = { @@ -82,7 +78,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) int vsync_start_offset; int vsync_end_offset; struct kmb_drm_private *dev_p = to_kmb(dev); -#endif + /* initialize mipi */ kmb_dsi_hw_init(dev, m); DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", @@ -92,7 +88,6 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) m->crtc_hsync_start - m->crtc_hdisplay, m->crtc_htotal - m->crtc_hsync_end, m->crtc_hsync_end - m->crtc_hsync_start); -#ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; @@ -156,7 +151,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, clk_prepare_enable(lcd->clk); kmb_crtc_mode_set_nofb(crtc); -// drm_crtc_vblank_on(crtc); + drm_crtc_vblank_on(crtc); } static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -167,33 +162,32 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, /* always disable planes on the CRTC that is being turned off */ drm_atomic_helper_disable_planes_on_crtc(old_state, false); -// drm_crtc_vblank_off(crtc); + drm_crtc_vblank_off(crtc); clk_disable_unprepare(lcd->clk); } static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*disable vblank interrupts here - * clear BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); } static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*enable vblank interrupts after - * set BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) drm_crtc_send_vblank_event(crtc, crtc->state->event); crtc->state->event = NULL; spin_unlock_irq(&crtc->dev->event_lock); - } static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index bbf3e649..e6aa32c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -127,10 +127,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = to_kmb(drm); struct platform_device *pdev = to_platform_device(drm->dev); -#ifdef WIP /*u32 version;*/ - int irq_lcd, irq_mipi; -#endif + int irq_lcd;// irq_mipi; int ret = 0; unsigned long clk; @@ -266,10 +264,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); #endif //KMB_CLOCKS -#ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - - * firmware has to redirect it to A53 + * firmware has redirected 79 to A53 IRQ 33 */ DRM_INFO("platform_get_irq_byname %pOF\n", drm->dev->of_node); @@ -279,14 +276,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); if (irq_lcd < 0) { DRM_ERROR("irq_lcd not found"); - return irq_lcd; + goto setup_fail; } pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); - ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); - dev_p->irq_lcd = irq_lcd; - +#ifdef WIP /* Allocate MIPI interrupt resources, enable interrupt line, * and setup IRQ handling */ @@ -322,19 +317,16 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } -#ifdef WIP - ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); + ret = drm_irq_install(drm, irq_lcd); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); goto irq_fail; } -#endif + dev_p->irq_lcd = irq_lcd; return 0; -#ifdef WIP irq_fail: drm_crtc_cleanup(&dev_p->crtc); -#endif setup_fail: of_reserved_mem_device_release(drm->dev); @@ -381,6 +373,11 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP); } + if (status & LCD_INT_LAYER) { + /* clear layer interrupts */ + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); + } + if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ val = kmb_read_lcd(dev_p, LCD_VSTATUS); @@ -400,23 +397,20 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) return IRQ_HANDLED; } +#ifdef MIPI_IRQ static irqreturn_t handle_mipi_irq(struct drm_device *dev) { mipi_tx_handle_irqs(to_kmb(dev)); return IRQ_HANDLED; } +#endif static irqreturn_t kmb_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; - struct kmb_drm_private *dev_p = to_kmb(dev); irqreturn_t ret = IRQ_NONE; - if (irq == dev_p->irq_lcd) - ret = handle_lcd_irq(dev); - else if (irq == dev_p->irq_mipi) - ret = handle_mipi_irq(dev); - + ret = handle_lcd_irq(dev); return ret; } @@ -552,6 +546,12 @@ static int kmb_probe(struct platform_device *pdev) /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); + ret = drm_vblank_init(drm, drm->mode_config.num_crtc); + DRM_INFO("mode_config.num_crtc=%d\n", drm->mode_config.num_crtc); + if (ret < 0) { + DRM_ERROR("failed to initialize vblank\n"); + goto err_vblank; + } drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); @@ -568,6 +568,7 @@ static int kmb_probe(struct platform_device *pdev) err_register: drm_kms_helper_poll_fini(drm); +err_vblank: pm_runtime_disable(drm->dev); err_free: drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index f6dfe24..3245ec7 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -155,9 +155,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, break; } - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - ~LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_CONTROL, ~ctrl); + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index e95891a..f5c1c4d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -87,7 +87,7 @@ #define LAYER3_DMA_IDLE (1<<24) #define LAYER3_DMA_FIFO_OVERFLOW (1<<25) #define LAYER3_DMA_FIFO_UNDERFLOW (1<<26) - +#define LCD_INT_LAYER (0x07fffff8) #define LCD_INT_ENABLE (0x4 * 0x002) #define LCD_INT_CLEAR (0x4 * 0x003) #define LCD_LINE_COUNT (0x4 * 0x004) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-07-14 20:59 UTC|newest] Thread overview: 133+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-14 20:56 [PATCH v2 00/59] Add support for KeemBay DRM driver Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 10/59] drm/kmb: Part 2 " Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 17/59] drm/kmb: Part7 " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 18/59] drm/kmb: Part8 " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 29/59] drm/kmb: Defer Probe Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` Anitha Chrisanthus [this message] 2020-07-14 20:57 ` [Intel-gfx] [PATCH v2 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 21:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for KeemBay DRM driver Patchwork 2020-07-14 22:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-07-15 1:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-07-15 15:05 ` [Intel-gfx] [PATCH v2 00/59] " Daniel Vetter 2020-07-15 15:05 ` Daniel Vetter 2020-07-15 15:14 ` Daniel Vetter 2020-07-15 15:14 ` Daniel Vetter 2020-07-15 17:06 ` Sam Ravnborg 2020-07-15 17:06 ` Sam Ravnborg 2020-07-15 18:38 ` Chrisanthus, Anitha 2020-07-15 18:38 ` Chrisanthus, Anitha 2020-07-15 17:01 ` Sam Ravnborg 2020-07-15 17:01 ` [Intel-gfx] " Sam Ravnborg
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