From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com Subject: [PATCH v2 05/59] drm/kmb: Updated kmb_plane_atomic_check Date: Tue, 14 Jul 2020 13:56:51 -0700 [thread overview] Message-ID: <1594760265-11618-6-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> Check if format is supported and size is within limits. v2: simplified the code as per code review Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 111 +++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 877314a..74a3573 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -21,15 +21,66 @@ #include "kmb_plane.h" #include "kmb_regs.h" +/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, +}; + +#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) +#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) + +/* video layer ( 0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + /*planar formats */ + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) +{ + int i; + + for (i = 0; i < plane->format_count; i++) { + if (plane->format_types[i] == format) + return 0; + } + return -EINVAL; +} + static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { -/* TBD below structure will be used for implementation later - * struct drm_crtc_state *crtc_state; - */ - /* TBD */ - /* Plane based checking */ + struct drm_framebuffer *fb; + int ret; + + fb = state->fb; + ret = check_pixel_format(plane, fb->format->format); + if (ret) + return ret; + + if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) + return -EINVAL; return 0; } @@ -38,36 +89,36 @@ unsigned int set_pixel_format(u32 format) unsigned int val = 0; switch (format) { - /*planar formats */ + /*planar formats */ case DRM_FORMAT_YUV444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_NV12: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_NV21: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ + /* packed formats */ case DRM_FORMAT_RGB332: val = LCD_LAYER_FORMAT_RGB332; break; @@ -127,7 +178,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) unsigned int val = 0; for (i = 0; i < format->num_planes; i++) - bpp += 8*format->cpp[i]; + bpp += 8 * format->cpp[i]; switch (bpp) { case 8: @@ -171,8 +222,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y); @@ -295,38 +346,6 @@ static const struct drm_plane_funcs kmb_plane_funcs = { .atomic_destroy_state = kmb_destroy_plane_state, }; -/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ -static const u32 kmb_formats_g[] = { - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, -}; - -/* video layer (0 & 1) formats, packed and planar formats are supported */ -static const u32 kmb_formats_v[] = { - /* packed formats */ - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - /*planar formats */ - DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, - DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, - DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, - DRM_FORMAT_NV12, DRM_FORMAT_NV21, -}; - struct kmb_plane *kmb_plane_init(struct drm_device *drm) { struct kmb_drm_private *lcd = to_kmb(drm); -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 05/59] drm/kmb: Updated kmb_plane_atomic_check Date: Tue, 14 Jul 2020 13:56:51 -0700 [thread overview] Message-ID: <1594760265-11618-6-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> Check if format is supported and size is within limits. v2: simplified the code as per code review Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 111 +++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 877314a..74a3573 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -21,15 +21,66 @@ #include "kmb_plane.h" #include "kmb_regs.h" +/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, +}; + +#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) +#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) + +/* video layer ( 0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + /*planar formats */ + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) +{ + int i; + + for (i = 0; i < plane->format_count; i++) { + if (plane->format_types[i] == format) + return 0; + } + return -EINVAL; +} + static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { -/* TBD below structure will be used for implementation later - * struct drm_crtc_state *crtc_state; - */ - /* TBD */ - /* Plane based checking */ + struct drm_framebuffer *fb; + int ret; + + fb = state->fb; + ret = check_pixel_format(plane, fb->format->format); + if (ret) + return ret; + + if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) + return -EINVAL; return 0; } @@ -38,36 +89,36 @@ unsigned int set_pixel_format(u32 format) unsigned int val = 0; switch (format) { - /*planar formats */ + /*planar formats */ case DRM_FORMAT_YUV444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_NV12: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_NV21: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ + /* packed formats */ case DRM_FORMAT_RGB332: val = LCD_LAYER_FORMAT_RGB332; break; @@ -127,7 +178,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) unsigned int val = 0; for (i = 0; i < format->num_planes; i++) - bpp += 8*format->cpp[i]; + bpp += 8 * format->cpp[i]; switch (bpp) { case 8: @@ -171,8 +222,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y); @@ -295,38 +346,6 @@ static const struct drm_plane_funcs kmb_plane_funcs = { .atomic_destroy_state = kmb_destroy_plane_state, }; -/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ -static const u32 kmb_formats_g[] = { - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, -}; - -/* video layer (0 & 1) formats, packed and planar formats are supported */ -static const u32 kmb_formats_v[] = { - /* packed formats */ - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - /*planar formats */ - DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, - DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, - DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, - DRM_FORMAT_NV12, DRM_FORMAT_NV21, -}; - struct kmb_plane *kmb_plane_init(struct drm_device *drm) { struct kmb_drm_private *lcd = to_kmb(drm); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-07-14 20:59 UTC|newest] Thread overview: 133+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-14 20:56 [PATCH v2 00/59] Add support for KeemBay DRM driver Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` Anitha Chrisanthus [this message] 2020-07-14 20:56 ` [Intel-gfx] [PATCH v2 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 10/59] drm/kmb: Part 2 " Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:56 ` [PATCH v2 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:56 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 17/59] drm/kmb: Part7 " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 18/59] drm/kmb: Part8 " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 29/59] drm/kmb: Defer Probe Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 20:57 ` [PATCH v2 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus 2020-07-14 20:57 ` [Intel-gfx] " Anitha Chrisanthus 2020-07-14 21:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for KeemBay DRM driver Patchwork 2020-07-14 22:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-07-15 1:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-07-15 15:05 ` [Intel-gfx] [PATCH v2 00/59] " Daniel Vetter 2020-07-15 15:05 ` Daniel Vetter 2020-07-15 15:14 ` Daniel Vetter 2020-07-15 15:14 ` Daniel Vetter 2020-07-15 17:06 ` Sam Ravnborg 2020-07-15 17:06 ` Sam Ravnborg 2020-07-15 18:38 ` Chrisanthus, Anitha 2020-07-15 18:38 ` Chrisanthus, Anitha 2020-07-15 17:01 ` Sam Ravnborg 2020-07-15 17:01 ` [Intel-gfx] " Sam Ravnborg
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