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From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock
Date: Thu, 19 Nov 2020 17:43:17 +0200	[thread overview]
Message-ID: <1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com>

Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/sama7g5.c       | 13 ++++++-------
 include/dt-bindings/clock/at91.h |  1 +
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 927eb3b2b126..a6e20b35960e 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 	if (IS_ERR(regmap))
 		return;
 
-	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
+	sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
 					nck(sama7g5_systemck),
 					nck(sama7g5_periphck),
 					nck(sama7g5_gck), 8);
@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		}
 	}
 
-	parent_names[0] = md_slck_name;
-	parent_names[1] = "mainck";
-	parent_names[2] = "cpupll_divpmcck";
-	parent_names[3] = "syspll_divpmcck";
-	hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
+	parent_names[0] = "cpupll_divpmcck";
+	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
 					   &mck0_layout, &mck0_characteristics,
 					   &pmc_mck0_lock,
 					   CLK_SET_RATE_PARENT, 0);
 	if (IS_ERR(hw))
 		goto err_free;
 
-	hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
+	sama7g5_pmc->chws[PMC_CPU] = hw;
+
+	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
 					  &mck0_layout, &mck0_characteristics,
 					  &pmc_mck0_lock, 0);
 	if (IS_ERR(hw))
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index fab313f62e8f..98e1b2ab6403 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -34,6 +34,7 @@
 #define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
 #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
 #define PMC_ETHPLL		(PMC_MAIN + 8)
+#define PMC_CPU			(PMC_MAIN + 9)
 
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock
Date: Thu, 19 Nov 2020 17:43:17 +0200	[thread overview]
Message-ID: <1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com>

Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/sama7g5.c       | 13 ++++++-------
 include/dt-bindings/clock/at91.h |  1 +
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 927eb3b2b126..a6e20b35960e 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 	if (IS_ERR(regmap))
 		return;
 
-	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
+	sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
 					nck(sama7g5_systemck),
 					nck(sama7g5_periphck),
 					nck(sama7g5_gck), 8);
@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		}
 	}
 
-	parent_names[0] = md_slck_name;
-	parent_names[1] = "mainck";
-	parent_names[2] = "cpupll_divpmcck";
-	parent_names[3] = "syspll_divpmcck";
-	hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
+	parent_names[0] = "cpupll_divpmcck";
+	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
 					   &mck0_layout, &mck0_characteristics,
 					   &pmc_mck0_lock,
 					   CLK_SET_RATE_PARENT, 0);
 	if (IS_ERR(hw))
 		goto err_free;
 
-	hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
+	sama7g5_pmc->chws[PMC_CPU] = hw;
+
+	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
 					  &mck0_layout, &mck0_characteristics,
 					  &pmc_mck0_lock, 0);
 	if (IS_ERR(hw))
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index fab313f62e8f..98e1b2ab6403 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -34,6 +34,7 @@
 #define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
 #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
 #define PMC_ETHPLL		(PMC_MAIN + 8)
+#define PMC_CPU			(PMC_MAIN + 9)
 
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
-- 
2.7.4


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  parent reply	other threads:[~2020-11-19 15:44 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 15:43 [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-11-19 15:43 ` [PATCH v6 01/11] clk: at91: sama7g5: fix compilation error Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-12-19 23:31   ` Stephen Boyd
2020-12-19 23:31     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 19:53   ` Stephen Boyd
2020-12-19 19:53     ` Stephen Boyd
2020-12-19 23:31   ` Stephen Boyd
2020-12-19 23:31     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 23:32   ` Stephen Boyd
2020-12-19 23:32     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 23:32   ` Stephen Boyd
2020-12-19 23:32     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 23:32   ` Stephen Boyd
2020-12-19 23:32     ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-11-19 15:43   ` Claudiu Beznea
2020-12-19 23:32   ` Stephen Boyd
2020-12-19 23:32     ` Stephen Boyd
2020-11-19 15:43 ` Claudiu Beznea [this message]
2020-11-19 15:43   ` [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock Claudiu Beznea
2020-12-19 23:32   ` Stephen Boyd
2020-12-19 23:32     ` Stephen Boyd
2020-11-27 12:12 ` [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu.Beznea
2020-11-27 12:12   ` Claudiu.Beznea

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