From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: linux-kernel@vger.kernel.org, Anshuman Khandual <anshuman.khandual@arm.com>, Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Linu Cherian <lcherian@marvell.com> Subject: [PATCH 00/11] arm64: coresight: Enable ETE and TRBE Date: Wed, 23 Dec 2020 15:33:32 +0530 [thread overview] Message-ID: <1608717823-18387-1-git-send-email-anshuman.khandual@arm.com> (raw) This series enables future IP trace features Embedded Trace Extension (ETE) and Trace Buffer Extension (TRBE). This series depends on the ETM system register instruction support series [0] which is available here [1]. This series which applies on [1] is avaialble here [2] for quick access. ETE is the PE (CPU) trace unit for CPUs, implementing future architecture extensions. ETE overlaps with the ETMv4 architecture, with additions to support the newer architecture features and some restrictions on the supported features w.r.t ETMv4. The ETE support is added by extending the ETMv4 driver to recognise the ETE and handle the features as exposed by the TRCIDRx registers. ETE only supports system instructions access from the host CPU. The ETE could be integrated with a TRBE (see below), or with the legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware description as the ETMs and requires a node per instance. Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is accessible via the system registers and can be combined with the ETE to provide a 1x1 configuration of source & sink. TRBE is being represented here as a CoreSight sink. Primary reason is that the ETE source could work with other traditional CoreSight sink devices. As TRBE captures the trace data which is produced by ETE, it cannot work alone. TRBE representation here have some distinct deviations from a traditional CoreSight sink device. Coresight path between ETE and TRBE are not built during boot looking at respective DT or ACPI entries. Unlike traditional sinks, TRBE can generate interrupts to signal including many other things, buffer got filled. The interrupt is a PPI and should be communicated from the platform. DT or ACPI entry representing TRBE should have the PPI number for a given platform. During perf session, the TRBE IRQ handler should capture trace for perf auxiliary buffer before restarting it back. System registers being used here to configure ETE and TRBE could be referred in the link below. https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers. Things todo: - Improve TRBE IRQ handling for all possible corner cases - Implement sysfs based trace sessions [0] https://lore.kernel.org/linux-arm-kernel/20201214173731.302520-1-suzuki.poulose@arm.com/ [1] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/sysreg-v5 [2] https://gitlab.arm.com/linux-arm/linux-anshuman/-/tree/coresight/ete_trbe_v1 Changes in V1: - There are not much ETE changes from Suzuki apart from splitting of the ETE DTS patch - TRBE changes have been captured in the respective patches Changes in RFC: https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khandual@arm.com/ Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Linu Cherian <lcherian@marvell.com> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Anshuman Khandual (5): arm64: Add TRBE definitions coresight: core: Add support for dedicated percpu sinks coresight: etm-perf: Truncate the perf record if handle has no space coresight: sink: Add TRBE driver dts: bindings: Document device tree binding for Arm TRBE Suzuki K Poulose (6): coresight: etm-perf: Allow an event to use different sinks coresight: Do not scan for graph if none is present coresight: etm4x: Add support for PE OS lock coresight: ete: Add support for ETE sysreg access coresight: ete: Add support for ETE tracing dts: bindings: Document device tree bindings for ETE Documentation/devicetree/bindings/arm/ete.txt | 41 + Documentation/devicetree/bindings/arm/trbe.txt | 20 + Documentation/trace/coresight/coresight-trbe.rst | 39 + arch/arm64/include/asm/sysreg.h | 51 ++ drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 14 + drivers/hwtracing/coresight/coresight-etm-perf.c | 51 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 138 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 64 +- drivers/hwtracing/coresight/coresight-platform.c | 6 + drivers/hwtracing/coresight/coresight-trbe.c | 925 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.h | 248 ++++++ include/linux/coresight.h | 12 + 14 files changed, 1580 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/ete.txt create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt create mode 100644 Documentation/trace/coresight/coresight-trbe.rst create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Anshuman Khandual <anshuman.khandual@arm.com>, linux-kernel@vger.kernel.org, Linu Cherian <lcherian@marvell.com>, Mike Leach <mike.leach@linaro.org> Subject: [PATCH 00/11] arm64: coresight: Enable ETE and TRBE Date: Wed, 23 Dec 2020 15:33:32 +0530 [thread overview] Message-ID: <1608717823-18387-1-git-send-email-anshuman.khandual@arm.com> (raw) This series enables future IP trace features Embedded Trace Extension (ETE) and Trace Buffer Extension (TRBE). This series depends on the ETM system register instruction support series [0] which is available here [1]. This series which applies on [1] is avaialble here [2] for quick access. ETE is the PE (CPU) trace unit for CPUs, implementing future architecture extensions. ETE overlaps with the ETMv4 architecture, with additions to support the newer architecture features and some restrictions on the supported features w.r.t ETMv4. The ETE support is added by extending the ETMv4 driver to recognise the ETE and handle the features as exposed by the TRCIDRx registers. ETE only supports system instructions access from the host CPU. The ETE could be integrated with a TRBE (see below), or with the legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware description as the ETMs and requires a node per instance. Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is accessible via the system registers and can be combined with the ETE to provide a 1x1 configuration of source & sink. TRBE is being represented here as a CoreSight sink. Primary reason is that the ETE source could work with other traditional CoreSight sink devices. As TRBE captures the trace data which is produced by ETE, it cannot work alone. TRBE representation here have some distinct deviations from a traditional CoreSight sink device. Coresight path between ETE and TRBE are not built during boot looking at respective DT or ACPI entries. Unlike traditional sinks, TRBE can generate interrupts to signal including many other things, buffer got filled. The interrupt is a PPI and should be communicated from the platform. DT or ACPI entry representing TRBE should have the PPI number for a given platform. During perf session, the TRBE IRQ handler should capture trace for perf auxiliary buffer before restarting it back. System registers being used here to configure ETE and TRBE could be referred in the link below. https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers. Things todo: - Improve TRBE IRQ handling for all possible corner cases - Implement sysfs based trace sessions [0] https://lore.kernel.org/linux-arm-kernel/20201214173731.302520-1-suzuki.poulose@arm.com/ [1] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/sysreg-v5 [2] https://gitlab.arm.com/linux-arm/linux-anshuman/-/tree/coresight/ete_trbe_v1 Changes in V1: - There are not much ETE changes from Suzuki apart from splitting of the ETE DTS patch - TRBE changes have been captured in the respective patches Changes in RFC: https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khandual@arm.com/ Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Linu Cherian <lcherian@marvell.com> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Anshuman Khandual (5): arm64: Add TRBE definitions coresight: core: Add support for dedicated percpu sinks coresight: etm-perf: Truncate the perf record if handle has no space coresight: sink: Add TRBE driver dts: bindings: Document device tree binding for Arm TRBE Suzuki K Poulose (6): coresight: etm-perf: Allow an event to use different sinks coresight: Do not scan for graph if none is present coresight: etm4x: Add support for PE OS lock coresight: ete: Add support for ETE sysreg access coresight: ete: Add support for ETE tracing dts: bindings: Document device tree bindings for ETE Documentation/devicetree/bindings/arm/ete.txt | 41 + Documentation/devicetree/bindings/arm/trbe.txt | 20 + Documentation/trace/coresight/coresight-trbe.rst | 39 + arch/arm64/include/asm/sysreg.h | 51 ++ drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 14 + drivers/hwtracing/coresight/coresight-etm-perf.c | 51 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 138 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 64 +- drivers/hwtracing/coresight/coresight-platform.c | 6 + drivers/hwtracing/coresight/coresight-trbe.c | 925 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.h | 248 ++++++ include/linux/coresight.h | 12 + 14 files changed, 1580 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/ete.txt create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt create mode 100644 Documentation/trace/coresight/coresight-trbe.rst create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2020-12-23 10:04 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-23 10:03 Anshuman Khandual [this message] 2020-12-23 10:03 ` [PATCH 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual 2020-12-23 10:03 ` [PATCH 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-03 17:02 ` Rob Herring 2021-01-03 17:02 ` Rob Herring 2021-01-04 14:42 ` Suzuki K Poulose 2021-01-04 14:42 ` Suzuki K Poulose 2021-01-04 18:15 ` Mathieu Poirier 2021-01-04 18:15 ` Mathieu Poirier 2021-01-04 20:31 ` Rob Herring 2021-01-04 20:31 ` Rob Herring 2020-12-23 10:03 ` [PATCH 07/11] arm64: Add TRBE definitions Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 10/11] coresight: sink: Add TRBE driver Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-04 16:28 ` Suzuki K Poulose 2021-01-04 16:28 ` Suzuki K Poulose 2021-01-05 9:29 ` Anshuman Khandual 2021-01-05 9:29 ` Anshuman Khandual 2021-01-05 11:37 ` Suzuki K Poulose 2021-01-05 11:37 ` Suzuki K Poulose 2021-01-06 11:50 ` Anshuman Khandual 2021-01-06 11:50 ` Anshuman Khandual 2021-01-07 14:01 ` Suzuki K Poulose 2021-01-07 14:01 ` Suzuki K Poulose 2020-12-23 10:03 ` [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-03 17:05 ` Rob Herring 2021-01-03 17:05 ` Rob Herring 2021-01-04 3:44 ` Anshuman Khandual 2021-01-04 3:44 ` Anshuman Khandual 2021-01-07 14:05 ` Suzuki K Poulose 2021-01-07 14:05 ` Suzuki K Poulose
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