From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: linux-kernel@vger.kernel.org, Anshuman Khandual <anshuman.khandual@arm.com>, Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Linu Cherian <lcherian@marvell.com> Subject: [PATCH 08/11] coresight: core: Add support for dedicated percpu sinks Date: Wed, 23 Dec 2020 15:33:40 +0530 [thread overview] Message-ID: <1608717823-18387-9-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1608717823-18387-1-git-send-email-anshuman.khandual@arm.com> Add support for dedicated sinks that are bound to individual CPUs. (e.g, TRBE). To allow quicker access to the sink for a given CPU bound source, keep a percpu array of the sink devices. Also, add support for building a path to the CPU local sink from the ETM. This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM. This new sink type is exclusively available and can only work with percpu source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC. This defines a percpu structure that accommodates a single coresight_device which can be used to store an initialized instance from a sink driver. As these sinks are exclusively linked and dependent on corresponding percpu sources devices, they should also be the default sink device during a perf session. Outwards device connections are scanned while establishing paths between a source and a sink device. But such connections are not present for certain percpu source and sink devices which are exclusively linked and dependent. Build the path directly and skip connection scanning for such devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Changes in V1: - Replaced post init ETE-TRBE link configuration with dynamic path creation drivers/hwtracing/coresight/coresight-core.c | 14 ++++++++++++++ include/linux/coresight.h | 12 ++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0062c89..b300606 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -23,6 +23,7 @@ #include "coresight-priv.h" static DEFINE_MUTEX(coresight_mutex); +DEFINE_PER_CPU(struct coresight_device *, csdev_sink); /** * struct coresight_node - elements of a path, from source to sink @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev, if (csdev == sink) goto out; + if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) && + sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) { + _coresight_build_path(sink, sink, path); + found = true; + goto out; + } + /* Not a sink - recursively explore each port found on this element */ for (i = 0; i < csdev->pdata->nr_outport; i++) { struct coresight_device *child_dev; @@ -998,6 +1006,12 @@ coresight_find_default_sink(struct coresight_device *csdev) { int depth = 0; + if (coresight_is_percpu_source(csdev)) { + csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev)); + if (csdev->def_sink) + return csdev->def_sink; + } + /* look for a default sink if we have not found for this device */ if (!csdev->def_sink) csdev->def_sink = coresight_find_sink(csdev, &depth); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 951ba88..2aee12e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink { CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, + CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, }; enum coresight_dev_subtype_link { @@ -432,6 +433,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o csa->write(val, offset, false, true); } +static inline bool coresight_is_percpu_source(struct coresight_device *csdev) +{ + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && + csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; +} + +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) +{ + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && + csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM; +} #else /* !CONFIG_64BIT */ static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Anshuman Khandual <anshuman.khandual@arm.com>, linux-kernel@vger.kernel.org, Linu Cherian <lcherian@marvell.com>, Mike Leach <mike.leach@linaro.org> Subject: [PATCH 08/11] coresight: core: Add support for dedicated percpu sinks Date: Wed, 23 Dec 2020 15:33:40 +0530 [thread overview] Message-ID: <1608717823-18387-9-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1608717823-18387-1-git-send-email-anshuman.khandual@arm.com> Add support for dedicated sinks that are bound to individual CPUs. (e.g, TRBE). To allow quicker access to the sink for a given CPU bound source, keep a percpu array of the sink devices. Also, add support for building a path to the CPU local sink from the ETM. This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM. This new sink type is exclusively available and can only work with percpu source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC. This defines a percpu structure that accommodates a single coresight_device which can be used to store an initialized instance from a sink driver. As these sinks are exclusively linked and dependent on corresponding percpu sources devices, they should also be the default sink device during a perf session. Outwards device connections are scanned while establishing paths between a source and a sink device. But such connections are not present for certain percpu source and sink devices which are exclusively linked and dependent. Build the path directly and skip connection scanning for such devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Changes in V1: - Replaced post init ETE-TRBE link configuration with dynamic path creation drivers/hwtracing/coresight/coresight-core.c | 14 ++++++++++++++ include/linux/coresight.h | 12 ++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0062c89..b300606 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -23,6 +23,7 @@ #include "coresight-priv.h" static DEFINE_MUTEX(coresight_mutex); +DEFINE_PER_CPU(struct coresight_device *, csdev_sink); /** * struct coresight_node - elements of a path, from source to sink @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev, if (csdev == sink) goto out; + if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) && + sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) { + _coresight_build_path(sink, sink, path); + found = true; + goto out; + } + /* Not a sink - recursively explore each port found on this element */ for (i = 0; i < csdev->pdata->nr_outport; i++) { struct coresight_device *child_dev; @@ -998,6 +1006,12 @@ coresight_find_default_sink(struct coresight_device *csdev) { int depth = 0; + if (coresight_is_percpu_source(csdev)) { + csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev)); + if (csdev->def_sink) + return csdev->def_sink; + } + /* look for a default sink if we have not found for this device */ if (!csdev->def_sink) csdev->def_sink = coresight_find_sink(csdev, &depth); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 951ba88..2aee12e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink { CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, + CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, }; enum coresight_dev_subtype_link { @@ -432,6 +433,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o csa->write(val, offset, false, true); } +static inline bool coresight_is_percpu_source(struct coresight_device *csdev) +{ + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && + csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; +} + +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) +{ + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && + csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM; +} #else /* !CONFIG_64BIT */ static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-23 10:05 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-23 10:03 [PATCH 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-03 17:02 ` Rob Herring 2021-01-03 17:02 ` Rob Herring 2021-01-04 14:42 ` Suzuki K Poulose 2021-01-04 14:42 ` Suzuki K Poulose 2021-01-04 18:15 ` Mathieu Poirier 2021-01-04 18:15 ` Mathieu Poirier 2021-01-04 20:31 ` Rob Herring 2021-01-04 20:31 ` Rob Herring 2020-12-23 10:03 ` [PATCH 07/11] arm64: Add TRBE definitions Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual [this message] 2020-12-23 10:03 ` [PATCH 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual 2020-12-23 10:03 ` [PATCH 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2020-12-23 10:03 ` [PATCH 10/11] coresight: sink: Add TRBE driver Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-04 16:28 ` Suzuki K Poulose 2021-01-04 16:28 ` Suzuki K Poulose 2021-01-05 9:29 ` Anshuman Khandual 2021-01-05 9:29 ` Anshuman Khandual 2021-01-05 11:37 ` Suzuki K Poulose 2021-01-05 11:37 ` Suzuki K Poulose 2021-01-06 11:50 ` Anshuman Khandual 2021-01-06 11:50 ` Anshuman Khandual 2021-01-07 14:01 ` Suzuki K Poulose 2021-01-07 14:01 ` Suzuki K Poulose 2020-12-23 10:03 ` [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual 2020-12-23 10:03 ` Anshuman Khandual 2021-01-03 17:05 ` Rob Herring 2021-01-03 17:05 ` Rob Herring 2021-01-04 3:44 ` Anshuman Khandual 2021-01-04 3:44 ` Anshuman Khandual 2021-01-07 14:05 ` Suzuki K Poulose 2021-01-07 14:05 ` Suzuki K Poulose
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