From: Ulf Hansson <ulf.hansson@linaro.org> To: "Rafael J . Wysocki" <rjw@rjwysocki.net>, Sudeep Holla <sudeep.holla@arm.com>, Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>, Mark Rutland <mark.rutland@arm.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, linux-pm@vger.kernel.org Cc: "Raju P . L . S . S . S . N" <rplsssn@codeaurora.org>, Stephen Boyd <sboyd@kernel.org>, Tony Lindgren <tony@atomide.com>, Kevin Hilman <khilman@kernel.org>, Lina Iyer <ilina@codeaurora.org>, Ulf Hansson <ulf.hansson@linaro.org>, Viresh Kumar <viresh.kumar@linaro.org>, Vincent Guittot <vincent.guittot@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Lina Iyer <lina.iyer@linaro.org> Subject: [PATCH v10 05/27] dt: psci: Update DT bindings to support hierarchical PSCI states Date: Thu, 29 Nov 2018 18:46:38 +0100 [thread overview] Message-ID: <20181129174700.16585-6-ulf.hansson@linaro.org> (raw) In-Reply-To: <20181129174700.16585-1-ulf.hansson@linaro.org> From: Lina Iyer <lina.iyer@linaro.org> Update DT bindings to represent hierarchical CPU and CPU PM domain idle states for PSCI. Also update the PSCI examples to clearly show how flattened and hierarchical idle states can be represented in DT. Cc: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Co-developed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> --- Change in V10: - Clarified that the new hierarchical representation is orthogonal to OS-initiated vs platform-coordinated PSCI CPU suspend mode. - Clarified the representation for "arm,psci-suspend-param" in regards to the flattened vs hierarchical model. - Added power-domain-names property to the CPU nodes, as to avoid future churns, if ever multiple power-domains specifiers. --- .../devicetree/bindings/arm/psci.txt | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d52492..e6d3553c8df8 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,173 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +ARM systems can have multiple cores sometimes in hierarchical arrangement. +This often, but not always, maps directly to the processor power topology of +the system. Individual nodes in a topology have their own specific power states +and can be better represented in DT hierarchically. + +For these cases, the definitions of the idle states for the CPUs and the CPU +topology, must conform to the domain idle state specification [3]. The domain +idle states themselves, must be compatible with the defined 'domain-idle-state' +binding [1], and also need to specify the arm,psci-suspend-param property for +each idle state. + +DT allows representing CPUs and CPU idle states in two different ways - + +The flattened model as given in Example 1, lists CPU's idle states followed by +the domain idle state that the CPUs may choose. Note that the idle states are +all compatible with "arm,idle-state". Additionally, for the domain idle state +the "arm,psci-suspend-param" represents a superset of the CPU's idle state. + +Example 2 represents the hierarchical model of CPUs and domain idle states. +CPUs define their domain provider in their psci DT node. The domain controls +the power to the CPU and possibly other h/w blocks that would enter an idle +state along with the CPU. The CPU's idle states may therefore be considered as +the domain's idle states and have the compatible "arm,idle-state". Such domains +may also be embedded within another domain that may represent common h/w blocks +between these CPUs. The idle states of the CPU topology shall be represented as +the domain's idle states. Note that for the domain idle state, the +"arm,psci-suspend-param" represents idle states hierarchically. + +In PSCI firmware v1.0, the OS-Initiated mode is introduced. However, the +flattened vs hierarchical DT representation is orthogonal to the OS-Initiated +vs the platform-coordinated PSCI CPU suspend modes, thus should be considered +independent of each other. + +The hierarchical representation helps and makes it easy to implement OSI mode +and OS implementations may choose to mandate it. For the default platform- +coordinated mode, both representations are viable options. + +Example 1: Flattened representation of CPU and domain idle states + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Example 2: Hierarchical representation of CPU and domain idle states + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Ulf Hansson <ulf.hansson@linaro.org> To: "Rafael J . Wysocki" <rjw@rjwysocki.net>, Sudeep Holla <sudeep.holla@arm.com>, Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>, Mark Rutland <mark.rutland@arm.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, linux-pm@vger.kernel.org Cc: Ulf Hansson <ulf.hansson@linaro.org>, Vincent Guittot <vincent.guittot@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Kevin Hilman <khilman@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Viresh Kumar <viresh.kumar@linaro.org>, linux-kernel@vger.kernel.org, Lina Iyer <ilina@codeaurora.org>, Tony Lindgren <tony@atomide.com>, Lina Iyer <lina.iyer@linaro.org>, linux-arm-msm@vger.kernel.org, "Raju P . L . S . S . S . N" <rplsssn@codeaurora.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 05/27] dt: psci: Update DT bindings to support hierarchical PSCI states Date: Thu, 29 Nov 2018 18:46:38 +0100 [thread overview] Message-ID: <20181129174700.16585-6-ulf.hansson@linaro.org> (raw) In-Reply-To: <20181129174700.16585-1-ulf.hansson@linaro.org> From: Lina Iyer <lina.iyer@linaro.org> Update DT bindings to represent hierarchical CPU and CPU PM domain idle states for PSCI. Also update the PSCI examples to clearly show how flattened and hierarchical idle states can be represented in DT. Cc: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Co-developed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> --- Change in V10: - Clarified that the new hierarchical representation is orthogonal to OS-initiated vs platform-coordinated PSCI CPU suspend mode. - Clarified the representation for "arm,psci-suspend-param" in regards to the flattened vs hierarchical model. - Added power-domain-names property to the CPU nodes, as to avoid future churns, if ever multiple power-domains specifiers. --- .../devicetree/bindings/arm/psci.txt | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d52492..e6d3553c8df8 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,173 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +ARM systems can have multiple cores sometimes in hierarchical arrangement. +This often, but not always, maps directly to the processor power topology of +the system. Individual nodes in a topology have their own specific power states +and can be better represented in DT hierarchically. + +For these cases, the definitions of the idle states for the CPUs and the CPU +topology, must conform to the domain idle state specification [3]. The domain +idle states themselves, must be compatible with the defined 'domain-idle-state' +binding [1], and also need to specify the arm,psci-suspend-param property for +each idle state. + +DT allows representing CPUs and CPU idle states in two different ways - + +The flattened model as given in Example 1, lists CPU's idle states followed by +the domain idle state that the CPUs may choose. Note that the idle states are +all compatible with "arm,idle-state". Additionally, for the domain idle state +the "arm,psci-suspend-param" represents a superset of the CPU's idle state. + +Example 2 represents the hierarchical model of CPUs and domain idle states. +CPUs define their domain provider in their psci DT node. The domain controls +the power to the CPU and possibly other h/w blocks that would enter an idle +state along with the CPU. The CPU's idle states may therefore be considered as +the domain's idle states and have the compatible "arm,idle-state". Such domains +may also be embedded within another domain that may represent common h/w blocks +between these CPUs. The idle states of the CPU topology shall be represented as +the domain's idle states. Note that for the domain idle state, the +"arm,psci-suspend-param" represents idle states hierarchically. + +In PSCI firmware v1.0, the OS-Initiated mode is introduced. However, the +flattened vs hierarchical DT representation is orthogonal to the OS-Initiated +vs the platform-coordinated PSCI CPU suspend modes, thus should be considered +independent of each other. + +The hierarchical representation helps and makes it easy to implement OSI mode +and OS implementations may choose to mandate it. For the default platform- +coordinated mode, both representations are viable options. + +Example 1: Flattened representation of CPU and domain idle states + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Example 2: Hierarchical representation of CPU and domain idle states + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-11-29 17:46 UTC|newest] Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-29 17:46 [PATCH v10 00/27] PM / Domains: Support hierarchical CPU arrangement (PSCI/ARM) Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 01/27] PM / Domains: Add generic data pointer to genpd_power_state struct Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-18 10:39 ` Daniel Lezcano 2018-12-18 10:39 ` Daniel Lezcano 2018-12-18 11:53 ` Ulf Hansson 2018-12-18 11:53 ` Ulf Hansson 2019-01-11 10:52 ` Rafael J. Wysocki 2019-01-11 10:52 ` Rafael J. Wysocki 2018-11-29 17:46 ` [PATCH v10 02/27] PM / Domains: Add support for CPU devices to genpd Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 9:53 ` Daniel Lezcano 2018-12-19 9:53 ` Daniel Lezcano 2018-12-19 10:02 ` Ulf Hansson 2018-12-19 10:02 ` Ulf Hansson 2019-01-11 10:54 ` Rafael J. Wysocki 2019-01-11 10:54 ` Rafael J. Wysocki 2018-11-29 17:46 ` [PATCH v10 03/27] timer: Export next wakeup time of a CPU Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2019-01-11 11:06 ` Rafael J. Wysocki 2019-01-11 11:06 ` Rafael J. Wysocki 2019-01-11 11:06 ` Rafael J. Wysocki 2019-01-16 7:57 ` Ulf Hansson 2019-01-16 7:57 ` Ulf Hansson 2019-01-16 7:57 ` Ulf Hansson 2019-01-16 10:59 ` Rafael J. Wysocki 2019-01-16 10:59 ` Rafael J. Wysocki 2019-01-16 10:59 ` Rafael J. Wysocki 2019-01-16 12:00 ` Ulf Hansson 2019-01-16 12:00 ` Ulf Hansson 2019-01-16 12:00 ` Ulf Hansson 2019-01-25 10:04 ` Ulf Hansson 2019-01-25 10:04 ` Ulf Hansson 2019-01-25 10:04 ` Ulf Hansson 2019-01-25 10:18 ` Rafael J. Wysocki 2019-01-25 10:18 ` Rafael J. Wysocki 2019-01-25 10:18 ` Rafael J. Wysocki 2018-11-29 17:46 ` [PATCH v10 04/27] PM / Domains: Add genpd governor for CPUs Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 9:54 ` Daniel Lezcano 2018-12-19 9:54 ` Daniel Lezcano 2018-12-19 10:09 ` Ulf Hansson 2018-12-19 10:09 ` Ulf Hansson 2018-12-19 10:09 ` Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson [this message] 2018-11-29 17:46 ` [PATCH v10 05/27] dt: psci: Update DT bindings to support hierarchical PSCI states Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 06/27] of: base: Add of_get_cpu_state_node() to get idle states for a CPU node Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 11:05 ` Daniel Lezcano 2018-12-19 11:05 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 07/27] cpuidle: dt: Support hierarchical CPU idle states Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 11:20 ` Daniel Lezcano 2018-12-19 11:20 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 08/27] ARM/ARM64: cpuidle: Let back-end init ops take the driver as input Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 09/27] drivers: firmware: psci: Move psci to separate directory Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 10/27] MAINTAINERS: Update files for PSCI Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 11/27] drivers: firmware: psci: Split psci_dt_cpu_init_idle() Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 12/27] drivers: firmware: psci: Simplify state node parsing Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 13/27] drivers: firmware: psci: Support hierarchical CPU idle states Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 12:11 ` Daniel Lezcano 2018-12-19 12:11 ` Daniel Lezcano 2018-12-19 12:53 ` Ulf Hansson 2018-12-19 12:53 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 14/27] drivers: firmware: psci: Simplify error path of psci_dt_init() Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-19 12:08 ` Daniel Lezcano 2018-12-19 12:08 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 15/27] drivers: firmware: psci: Announce support for OS initiated suspend mode Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-20 13:11 ` Daniel Lezcano 2018-12-20 13:11 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 16/27] drivers: firmware: psci: Prepare to use " Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-20 14:08 ` Daniel Lezcano 2018-12-20 14:08 ` Daniel Lezcano 2018-12-20 15:41 ` Ulf Hansson 2018-12-20 15:41 ` Ulf Hansson 2018-12-20 17:16 ` Daniel Lezcano 2018-12-20 17:16 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 17/27] drivers: firmware: psci: Prepare to support PM domains Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-20 14:19 ` Daniel Lezcano 2018-12-20 14:19 ` Daniel Lezcano 2018-12-20 15:49 ` Ulf Hansson 2018-12-20 15:49 ` Ulf Hansson 2018-12-20 18:06 ` Daniel Lezcano 2018-12-20 18:06 ` Daniel Lezcano 2018-12-20 21:37 ` Ulf Hansson 2018-12-20 21:37 ` Ulf Hansson 2018-12-21 7:15 ` Daniel Lezcano 2018-12-21 7:15 ` Daniel Lezcano 2018-11-29 17:46 ` [PATCH v10 18/27] drivers: firmware: psci: Add support for PM domains using genpd Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-03 16:37 ` Lina Iyer 2018-12-03 16:37 ` Lina Iyer 2018-12-03 20:03 ` Ulf Hansson 2018-12-03 20:03 ` Ulf Hansson 2018-12-20 14:35 ` Daniel Lezcano 2018-12-20 14:35 ` Daniel Lezcano 2018-12-20 21:09 ` Ulf Hansson 2018-12-20 21:09 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 19/27] drivers: firmware: psci: Add hierarchical domain idle states converter Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 20/27] drivers: firmware: psci: Introduce psci_dt_topology_init() Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 21/27] drivers: firmware: psci: Add a helper to attach a CPU to its PM domain Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-12-04 18:45 ` Lina Iyer 2018-12-04 18:45 ` Lina Iyer 2018-12-06 9:15 ` Ulf Hansson 2018-12-06 9:15 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 22/27] drivers: firmware: psci: Attach the CPU's device " Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 23/27] drivers: firmware: psci: Manage runtime PM in the idle path for CPUs Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 24/27] drivers: firmware: psci: Support CPU hotplug for the hierarchical model Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 22:31 ` Lina Iyer 2018-11-29 22:31 ` Lina Iyer 2018-11-30 8:25 ` Ulf Hansson 2018-11-30 8:25 ` Ulf Hansson 2018-11-30 20:57 ` Lina Iyer 2018-11-30 20:57 ` Lina Iyer 2018-12-19 11:17 ` Lorenzo Pieralisi 2018-12-19 11:17 ` Lorenzo Pieralisi 2018-12-19 11:47 ` Ulf Hansson 2018-12-19 11:47 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 25/27] arm64: kernel: Respect the hierarchical CPU topology in DT for PSCI Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:46 ` [PATCH v10 26/27] arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 Ulf Hansson 2018-11-29 17:46 ` Ulf Hansson 2018-11-29 17:47 ` [PATCH v10 27/27] arm64: dts: hikey: Convert to the hierarchical CPU topology layout Ulf Hansson 2018-11-29 17:47 ` Ulf Hansson 2018-12-17 16:12 ` [PATCH v10 00/27] PM / Domains: Support hierarchical CPU arrangement (PSCI/ARM) Ulf Hansson 2018-12-17 16:12 ` Ulf Hansson 2019-01-11 11:08 ` Rafael J. Wysocki 2019-01-11 11:08 ` Rafael J. Wysocki 2019-01-03 12:06 ` Sudeep Holla 2019-01-03 12:06 ` Sudeep Holla 2019-01-03 12:06 ` Sudeep Holla 2019-01-16 9:10 ` Ulf Hansson 2019-01-16 9:10 ` Ulf Hansson 2019-01-17 17:44 ` Sudeep Holla 2019-01-17 17:44 ` Sudeep Holla 2019-01-17 17:44 ` Sudeep Holla 2019-01-18 11:56 ` Ulf Hansson 2019-01-18 11:56 ` Ulf Hansson
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20181129174700.16585-6-ulf.hansson@linaro.org \ --to=ulf.hansson@linaro.org \ --cc=Lorenzo.Pieralisi@arm.com \ --cc=daniel.lezcano@linaro.org \ --cc=geert+renesas@glider.be \ --cc=ilina@codeaurora.org \ --cc=khilman@kernel.org \ --cc=lina.iyer@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pm@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=rjw@rjwysocki.net \ --cc=rplsssn@codeaurora.org \ --cc=sboyd@kernel.org \ --cc=sudeep.holla@arm.com \ --cc=tony@atomide.com \ --cc=vincent.guittot@linaro.org \ --cc=viresh.kumar@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.