From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v8 1/7] drm/i915/tgl: Add DC3CO required register and bits
Date: Fri, 13 Sep 2019 13:53:33 +0530 [thread overview]
Message-ID: <20190913082339.1785-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190913082339.1785-1-anshuman.gupta@intel.com>
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v1: Use of REG_BIT and using extra space for EXITLINE_ macro
definition. [Animesh]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4138,6 +4138,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4184,11 +4185,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE REG_BIT(31)
+#define EXITLINE_MASK REG_GENMASK(12, 0)
+#define EXITLINE_SHIFT 0
+
/*
* HSW+ eDP PSR registers
*
@@ -10118,6 +10124,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN _MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO REG_BIT(30)
+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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next prev parent reply other threads:[~2019-09-13 8:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-13 8:23 [PATCH v8 0/7] DC3CO Support for TGL Anshuman Gupta
2019-09-13 8:23 ` Anshuman Gupta [this message]
2019-09-16 13:24 ` [PATCH v8 1/7] drm/i915/tgl: Add DC3CO required register and bits Animesh Manna
2019-09-13 8:23 ` [PATCH v8 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-09-16 13:25 ` Animesh Manna
2019-09-13 8:23 ` [PATCH v8 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
2019-09-23 16:21 ` Imre Deak
2019-09-13 8:23 ` [PATCH v8 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
2019-09-23 16:26 ` Imre Deak
2019-09-24 6:13 ` [PATCH v8 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline.y Anshuman Gupta
2019-09-25 9:10 ` [PATCH v8 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
2019-09-25 12:26 ` Imre Deak
2019-09-13 8:23 ` [PATCH v8 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-09-23 16:42 ` Imre Deak
2019-09-23 17:56 ` Anshuman Gupta
2019-09-13 8:23 ` [PATCH v8 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-09-23 16:46 ` Imre Deak
2019-09-13 8:23 ` [PATCH v8 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-09-13 12:17 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev9) Patchwork
2019-09-13 12:20 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-09-13 12:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-14 10:21 ` ✓ Fi.CI.IGT: " Patchwork
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