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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/5] drm/i915: Drop unused AUX register offsets
Date: Fri, 25 Oct 2019 16:06:20 -0700	[thread overview]
Message-ID: <20191025230623.27829-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20191025230623.27829-1-matthew.d.roper@intel.com>

We reference DP AUX registers via the DP_AUX_CH_CTL() and
DP_AUX_CH_DATA() macros that calculate all the register offsets for us
automatically; there's no need to explicitly define every offset in
i915_reg.h if they're never going to be used by the driver code.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 36 ---------------------------------
 1 file changed, 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cd40e7af618..cbf6df002771 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5538,45 +5538,9 @@ enum {
  */
 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
-#define _DPA_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
-#define _DPA_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
-#define _DPA_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
-#define _DPA_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
 
 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
-#define _DPB_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
-#define _DPB_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
-#define _DPB_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
-#define _DPB_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
-
-#define _DPC_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
-#define _DPC_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
-#define _DPC_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
-#define _DPC_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
-#define _DPC_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
-#define _DPC_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
-
-#define _DPD_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
-#define _DPD_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
-#define _DPD_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
-#define _DPD_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
-#define _DPD_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
-#define _DPD_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
-
-#define _DPE_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
-#define _DPE_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
-#define _DPE_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
-#define _DPE_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
-#define _DPE_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
-#define _DPE_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
-
-#define _DPF_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
-#define _DPF_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
-#define _DPF_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
-#define _DPF_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
-#define _DPF_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
-#define _DPF_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
 
 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Drop unused AUX register offsets
Date: Fri, 25 Oct 2019 16:06:20 -0700	[thread overview]
Message-ID: <20191025230623.27829-3-matthew.d.roper@intel.com> (raw)
Message-ID: <20191025230620.m_-u8dgYFdBiqZXBb1co_shgo1nEK5diMgTYtJCmAi4@z> (raw)
In-Reply-To: <20191025230623.27829-1-matthew.d.roper@intel.com>

We reference DP AUX registers via the DP_AUX_CH_CTL() and
DP_AUX_CH_DATA() macros that calculate all the register offsets for us
automatically; there's no need to explicitly define every offset in
i915_reg.h if they're never going to be used by the driver code.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 36 ---------------------------------
 1 file changed, 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cd40e7af618..cbf6df002771 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5538,45 +5538,9 @@ enum {
  */
 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
-#define _DPA_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
-#define _DPA_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
-#define _DPA_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
-#define _DPA_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
 
 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
-#define _DPB_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
-#define _DPB_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
-#define _DPB_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
-#define _DPB_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
-
-#define _DPC_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
-#define _DPC_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
-#define _DPC_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
-#define _DPC_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
-#define _DPC_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
-#define _DPC_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
-
-#define _DPD_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
-#define _DPD_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
-#define _DPD_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
-#define _DPD_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
-#define _DPD_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
-#define _DPD_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
-
-#define _DPE_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
-#define _DPE_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
-#define _DPE_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
-#define _DPE_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
-#define _DPE_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
-#define _DPE_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
-
-#define _DPF_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
-#define _DPF_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
-#define _DPF_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
-#define _DPF_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
-#define _DPF_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
-#define _DPF_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
 
 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-25 23:06 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-25 23:06 [PATCH 0/5] DP AUX updates Matt Roper
2019-10-25 23:06 ` [Intel-gfx] " Matt Roper
2019-10-25 23:06 ` [PATCH 1/5] drm/i915/tgl: Handle AUX interrupts for TC ports Matt Roper
2019-10-25 23:06   ` [Intel-gfx] " Matt Roper
2019-10-25 23:11   ` Lucas De Marchi
2019-10-25 23:11     ` [Intel-gfx] " Lucas De Marchi
2019-10-25 23:06 ` Matt Roper [this message]
2019-10-25 23:06   ` [Intel-gfx] [PATCH 2/5] drm/i915: Drop unused AUX register offsets Matt Roper
2019-10-25 23:11   ` Lucas De Marchi
2019-10-25 23:11     ` [Intel-gfx] " Lucas De Marchi
2019-10-26  5:12   ` Matt Roper
2019-10-26  5:12     ` [Intel-gfx] " Matt Roper
2019-10-25 23:06 ` [PATCH 3/5] drm/i915: Add missing AUX channel H & I support Matt Roper
2019-10-25 23:06   ` [Intel-gfx] " Matt Roper
2019-10-25 23:13   ` Lucas De Marchi
2019-10-25 23:13     ` [Intel-gfx] " Lucas De Marchi
2019-10-28 14:57     ` Matt Roper
2019-10-28 14:57       ` [Intel-gfx] " Matt Roper
2019-10-29 17:59       ` Lucas De Marchi
2019-10-29 17:59         ` [Intel-gfx] " Lucas De Marchi
2019-10-25 23:06 ` [PATCH 4/5] drm/i915: Provide more information on DP AUX failures Matt Roper
2019-10-25 23:06   ` [Intel-gfx] " Matt Roper
2019-10-25 23:19   ` Lucas De Marchi
2019-10-25 23:19     ` [Intel-gfx] " Lucas De Marchi
2019-10-25 23:25     ` Matt Roper
2019-10-25 23:25       ` [Intel-gfx] " Matt Roper
2019-10-25 23:32       ` Lucas De Marchi
2019-10-25 23:32         ` [Intel-gfx] " Lucas De Marchi
2019-10-29 17:31     ` [PATCH v2 " Matt Roper
2019-10-29 17:31       ` [Intel-gfx] " Matt Roper
2019-10-29 19:33       ` Lucas De Marchi
2019-10-29 19:33         ` [Intel-gfx] " Lucas De Marchi
2019-10-28 16:43   ` [PATCH " Ville Syrjälä
2019-10-28 16:43     ` [Intel-gfx] " Ville Syrjälä
2019-10-25 23:06 ` [PATCH 5/5] drm/i915/tgl: Add AUX B & C to DC_OFF_POWER_DOMAINS Matt Roper
2019-10-25 23:06   ` [Intel-gfx] " Matt Roper
2019-10-25 23:24   ` Lucas De Marchi
2019-10-25 23:24     ` [Intel-gfx] " Lucas De Marchi
2019-10-26  8:57   ` Imre Deak
2019-10-26  8:57     ` [Intel-gfx] " Imre Deak
2019-10-26  1:09 ` ✗ Fi.CI.BUILD: failure for DP AUX updates Patchwork
2019-10-26  1:09   ` [Intel-gfx] " Patchwork
2019-10-26  5:37 ` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev2) Patchwork
2019-10-26  5:37   ` [Intel-gfx] " Patchwork
2019-10-26  5:57 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-26  5:57   ` [Intel-gfx] " Patchwork
2019-10-26  6:26 ` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev3) Patchwork
2019-10-26  6:26   ` [Intel-gfx] " Patchwork
2019-10-26  6:47 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-26  6:47   ` [Intel-gfx] " Patchwork
2019-10-28  1:02 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-28  1:02   ` [Intel-gfx] " Patchwork
2019-10-29 17:58   ` Matt Roper
2019-10-29 17:58     ` [Intel-gfx] " Matt Roper
2019-10-29 19:56     ` Matt Roper
2019-10-29 19:56       ` [Intel-gfx] " Matt Roper

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