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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Robert Richter <rrichter@marvell.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Eric Auger <eric.auger@redhat.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor
Date: Wed,  4 Mar 2020 20:33:27 +0000	[thread overview]
Message-ID: <20200304203330.4967-21-maz@kernel.org> (raw)
In-Reply-To: <20200304203330.4967-1-maz@kernel.org>

The GICv4.1 architecture gives the hypervisor the option to let
the guest choose whether it wants the good old SGIs with an
active state, or the new, HW-based ones that do not have one.

For this, plumb the configuration of SGIs into the GICv3 MMIO
handling, present the GICD_TYPER2.nASSGIcap to the guest,
and handle the GICD_CTLR.nASSGIreq setting.

In order to be able to deal with the restore of a guest, also
apply the GICD_CTLR.nASSGIreq setting at first run so that we
can move the restored SGIs to the HW if that's what the guest
had selected in a previous life.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 virt/kvm/arm/vgic/vgic-mmio-v3.c | 48 ++++++++++++++++++++++++++++++--
 virt/kvm/arm/vgic/vgic-v3.c      |  2 ++
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
index de89da76a379..442f3b8c2559 100644
--- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
+++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
@@ -3,6 +3,7 @@
  * VGICv3 MMIO handling functions
  */
 
+#include <linux/bitfield.h>
 #include <linux/irqchip/arm-gic-v3.h>
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
@@ -70,6 +71,8 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 		if (vgic->enabled)
 			value |= GICD_CTLR_ENABLE_SS_G1;
 		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
+		if (kvm_vgic_global_state.has_gicv4_1 && vgic->nassgireq)
+			value |= GICD_CTLR_nASSGIreq;
 		break;
 	case GICD_TYPER:
 		value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
@@ -81,6 +84,10 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 			value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
 		}
 		break;
+	case GICD_TYPER2:
+		if (kvm_vgic_global_state.has_gicv4_1)
+			value = GICD_TYPER2_nASSGIcap;
+		break;
 	case GICD_IIDR:
 		value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
 			(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
@@ -98,17 +105,43 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 				    unsigned long val)
 {
 	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-	bool was_enabled = dist->enabled;
 
 	switch (addr & 0x0c) {
-	case GICD_CTLR:
+	case GICD_CTLR: {
+		bool was_enabled, is_hwsgi;
+
+		mutex_lock(&vcpu->kvm->lock);
+
+		was_enabled = dist->enabled;
+		is_hwsgi = dist->nassgireq;
+
 		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		/* Dist stays enabled? nASSGIreq is RO */
+		if (was_enabled && dist->enabled) {
+			val &= ~GICD_CTLR_nASSGIreq;
+			val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
+		}
+
+		/* Switching HW SGIs? */
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		if (is_hwsgi != dist->nassgireq)
+			vgic_v4_configure_vsgis(vcpu->kvm);
+
 		if (!was_enabled && dist->enabled)
 			vgic_kick_vcpus(vcpu->kvm);
+
+		mutex_unlock(&vcpu->kvm->lock);
 		break;
+	}
 	case GICD_TYPER:
+	case GICD_TYPER2:
 	case GICD_IIDR:
+		/* This is at best for documentation purposes... */
 		return;
 	}
 }
@@ -117,10 +150,21 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 					   gpa_t addr, unsigned int len,
 					   unsigned long val)
 {
+	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+
 	switch (addr & 0x0c) {
 	case GICD_IIDR:
 		if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 			return -EINVAL;
+		return 0;
+	case GICD_CTLR:
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		return 0;
 	}
 
 	vgic_mmio_write_v3_misc(vcpu, addr, len, val);
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index 1bc09b523486..2c9fc13e2c59 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
 		goto out;
 	}
 
+	if (kvm_vgic_global_state.has_gicv4_1)
+		vgic_v4_configure_vsgis(kvm);
 	dist->ready = true;
 
 out:
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Robert Richter <rrichter@marvell.com>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor
Date: Wed,  4 Mar 2020 20:33:27 +0000	[thread overview]
Message-ID: <20200304203330.4967-21-maz@kernel.org> (raw)
In-Reply-To: <20200304203330.4967-1-maz@kernel.org>

The GICv4.1 architecture gives the hypervisor the option to let
the guest choose whether it wants the good old SGIs with an
active state, or the new, HW-based ones that do not have one.

For this, plumb the configuration of SGIs into the GICv3 MMIO
handling, present the GICD_TYPER2.nASSGIcap to the guest,
and handle the GICD_CTLR.nASSGIreq setting.

In order to be able to deal with the restore of a guest, also
apply the GICD_CTLR.nASSGIreq setting at first run so that we
can move the restored SGIs to the HW if that's what the guest
had selected in a previous life.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 virt/kvm/arm/vgic/vgic-mmio-v3.c | 48 ++++++++++++++++++++++++++++++--
 virt/kvm/arm/vgic/vgic-v3.c      |  2 ++
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
index de89da76a379..442f3b8c2559 100644
--- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
+++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
@@ -3,6 +3,7 @@
  * VGICv3 MMIO handling functions
  */
 
+#include <linux/bitfield.h>
 #include <linux/irqchip/arm-gic-v3.h>
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
@@ -70,6 +71,8 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 		if (vgic->enabled)
 			value |= GICD_CTLR_ENABLE_SS_G1;
 		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
+		if (kvm_vgic_global_state.has_gicv4_1 && vgic->nassgireq)
+			value |= GICD_CTLR_nASSGIreq;
 		break;
 	case GICD_TYPER:
 		value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
@@ -81,6 +84,10 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 			value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
 		}
 		break;
+	case GICD_TYPER2:
+		if (kvm_vgic_global_state.has_gicv4_1)
+			value = GICD_TYPER2_nASSGIcap;
+		break;
 	case GICD_IIDR:
 		value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
 			(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
@@ -98,17 +105,43 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 				    unsigned long val)
 {
 	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-	bool was_enabled = dist->enabled;
 
 	switch (addr & 0x0c) {
-	case GICD_CTLR:
+	case GICD_CTLR: {
+		bool was_enabled, is_hwsgi;
+
+		mutex_lock(&vcpu->kvm->lock);
+
+		was_enabled = dist->enabled;
+		is_hwsgi = dist->nassgireq;
+
 		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		/* Dist stays enabled? nASSGIreq is RO */
+		if (was_enabled && dist->enabled) {
+			val &= ~GICD_CTLR_nASSGIreq;
+			val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
+		}
+
+		/* Switching HW SGIs? */
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		if (is_hwsgi != dist->nassgireq)
+			vgic_v4_configure_vsgis(vcpu->kvm);
+
 		if (!was_enabled && dist->enabled)
 			vgic_kick_vcpus(vcpu->kvm);
+
+		mutex_unlock(&vcpu->kvm->lock);
 		break;
+	}
 	case GICD_TYPER:
+	case GICD_TYPER2:
 	case GICD_IIDR:
+		/* This is at best for documentation purposes... */
 		return;
 	}
 }
@@ -117,10 +150,21 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 					   gpa_t addr, unsigned int len,
 					   unsigned long val)
 {
+	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+
 	switch (addr & 0x0c) {
 	case GICD_IIDR:
 		if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 			return -EINVAL;
+		return 0;
+	case GICD_CTLR:
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		return 0;
 	}
 
 	vgic_mmio_write_v3_misc(vcpu, addr, len, val);
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index 1bc09b523486..2c9fc13e2c59 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
 		goto out;
 	}
 
+	if (kvm_vgic_global_state.has_gicv4_1)
+		vgic_v4_configure_vsgis(kvm);
 	dist->ready = true;
 
 out:
-- 
2.20.1

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Eric Auger <eric.auger@redhat.com>,
	Robert Richter <rrichter@marvell.com>,
	James Morse <james.morse@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor
Date: Wed,  4 Mar 2020 20:33:27 +0000	[thread overview]
Message-ID: <20200304203330.4967-21-maz@kernel.org> (raw)
In-Reply-To: <20200304203330.4967-1-maz@kernel.org>

The GICv4.1 architecture gives the hypervisor the option to let
the guest choose whether it wants the good old SGIs with an
active state, or the new, HW-based ones that do not have one.

For this, plumb the configuration of SGIs into the GICv3 MMIO
handling, present the GICD_TYPER2.nASSGIcap to the guest,
and handle the GICD_CTLR.nASSGIreq setting.

In order to be able to deal with the restore of a guest, also
apply the GICD_CTLR.nASSGIreq setting at first run so that we
can move the restored SGIs to the HW if that's what the guest
had selected in a previous life.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 virt/kvm/arm/vgic/vgic-mmio-v3.c | 48 ++++++++++++++++++++++++++++++--
 virt/kvm/arm/vgic/vgic-v3.c      |  2 ++
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
index de89da76a379..442f3b8c2559 100644
--- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
+++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
@@ -3,6 +3,7 @@
  * VGICv3 MMIO handling functions
  */
 
+#include <linux/bitfield.h>
 #include <linux/irqchip/arm-gic-v3.h>
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
@@ -70,6 +71,8 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 		if (vgic->enabled)
 			value |= GICD_CTLR_ENABLE_SS_G1;
 		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
+		if (kvm_vgic_global_state.has_gicv4_1 && vgic->nassgireq)
+			value |= GICD_CTLR_nASSGIreq;
 		break;
 	case GICD_TYPER:
 		value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
@@ -81,6 +84,10 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 			value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
 		}
 		break;
+	case GICD_TYPER2:
+		if (kvm_vgic_global_state.has_gicv4_1)
+			value = GICD_TYPER2_nASSGIcap;
+		break;
 	case GICD_IIDR:
 		value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
 			(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
@@ -98,17 +105,43 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 				    unsigned long val)
 {
 	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-	bool was_enabled = dist->enabled;
 
 	switch (addr & 0x0c) {
-	case GICD_CTLR:
+	case GICD_CTLR: {
+		bool was_enabled, is_hwsgi;
+
+		mutex_lock(&vcpu->kvm->lock);
+
+		was_enabled = dist->enabled;
+		is_hwsgi = dist->nassgireq;
+
 		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		/* Dist stays enabled? nASSGIreq is RO */
+		if (was_enabled && dist->enabled) {
+			val &= ~GICD_CTLR_nASSGIreq;
+			val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
+		}
+
+		/* Switching HW SGIs? */
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		if (is_hwsgi != dist->nassgireq)
+			vgic_v4_configure_vsgis(vcpu->kvm);
+
 		if (!was_enabled && dist->enabled)
 			vgic_kick_vcpus(vcpu->kvm);
+
+		mutex_unlock(&vcpu->kvm->lock);
 		break;
+	}
 	case GICD_TYPER:
+	case GICD_TYPER2:
 	case GICD_IIDR:
+		/* This is at best for documentation purposes... */
 		return;
 	}
 }
@@ -117,10 +150,21 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 					   gpa_t addr, unsigned int len,
 					   unsigned long val)
 {
+	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+
 	switch (addr & 0x0c) {
 	case GICD_IIDR:
 		if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 			return -EINVAL;
+		return 0;
+	case GICD_CTLR:
+		/* Not a GICv4.1? No HW SGIs */
+		if (!kvm_vgic_global_state.has_gicv4_1)
+			val &= ~GICD_CTLR_nASSGIreq;
+
+		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
+		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		return 0;
 	}
 
 	vgic_mmio_write_v3_misc(vcpu, addr, len, val);
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index 1bc09b523486..2c9fc13e2c59 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
 		goto out;
 	}
 
+	if (kvm_vgic_global_state.has_gicv4_1)
+		vgic_v4_configure_vsgis(kvm);
 	dist->ready = true;
 
 out:
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-03-04 20:36 UTC|newest]

Thread overview: 312+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-04 20:33 [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  6:30   ` Zenghui Yu
2020-03-12  6:30     ` Zenghui Yu
2020-03-12  6:30     ` Zenghui Yu
2020-03-12  9:28     ` Marc Zyngier
2020-03-12  9:28       ` Marc Zyngier
2020-03-12  9:28       ` Marc Zyngier
2020-03-12 12:05       ` Marc Zyngier
2020-03-12 12:05         ` Marc Zyngier
2020-03-12 12:05         ` Marc Zyngier
2020-03-13  1:39         ` Zenghui Yu
2020-03-13  1:39           ` Zenghui Yu
2020-03-13  1:39           ` Zenghui Yu
2020-03-12 17:16   ` Auger Eric
2020-03-12 17:16     ` Auger Eric
2020-03-12 17:16     ` Auger Eric
2020-03-12 17:23     ` Marc Zyngier
2020-03-12 17:23       ` Marc Zyngier
2020-03-12 17:23       ` Marc Zyngier
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 02/23] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 17:10   ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 03/23] irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  6:56   ` Zenghui Yu
2020-03-12  6:56     ` Zenghui Yu
2020-03-12  6:56     ` Zenghui Yu
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 04/23] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-20 14:23   ` Auger Eric
2020-03-20 14:23     ` Auger Eric
2020-03-20 14:23     ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 05/23] irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  7:11   ` Zenghui Yu
2020-03-12  7:11     ` Zenghui Yu
2020-03-12  7:11     ` Zenghui Yu
2020-03-20 14:23   ` Auger Eric
2020-03-20 14:23     ` Auger Eric
2020-03-20 14:23     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 06/23] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 17:10   ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 07/23] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 17:10   ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 08/23] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 17:10   ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-16 17:10     ` Auger Eric
2020-03-19 10:03     ` Marc Zyngier
2020-03-19 10:03       ` Marc Zyngier
2020-03-19 10:03       ` Marc Zyngier
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 09/23] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 17:53   ` Auger Eric
2020-03-16 17:53     ` Auger Eric
2020-03-16 17:53     ` Auger Eric
2020-03-17  2:02     ` Zenghui Yu
2020-03-17  2:02       ` Zenghui Yu
2020-03-17  2:02       ` Zenghui Yu
2020-03-17  8:36       ` Auger Eric
2020-03-17  8:36         ` Auger Eric
2020-03-17  8:36         ` Auger Eric
2020-03-19 10:20     ` Marc Zyngier
2020-03-19 10:20       ` Marc Zyngier
2020-03-19 10:20       ` Marc Zyngier
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 10/23] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-16 18:15   ` Auger Eric
2020-03-16 18:15     ` Auger Eric
2020-03-16 18:15     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 11/23] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  7:41   ` Zenghui Yu
2020-03-12  7:41     ` Zenghui Yu
2020-03-12  7:41     ` Zenghui Yu
2020-03-16 21:43   ` Auger Eric
2020-03-16 21:43     ` Auger Eric
2020-03-16 21:43     ` Auger Eric
2020-03-19 10:27     ` Marc Zyngier
2020-03-19 10:27       ` Marc Zyngier
2020-03-19 10:27       ` Marc Zyngier
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 12/23] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-17 10:35   ` Auger Eric
2020-03-17 10:35     ` Auger Eric
2020-03-17 10:35     ` Auger Eric
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 13/23] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  8:20   ` Zenghui Yu
2020-03-12  8:20     ` Zenghui Yu
2020-03-12  8:20     ` Zenghui Yu
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 14/23] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  8:06   ` Zenghui Yu
2020-03-12  8:06     ` Zenghui Yu
2020-03-12  8:06     ` Zenghui Yu
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 15/23] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  8:09   ` Zenghui Yu
2020-03-12  8:09     ` Zenghui Yu
2020-03-12  8:09     ` Zenghui Yu
2020-03-17 10:30   ` Auger Eric
2020-03-17 10:30     ` Auger Eric
2020-03-17 10:30     ` Auger Eric
2020-03-19 10:57     ` Marc Zyngier
2020-03-19 10:57       ` Marc Zyngier
2020-03-19 10:57       ` Marc Zyngier
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 16/23] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  8:12   ` Zenghui Yu
2020-03-12  8:12     ` Zenghui Yu
2020-03-12  8:12     ` Zenghui Yu
2020-03-17  2:49   ` Zenghui Yu
2020-03-17  2:49     ` Zenghui Yu
2020-03-17  2:49     ` Zenghui Yu
2020-03-19 10:55     ` Marc Zyngier
2020-03-19 10:55       ` Marc Zyngier
2020-03-19 10:55       ` Marc Zyngier
2020-03-20  2:31       ` Zenghui Yu
2020-03-20  2:31         ` Zenghui Yu
2020-03-20  2:31         ` Zenghui Yu
2020-03-29 20:26   ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 17/23] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-12  8:15   ` Zenghui Yu
2020-03-12  8:15     ` Zenghui Yu
2020-03-12  8:15     ` Zenghui Yu
2020-03-17 11:04   ` Auger Eric
2020-03-17 11:04     ` Auger Eric
2020-03-17 11:04     ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-18  3:28   ` Zenghui Yu
2020-03-18  3:28     ` Zenghui Yu
2020-03-18  3:28     ` Zenghui Yu
2020-03-20  8:11   ` Auger Eric
2020-03-20  8:11     ` Auger Eric
2020-03-20  8:11     ` Auger Eric
2020-03-20 10:05     ` Marc Zyngier
2020-03-20 10:05       ` Marc Zyngier
2020-03-20 10:05       ` Marc Zyngier
2020-03-20 10:56       ` Auger Eric
2020-03-20 10:56         ` Auger Eric
2020-03-20 10:56         ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 19/23] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-19 16:16   ` Auger Eric
2020-03-19 16:16     ` Auger Eric
2020-03-19 16:16     ` Auger Eric
2020-03-19 19:52     ` Marc Zyngier
2020-03-19 19:52       ` Marc Zyngier
2020-03-19 19:52       ` Marc Zyngier
2020-03-19 20:13       ` Auger Eric
2020-03-19 20:13         ` Auger Eric
2020-03-19 20:13         ` Auger Eric
2020-03-20  9:17         ` Marc Zyngier
2020-03-20  9:17           ` Marc Zyngier
2020-03-20  9:17           ` Marc Zyngier
2020-03-20  4:22   ` Zenghui Yu
2020-03-20  4:22     ` Zenghui Yu
2020-03-20  4:22     ` Zenghui Yu
2020-03-04 20:33 ` Marc Zyngier [this message]
2020-03-04 20:33   ` [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-18  6:34   ` Zenghui Yu
2020-03-18  6:34     ` Zenghui Yu
2020-03-18  6:34     ` Zenghui Yu
2020-03-19 12:10     ` Marc Zyngier
2020-03-19 12:10       ` Marc Zyngier
2020-03-19 12:10       ` Marc Zyngier
2020-03-19 20:38       ` Auger Eric
2020-03-19 20:38         ` Auger Eric
2020-03-19 20:38         ` Auger Eric
2020-03-20  3:08         ` Zenghui Yu
2020-03-20  3:08           ` Zenghui Yu
2020-03-20  3:08           ` Zenghui Yu
2020-03-20  7:59           ` Auger Eric
2020-03-20  7:59             ` Auger Eric
2020-03-20  7:59             ` Auger Eric
2020-03-20  9:46             ` Marc Zyngier
2020-03-20  9:46               ` Marc Zyngier
2020-03-20  9:46               ` Marc Zyngier
2020-03-20 11:09               ` Auger Eric
2020-03-20 11:09                 ` Auger Eric
2020-03-20 11:09                 ` Auger Eric
2020-03-20 11:20                 ` Marc Zyngier
2020-03-20 11:20                   ` Marc Zyngier
2020-03-20 11:20                   ` Marc Zyngier
2020-03-20  3:53       ` Zenghui Yu
2020-03-20  3:53         ` Zenghui Yu
2020-03-20  3:53         ` Zenghui Yu
2020-03-20  9:01         ` Marc Zyngier
2020-03-20  9:01           ` Marc Zyngier
2020-03-20  9:01           ` Marc Zyngier
2020-03-23  8:11           ` Zenghui Yu
2020-03-23  8:11             ` Zenghui Yu
2020-03-23  8:11             ` Zenghui Yu
2020-03-23  8:25             ` Marc Zyngier
2020-03-23  8:25               ` Marc Zyngier
2020-03-23  8:25               ` Marc Zyngier
2020-03-23 12:40               ` Zenghui Yu
2020-03-23 12:40                 ` Zenghui Yu
2020-03-23 12:40                 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 21/23] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-18  3:17   ` Zenghui Yu
2020-03-18  3:17     ` Zenghui Yu
2020-03-18  3:17     ` Zenghui Yu
2020-03-19 12:18     ` Marc Zyngier
2020-03-19 12:18       ` Marc Zyngier
2020-03-19 12:18       ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 22/23] KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-20  4:23   ` Zenghui Yu
2020-03-20  4:23     ` Zenghui Yu
2020-03-20  4:23     ` Zenghui Yu
2020-03-20  8:12   ` Auger Eric
2020-03-20  8:12     ` Auger Eric
2020-03-20  8:12     ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 23/23] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-04 20:33   ` Marc Zyngier
2020-03-18  3:19   ` Zenghui Yu
2020-03-18  3:19     ` Zenghui Yu
2020-03-18  3:19     ` Zenghui Yu
2020-03-19 15:05   ` Auger Eric
2020-03-19 15:05     ` Auger Eric
2020-03-19 15:05     ` Auger Eric
2020-03-19 15:21     ` Marc Zyngier
2020-03-19 15:21       ` Marc Zyngier
2020-03-19 15:21       ` Marc Zyngier
2020-03-19 15:43       ` Auger Eric
2020-03-19 15:43         ` Auger Eric
2020-03-19 15:43         ` Auger Eric
2020-03-19 16:16         ` Marc Zyngier
2020-03-19 16:16           ` Marc Zyngier
2020-03-19 16:16           ` Marc Zyngier
2020-03-19 16:17           ` Auger Eric
2020-03-19 16:17             ` Auger Eric
2020-03-19 16:17             ` Auger Eric
2020-03-20  4:38       ` Zenghui Yu
2020-03-20  4:38         ` Zenghui Yu
2020-03-20  4:38         ` Zenghui Yu
2020-03-20  9:09         ` Marc Zyngier
2020-03-20  9:09           ` Marc Zyngier
2020-03-20  9:09           ` Marc Zyngier
2020-03-20 11:35           ` Zenghui Yu
2020-03-20 11:35             ` Zenghui Yu
2020-03-20 11:35             ` Zenghui Yu
2020-03-20 11:46             ` Marc Zyngier
2020-03-20 11:46               ` Marc Zyngier
2020-03-20 11:46               ` Marc Zyngier
2020-03-20 12:09               ` Zenghui Yu
2020-03-20 12:09                 ` Zenghui Yu
2020-03-20 12:09                 ` Zenghui Yu
2020-03-05  3:39 ` [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Zenghui Yu
2020-03-05  3:39   ` Zenghui Yu
2020-03-05  3:39   ` Zenghui Yu
2020-03-09  8:17 ` Zenghui Yu
2020-03-09  8:17   ` Zenghui Yu
2020-03-09  8:17   ` Zenghui Yu
2020-03-09  8:46   ` Marc Zyngier
2020-03-09  8:46     ` Marc Zyngier
2020-03-09  8:46     ` Marc Zyngier

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