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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Paul Durrant" <paul@xen.org>, "Andrew Jeffery" <andrew@aj.id.au>,
	"Helge Deller" <deller@gmx.de>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-trivial@nongnu.org, qemu-arm@nongnu.org,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Anthony Perard" <anthony.perard@citrix.com>,
	xen-devel@lists.xenproject.org, qemu-ppc@nongnu.org,
	"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH 0/8] hw: Fix some incomplete memory region size
Date: Sun, 31 May 2020 19:38:06 +0200	[thread overview]
Message-ID: <20200531173814.8734-1-f4bug@amsat.org> (raw)

memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value.
This is not a problem for the 32-bit maximum, 4 GiB, but
in some places we incorrectly use UINT32_MAX instead of
4 GiB, and end up missing 1 byte in the memory region.

This series fixes the cases I encountered.
Also included few patches while reviewing, I replaced some
magic values by the IEC binary prefix equivalent.

Regards,

Phil.

Philippe Mathieu-Daudé (8):
  hw/arm/aspeed: Correct DRAM container region size
  hw/pci-host/prep: Correct RAVEN bus bridge memory region size
  hw/pci/pci_bridge: Correct pci_bridge_io memory region size
  hw/pci/pci_bridge: Use the IEC binary prefix definitions
  hw/pci-host: Use the IEC binary prefix definitions
  hw/hppa/dino: Use the IEC binary prefix definitions
  hw/i386/xen/xen-hvm: Use the IEC binary prefix definitions
  target/i386/cpu: Use the IEC binary prefix definitions

 hw/arm/aspeed.c         | 2 +-
 hw/hppa/dino.c          | 4 ++--
 hw/i386/xen/xen-hvm.c   | 3 ++-
 hw/pci-host/i440fx.c    | 3 ++-
 hw/pci-host/prep.c      | 2 +-
 hw/pci-host/q35.c       | 2 +-
 hw/pci-host/versatile.c | 5 +++--
 hw/pci/pci_bridge.c     | 7 ++++---
 target/i386/cpu.c       | 2 +-
 9 files changed, 17 insertions(+), 13 deletions(-)

-- 
2.21.3



WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Paul Durrant" <paul@xen.org>, "Andrew Jeffery" <andrew@aj.id.au>,
	"Helge Deller" <deller@gmx.de>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-trivial@nongnu.org, qemu-arm@nongnu.org,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Anthony Perard" <anthony.perard@citrix.com>,
	xen-devel@lists.xenproject.org, qemu-ppc@nongnu.org,
	"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH 0/8] hw: Fix some incomplete memory region size
Date: Sun, 31 May 2020 19:38:06 +0200	[thread overview]
Message-ID: <20200531173814.8734-1-f4bug@amsat.org> (raw)

memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value.
This is not a problem for the 32-bit maximum, 4 GiB, but
in some places we incorrectly use UINT32_MAX instead of
4 GiB, and end up missing 1 byte in the memory region.

This series fixes the cases I encountered.
Also included few patches while reviewing, I replaced some
magic values by the IEC binary prefix equivalent.

Regards,

Phil.

Philippe Mathieu-Daudé (8):
  hw/arm/aspeed: Correct DRAM container region size
  hw/pci-host/prep: Correct RAVEN bus bridge memory region size
  hw/pci/pci_bridge: Correct pci_bridge_io memory region size
  hw/pci/pci_bridge: Use the IEC binary prefix definitions
  hw/pci-host: Use the IEC binary prefix definitions
  hw/hppa/dino: Use the IEC binary prefix definitions
  hw/i386/xen/xen-hvm: Use the IEC binary prefix definitions
  target/i386/cpu: Use the IEC binary prefix definitions

 hw/arm/aspeed.c         | 2 +-
 hw/hppa/dino.c          | 4 ++--
 hw/i386/xen/xen-hvm.c   | 3 ++-
 hw/pci-host/i440fx.c    | 3 ++-
 hw/pci-host/prep.c      | 2 +-
 hw/pci-host/q35.c       | 2 +-
 hw/pci-host/versatile.c | 5 +++--
 hw/pci/pci_bridge.c     | 7 ++++---
 target/i386/cpu.c       | 2 +-
 9 files changed, 17 insertions(+), 13 deletions(-)

-- 
2.21.3



             reply	other threads:[~2020-05-31 17:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-31 17:38 Philippe Mathieu-Daudé [this message]
2020-05-31 17:38 ` [PATCH 0/8] hw: Fix some incomplete memory region size Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 1/8] hw/arm/aspeed: Correct DRAM container " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 2/8] hw/pci-host/prep: Correct RAVEN bus bridge memory " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 3/8] hw/pci/pci_bridge: Correct pci_bridge_io " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 4/8] hw/pci/pci_bridge: Use the IEC binary prefix definitions Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 5/8] hw/pci-host: " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 6/8] hw/hppa/dino: " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 7/8] hw/i386/xen/xen-hvm: " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-06-01  7:26   ` Paul Durrant
2020-06-01  7:26     ` Paul Durrant
2020-06-01  8:33     ` Philippe Mathieu-Daudé
2020-06-01  8:33       ` Philippe Mathieu-Daudé
2020-06-01 11:15       ` Philippe Mathieu-Daudé
2020-05-31 17:38 ` [PATCH 8/8] target/i386/cpu: " Philippe Mathieu-Daudé
2020-05-31 17:38   ` Philippe Mathieu-Daudé
2020-05-31 19:48 ` [PATCH 0/8] hw: Fix some incomplete memory region size Peter Maydell
2020-05-31 19:48   ` Peter Maydell

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