From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Richard Henderson <richard.henderson@linaro.org>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PULL 51/63] target/riscv: vector mask-register logical instructions
Date: Fri, 26 Jun 2020 14:43:58 -0700 [thread overview]
Message-ID: <20200626214410.3613258-52-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200626214410.3613258-1-alistair.francis@wdc.com>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200623215920.2594-50-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 9 ++++++
target/riscv/insn32.decode | 8 +++++
target/riscv/insn_trans/trans_rvv.inc.c | 35 ++++++++++++++++++++++
target/riscv/vector_helper.c | 40 +++++++++++++++++++++++++
4 files changed, 92 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 217f09a55c..292279f0c5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1092,3 +1092,12 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2668d483a7..c71cbef182 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -547,6 +547,14 @@ vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
+vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
+vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
+vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
+vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
+vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
+vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
+vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
+vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index b78829be36..e2954aa99a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2354,3 +2354,38 @@ GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+
+/*
+ *** Vector Mask Operations
+ */
+
+/* Vector Mask-Register Logical Instructions */
+#define GEN_MM_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ if (vext_check_isa_ill(s)) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_MM_TRANS(vmand_mm)
+GEN_MM_TRANS(vmnand_mm)
+GEN_MM_TRANS(vmandnot_mm)
+GEN_MM_TRANS(vmxor_mm)
+GEN_MM_TRANS(vmor_mm)
+GEN_MM_TRANS(vmnor_mm)
+GEN_MM_TRANS(vmornot_mm)
+GEN_MM_TRANS(vmxnor_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 61d169398a..028abd1871 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4502,3 +4502,43 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
*((uint64_t *)vd) = s1;
clearq(vd, 1, sizeof(uint64_t), tot);
}
+
+/*
+ *** Vector Mask Operations
+ */
+/* Vector Mask-Register Logical Instructions */
+#define GEN_VEXT_MASK_VV(NAME, OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ int a, b; \
+ \
+ for (i = 0; i < vl; i++) { \
+ a = vext_elem_mask(vs1, mlen, i); \
+ b = vext_elem_mask(vs2, mlen, i); \
+ vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ } \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+#define DO_NAND(N, M) (!(N & M))
+#define DO_ANDNOT(N, M) (N & !M)
+#define DO_NOR(N, M) (!(N | M))
+#define DO_ORNOT(N, M) (N | !M)
+#define DO_XNOR(N, M) (!(N ^ M))
+
+GEN_VEXT_MASK_VV(vmand_mm, DO_AND)
+GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND)
+GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT)
+GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR)
+GEN_VEXT_MASK_VV(vmor_mm, DO_OR)
+GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
+GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
+GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
--
2.27.0
next prev parent reply other threads:[~2020-06-26 22:23 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 21:43 [PULL 00/63] riscv-to-apply queue Alistair Francis
2020-06-26 21:43 ` [PULL 01/63] riscv: plic: Honour source priorities Alistair Francis
2020-06-26 21:43 ` [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls Alistair Francis
2020-06-26 22:01 ` Jessica Clarke
2020-06-26 21:58 ` Alistair Francis
2020-06-26 21:43 ` [PULL 03/63] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-06-26 21:43 ` [PULL 04/63] target/riscv: implementation-defined constant parameters Alistair Francis
2020-06-26 21:43 ` [PULL 05/63] target/riscv: support vector extension csr Alistair Francis
2020-06-26 21:43 ` [PULL 06/63] target/riscv: add vector configure instruction Alistair Francis
2020-06-26 21:43 ` [PULL 07/63] target/riscv: add an internals.h header Alistair Francis
2020-06-26 21:43 ` [PULL 08/63] target/riscv: add vector stride load and store instructions Alistair Francis
2020-06-26 21:43 ` [PULL 09/63] target/riscv: add vector index " Alistair Francis
2020-06-26 21:43 ` [PULL 10/63] target/riscv: add fault-only-first unit stride load Alistair Francis
2020-06-26 21:43 ` [PULL 11/63] target/riscv: add vector amo operations Alistair Francis
2020-06-26 21:43 ` [PULL 12/63] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 13/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-06-26 21:43 ` [PULL 15/63] target/riscv: vector bitwise logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 16/63] target/riscv: vector single-width bit shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 17/63] target/riscv: vector narrowing integer right " Alistair Francis
2020-06-26 21:43 ` [PULL 18/63] target/riscv: vector integer comparison instructions Alistair Francis
2020-06-26 21:43 ` [PULL 19/63] target/riscv: vector integer min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 20/63] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 21/63] target/riscv: vector integer divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 22/63] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 23/63] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 24/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 25/63] target/riscv: vector integer merge and move instructions Alistair Francis
2020-06-26 21:43 ` [PULL 26/63] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 27/63] target/riscv: vector single-width averaging " Alistair Francis
2020-06-26 21:43 ` [PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-06-26 21:43 ` [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-06-26 21:43 ` [PULL 30/63] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-06-26 21:43 ` [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-06-26 21:43 ` [PULL 33/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 34/63] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 35/63] target/riscv: vector widening floating-point multiply Alistair Francis
2020-06-26 21:43 ` [PULL 36/63] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 37/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 38/63] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-06-26 21:43 ` [PULL 39/63] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 40/63] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-06-26 21:43 ` [PULL 41/63] target/riscv: vector floating-point compare instructions Alistair Francis
2020-06-26 21:43 ` [PULL 42/63] target/riscv: vector floating-point classify instructions Alistair Francis
2020-06-26 21:43 ` [PULL 43/63] target/riscv: vector floating-point merge instructions Alistair Francis
2020-06-26 21:43 ` [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-06-26 21:43 ` [PULL 45/63] target/riscv: widening " Alistair Francis
2020-06-26 21:43 ` [PULL 46/63] target/riscv: narrowing " Alistair Francis
2020-06-26 21:43 ` [PULL 47/63] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-06-26 21:43 ` [PULL 48/63] target/riscv: vector wideing " Alistair Francis
2020-06-26 21:43 ` [PULL 49/63] target/riscv: vector single-width floating-point " Alistair Francis
2020-06-26 21:43 ` [PULL 50/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` Alistair Francis [this message]
2020-06-26 21:43 ` [PULL 52/63] target/riscv: vector mask population count vmpopc Alistair Francis
2020-06-26 21:44 ` [PULL 53/63] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-06-26 21:44 ` [PULL 54/63] target/riscv: set-X-first " Alistair Francis
2020-06-26 21:44 ` [PULL 55/63] target/riscv: vector iota instruction Alistair Francis
2020-06-26 21:44 ` [PULL 56/63] target/riscv: vector element index instruction Alistair Francis
2020-06-26 21:44 ` [PULL 57/63] target/riscv: integer extract instruction Alistair Francis
2020-06-26 21:44 ` [PULL 58/63] target/riscv: integer scalar move instruction Alistair Francis
2020-06-26 21:44 ` [PULL 59/63] target/riscv: floating-point scalar move instructions Alistair Francis
2020-06-26 21:44 ` [PULL 60/63] target/riscv: vector slide instructions Alistair Francis
2020-06-26 21:44 ` [PULL 61/63] target/riscv: vector register gather instruction Alistair Francis
2020-06-26 21:44 ` [PULL 62/63] target/riscv: vector compress instruction Alistair Francis
2020-06-26 21:44 ` [PULL 63/63] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-06-26 22:38 ` [PULL 00/63] riscv-to-apply queue no-reply
2020-06-26 22:44 ` no-reply
2020-06-28 14:30 ` Peter Maydell
2020-06-28 22:51 ` Alistair Francis
2020-06-29 0:52 ` LIU Zhiwei
2020-06-30 6:56 ` LIU Zhiwei
2020-06-30 8:11 ` Thomas Huth
2020-06-30 8:44 ` LIU Zhiwei
2020-08-03 17:53 ` Thomas Huth
2020-08-03 18:00 ` Philippe Mathieu-Daudé
2020-08-03 18:11 ` Thomas Huth
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