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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: saiprakash.ranjan@codeaurora.org, suzuki.poulose@arm.com,
	vulab@iscas.ac.cn, tingwei@codeaurora.org,
	andriy.shevchenko@linux.intel.com,
	linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: [PATCH 13/17] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb()
Date: Thu, 16 Jul 2020 11:57:42 -0600	[thread overview]
Message-ID: <20200716175746.3338735-14-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200716175746.3338735-1-mathieu.poirier@linaro.org>

From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

Reading TMC mode register without proper coresight power
management can lead to exceptions like the one in the call
trace below in tmc_read_unprepare_etb() when the trace data
is read after the sink is disabled. So fix this by having
a check for coresight sysfs mode before reading TMC mode
management register in tmc_read_unprepare_etb() similar to
tmc_read_prepare_etb().

  SError Interrupt on CPU6, code 0xbe000411 -- SError
  pstate: 80400089 (Nzcv daIf +PAN -UAO)
  pc : tmc_read_unprepare_etb+0x74/0x108
  lr : tmc_read_unprepare_etb+0x54/0x108
  sp : ffffff80d9507c30
  x29: ffffff80d9507c30 x28: ffffff80b3569a0c
  x27: 0000000000000000 x26: 00000000000a0001
  x25: ffffff80cbae9550 x24: 0000000000000010
  x23: ffffffd07296b0f0 x22: ffffffd0109ee028
  x21: 0000000000000000 x20: ffffff80d19e70e0
  x19: ffffff80d19e7080 x18: 0000000000000000
  x17: 0000000000000000 x16: 0000000000000000
  x15: 0000000000000000 x14: 0000000000000000
  x13: 0000000000000000 x12: 0000000000000000
  x11: 0000000000000000 x10: dfffffd000000001
  x9 : 0000000000000000 x8 : 0000000000000002
  x7 : ffffffd071d0fe78 x6 : 0000000000000000
  x5 : 0000000000000080 x4 : 0000000000000001
  x3 : ffffffd071d0fe98 x2 : 0000000000000000
  x1 : 0000000000000004 x0 : 0000000000000001
  Kernel panic - not syncing: Asynchronous SError Interrupt

Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare functions generic")
Reported-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Tested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 36cce2bfb744..6375504ba8b0 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -639,15 +639,14 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
 
 	spin_lock_irqsave(&drvdata->spinlock, flags);
 
-	/* There is no point in reading a TMC in HW FIFO mode */
-	mode = readl_relaxed(drvdata->base + TMC_MODE);
-	if (mode != TMC_MODE_CIRCULAR_BUFFER) {
-		spin_unlock_irqrestore(&drvdata->spinlock, flags);
-		return -EINVAL;
-	}
-
 	/* Re-enable the TMC if need be */
 	if (drvdata->mode == CS_MODE_SYSFS) {
+		/* There is no point in reading a TMC in HW FIFO mode */
+		mode = readl_relaxed(drvdata->base + TMC_MODE);
+		if (mode != TMC_MODE_CIRCULAR_BUFFER) {
+			spin_unlock_irqrestore(&drvdata->spinlock, flags);
+			return -EINVAL;
+		}
 		/*
 		 * The trace run will continue with the same allocated trace
 		 * buffer. As such zero-out the buffer so that we don't end
-- 
2.25.1


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  parent reply	other threads:[~2020-07-16 18:01 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
2020-07-16 17:57 ` [PATCH 01/17] coresight: replicator: Use CS_AMBA_ID macro for id table Mathieu Poirier
2020-07-16 17:57 ` [PATCH 02/17] coresight: catu: " Mathieu Poirier
2020-07-16 17:57 ` [PATCH 03/17] coresight: etm4x: Add support to skip trace unit power up Mathieu Poirier
2020-07-16 17:57 ` [PATCH 04/17] dt-bindings: arm: coresight: " Mathieu Poirier
2020-07-16 17:57 ` [PATCH 05/17] coresight: replicator: Reset replicator if context is lost Mathieu Poirier
2020-07-16 17:57 ` [PATCH 06/17] dt-bindings: arm: coresight: Add optional property to replicators Mathieu Poirier
2020-07-16 17:57 ` [PATCH 07/17] coresight: Use devm_kcalloc() in coresight_alloc_conns() Mathieu Poirier
2020-07-16 17:57 ` [PATCH 08/17] coresight: Drop double check for ACPI companion device Mathieu Poirier
2020-07-16 17:57 ` [PATCH 09/17] coresight: etmv4: Fix resource selector constant Mathieu Poirier
2020-07-16 17:57 ` [PATCH 10/17] coresight: etmv4: Counter values not saved on disable Mathieu Poirier
2020-07-16 17:57 ` [PATCH 11/17] coresight: Fix comment in main header file Mathieu Poirier
2020-07-16 17:57 ` [PATCH 12/17] coresight: tmc: Add shutdown callback for TMC ETR Mathieu Poirier
2020-07-16 17:57 ` Mathieu Poirier [this message]
2020-07-16 17:57 ` [PATCH 14/17] coresight: Add default sink selection to CoreSight base Mathieu Poirier
2020-07-16 17:57 ` [PATCH 15/17] coresight: tmc: Update sink types for default selection Mathieu Poirier
2020-07-16 17:57 ` [PATCH 16/17] coresight: etm: perf: Add default sink selection to etm perf Mathieu Poirier
2020-07-16 17:57 ` [PATCH 17/17] coresight: etm4x: Fix save/restore during cpu idle Mathieu Poirier

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