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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org
Subject: [PATCH v5 12/36] PM / devfreq: tegra20: Use MC timings for building OPP table
Date: Fri, 14 Aug 2020 03:05:57 +0300	[thread overview]
Message-ID: <20200814000621.8415-13-digetx@gmail.com> (raw)
In-Reply-To: <20200814000621.8415-1-digetx@gmail.com>

The clk_round_rate() won't be usable for building OPP table once
interconnect support will be added to the EMC driver because that CLK API
function limits the rounded rate based on the clk rate that is imposed by
active clk-users, and thus, the rounding won't work as expected if
interconnect will set the minimum EMC clock rate before devfreq driver is
loaded. The struct tegra_mc contains memory timings which could be used by
the devfreq driver for building up OPP table instead of rounding clock
rate, this patch implements this idea.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/devfreq/tegra20-devfreq.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index 6469dc69c5e0..a985f24098f5 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -123,8 +123,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 {
 	struct tegra_devfreq *tegra;
 	struct tegra_mc *mc;
-	unsigned long max_rate;
-	unsigned long rate;
+	unsigned int i;
 	int err;
 
 	mc = tegra_get_memory_controller();
@@ -135,6 +134,11 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 		return err;
 	}
 
+	if (!mc->num_timings) {
+		dev_info(&pdev->dev, "memory controller has no timings\n");
+		return -ENODEV;
+	}
+
 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 	if (!tegra)
 		return -ENOMEM;
@@ -151,12 +155,8 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 
 	tegra->regs = mc->regs;
 
-	max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
-
-	for (rate = 0; rate <= max_rate; rate++) {
-		rate = clk_round_rate(tegra->emc_clock, rate);
-
-		err = dev_pm_opp_add(&pdev->dev, rate, 0);
+	for (i = 0; i < mc->num_timings; i++) {
+		err = dev_pm_opp_add(&pdev->dev, mc->timings[i].rate, 0);
 		if (err) {
 			dev_err(&pdev->dev, "failed to add opp: %d\n", err);
 			goto remove_opps;
-- 
2.27.0


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-pm@vger.kernel.org
Subject: [PATCH v5 12/36] PM / devfreq: tegra20: Use MC timings for building OPP table
Date: Fri, 14 Aug 2020 03:05:57 +0300	[thread overview]
Message-ID: <20200814000621.8415-13-digetx@gmail.com> (raw)
In-Reply-To: <20200814000621.8415-1-digetx@gmail.com>

The clk_round_rate() won't be usable for building OPP table once
interconnect support will be added to the EMC driver because that CLK API
function limits the rounded rate based on the clk rate that is imposed by
active clk-users, and thus, the rounding won't work as expected if
interconnect will set the minimum EMC clock rate before devfreq driver is
loaded. The struct tegra_mc contains memory timings which could be used by
the devfreq driver for building up OPP table instead of rounding clock
rate, this patch implements this idea.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/devfreq/tegra20-devfreq.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index 6469dc69c5e0..a985f24098f5 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -123,8 +123,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 {
 	struct tegra_devfreq *tegra;
 	struct tegra_mc *mc;
-	unsigned long max_rate;
-	unsigned long rate;
+	unsigned int i;
 	int err;
 
 	mc = tegra_get_memory_controller();
@@ -135,6 +134,11 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 		return err;
 	}
 
+	if (!mc->num_timings) {
+		dev_info(&pdev->dev, "memory controller has no timings\n");
+		return -ENODEV;
+	}
+
 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 	if (!tegra)
 		return -ENOMEM;
@@ -151,12 +155,8 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 
 	tegra->regs = mc->regs;
 
-	max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
-
-	for (rate = 0; rate <= max_rate; rate++) {
-		rate = clk_round_rate(tegra->emc_clock, rate);
-
-		err = dev_pm_opp_add(&pdev->dev, rate, 0);
+	for (i = 0; i < mc->num_timings; i++) {
+		err = dev_pm_opp_add(&pdev->dev, mc->timings[i].rate, 0);
 		if (err) {
 			dev_err(&pdev->dev, "failed to add opp: %d\n", err);
 			goto remove_opps;
-- 
2.27.0

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  parent reply	other threads:[~2020-08-14  0:09 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-14  0:05 [PATCH v5 00/36] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-08-14  0:05 ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 01/36] clk: Export clk_hw_reparent() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 02/36] clk: tegra: Remove Memory Controller lock Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 03/36] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 04/36] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 05/36] memory: tegra30-emc: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 06/36] memory: tegra124-emc: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 07/36] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 08/36] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 09/36] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 10/36] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 11/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` Dmitry Osipenko [this message]
2020-08-14  0:05   ` [PATCH v5 12/36] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko
2020-08-14  1:00   ` Chanwoo Choi
2020-08-14  1:00     ` Chanwoo Choi
2020-08-14  0:05 ` [PATCH v5 13/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  2:02   ` Chanwoo Choi
2020-08-14  2:02     ` Chanwoo Choi
2020-08-14 16:47     ` Dmitry Osipenko
2020-08-14 16:47       ` Dmitry Osipenko
2020-08-28  1:47       ` Chanwoo Choi
2020-08-28  1:47         ` Chanwoo Choi
2020-08-28  8:30         ` Dmitry Osipenko
2020-08-28  8:30           ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 14/36] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 15/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 16/36] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 17/36] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 18/36] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 19/36] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 20/36] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 21/36] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 22/36] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-25  2:09   ` Rob Herring
2020-08-25  2:09     ` Rob Herring
2020-08-14  0:06 ` [PATCH v5 23/36] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 24/36] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 25/36] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 26/36] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 27/36] memory: tegra-mc: Register as interconnect provider Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-09-09  8:31   ` Georgi Djakov
2020-09-09  8:31     ` Georgi Djakov
2020-09-09 21:15     ` Dmitry Osipenko
2020-09-09 21:15       ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 28/36] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 29/36] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-09-09  8:32   ` Georgi Djakov
2020-09-09  8:32     ` Georgi Djakov
2020-08-14  0:06 ` [PATCH v5 31/36] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 32/36] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 33/36] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-09-09  8:32   ` Georgi Djakov
2020-09-09  8:32     ` Georgi Djakov
2020-08-14  0:06 ` [PATCH v5 34/36] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 35/36] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 36/36] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko

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