From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Fredrik Noring" <noring@nocrew.org>,
"Craig Janeczek" <jancraig@amazon.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Huacai Chen" <chenhc@lemote.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 15/26] target/mips: Extract NEC Vr54xx translation routines
Date: Fri, 20 Nov 2020 22:08:33 +0100 [thread overview]
Message-ID: <20201120210844.2625602-16-f4bug@amsat.org> (raw)
In-Reply-To: <20201120210844.2625602-1-f4bug@amsat.org>
Extract the NEC Vr54xx translation routines to
'vendor-vr54xx_translate.c.inc'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 86 +--------------------
target/mips/vendor-vr54xx_translate.c.inc | 93 +++++++++++++++++++++++
2 files changed, 95 insertions(+), 84 deletions(-)
create mode 100644 target/mips/vendor-vr54xx_translate.c.inc
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 095ee31ab5f..b01a16e9da4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -295,26 +295,6 @@ enum {
OPC_DLSA = 0x15 | OPC_SPECIAL,
};
-/* Multiplication variants of the vr54xx. */
-#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
-
-enum {
- OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
- OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
- OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
- OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
- OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
- OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
- OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
- OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
- OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
- OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
- OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
- OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
- OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
- OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
-};
-
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
@@ -4546,70 +4526,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
-static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
-
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case OPC_VR54XX_MULS:
- gen_helper_muls(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSU:
- gen_helper_mulsu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACC:
- gen_helper_macc(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCU:
- gen_helper_maccu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSAC:
- gen_helper_msac(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACU:
- gen_helper_msacu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHI:
- gen_helper_mulhi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHIU:
- gen_helper_mulhiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHI:
- gen_helper_mulshi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHIU:
- gen_helper_mulshiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCHI:
- gen_helper_macchi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCHIU:
- gen_helper_macchiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACHI:
- gen_helper_msachi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACHIU:
- gen_helper_msachiu(t0, cpu_env, t0, t1);
- break;
- default:
- MIPS_INVAL("mul vr54xx");
- generate_exception_end(ctx, EXCP_RI);
- goto out;
- }
- gen_store_gpr(t0, rd);
-
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
static void gen_cl(DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
@@ -13022,6 +12938,8 @@ out:
#include "mod-mips-dsp_translate.c.inc"
+#include "vendor-vr54xx_translate.c.inc"
+
static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
diff --git a/target/mips/vendor-vr54xx_translate.c.inc b/target/mips/vendor-vr54xx_translate.c.inc
new file mode 100644
index 00000000000..8c952a98ebc
--- /dev/null
+++ b/target/mips/vendor-vr54xx_translate.c.inc
@@ -0,0 +1,93 @@
+/*
+ * MIPS NEC Vr54xx translation routines.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+/* Multiplication variants of the vr54xx. */
+#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
+
+enum {
+ OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
+ OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
+ OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
+ OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
+ OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
+ OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
+ OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
+ OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
+ OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
+ OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
+ OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
+ OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
+};
+
+static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ switch (opc) {
+ case OPC_VR54XX_MULS:
+ gen_helper_muls(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MULSU:
+ gen_helper_mulsu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MACC:
+ gen_helper_macc(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MACCU:
+ gen_helper_maccu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MSAC:
+ gen_helper_msac(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MSACU:
+ gen_helper_msacu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MULHI:
+ gen_helper_mulhi(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MULHIU:
+ gen_helper_mulhiu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MULSHI:
+ gen_helper_mulshi(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MULSHIU:
+ gen_helper_mulshiu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MACCHI:
+ gen_helper_macchi(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MACCHIU:
+ gen_helper_macchiu(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MSACHI:
+ gen_helper_msachi(t0, cpu_env, t0, t1);
+ break;
+ case OPC_VR54XX_MSACHIU:
+ gen_helper_msachiu(t0, cpu_env, t0, t1);
+ break;
+ default:
+ MIPS_INVAL("mul vr54xx");
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+ gen_store_gpr(t0, rd);
+
+ out:
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
--
2.26.2
next prev parent reply other threads:[~2020-11-20 21:21 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-20 21:08 [PATCH 00/26] target/mips: Explode 60% of the 32K-lines translate.c Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 01/26] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2020-11-21 19:39 ` Richard Henderson
2020-11-22 17:01 ` Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 02/26] target/mips: Extract MSA helpers to mod-mips-msa_helper.c Philippe Mathieu-Daudé
2020-11-21 19:44 ` Richard Henderson
2020-11-22 17:16 ` Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 03/26] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2020-11-21 19:45 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 04/26] target/mips: Extract MSA translation routines Philippe Mathieu-Daudé
2020-11-21 19:47 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 05/26] target/mips: Rename dsp_helper.c as mod-mips-dsp_helper.c Philippe Mathieu-Daudé
2020-11-21 19:48 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 06/26] target/mips: Extract DSP helper definitions Philippe Mathieu-Daudé
2020-11-21 19:48 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 07/26] target/mips: Extract DSP translation routines Philippe Mathieu-Daudé
2020-11-21 19:51 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 08/26] target/mips: Extract Multi-Threading helper definitions Philippe Mathieu-Daudé
2020-11-21 19:53 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 09/26] target/mips: Extract Code Compaction ASE translation routines Philippe Mathieu-Daudé
2020-11-21 19:56 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 10/26] target/mips: Extract the microMIPS ISA helper definitions Philippe Mathieu-Daudé
2020-11-21 20:00 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 11/26] target/mips: Extract the microMIPS ISA translation routines Philippe Mathieu-Daudé
2020-11-21 20:02 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 12/26] target/mips: Extract nanoMIPS " Philippe Mathieu-Daudé
2020-11-21 20:04 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 13/26] target/mips: Extract NEC Vr54xx helpers to vendor-vr54xx_helper.c Philippe Mathieu-Daudé
2020-11-21 20:05 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 14/26] target/mips: Extract NEC Vr54xx helper definitions Philippe Mathieu-Daudé
2020-11-21 20:06 ` Richard Henderson
2020-11-20 21:08 ` Philippe Mathieu-Daudé [this message]
2020-11-21 20:06 ` [PATCH 15/26] target/mips: Extract NEC Vr54xx translation routines Richard Henderson
2020-11-20 21:08 ` [PATCH 16/26] target/mips: Rename lmmi_helper.c as loong-simd_helper.c Philippe Mathieu-Daudé
2020-11-21 20:07 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 17/26] target/mips: Extract Loongson SIMD helper definitions Philippe Mathieu-Daudé
2020-11-21 20:07 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 18/26] target/mips: Extract Loongson SIMD translation routines Philippe Mathieu-Daudé
2020-11-21 14:30 ` Philippe Mathieu-Daudé
2020-11-21 20:09 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 19/26] target/mips: Extract Loongson EXTensions " Philippe Mathieu-Daudé
2020-11-21 20:10 ` Richard Henderson
2020-11-22 17:49 ` Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 20/26] target/mips: Extract XBurst Media eXtension Unit " Philippe Mathieu-Daudé
2020-11-21 20:13 ` Richard Henderson
2020-11-22 17:58 ` Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 21/26] target/mips: Make pipeline 1 multiply opcodes generic Philippe Mathieu-Daudé
2020-11-21 20:14 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 22/26] target/mips: Extract Toshiba TXx9 translation routines Philippe Mathieu-Daudé
2020-11-21 20:15 ` Richard Henderson
2020-11-20 21:08 ` [PATCH 23/26] target/mips: Extract Toshiba TX79 multimedia " Philippe Mathieu-Daudé
2020-11-21 20:17 ` Richard Henderson
2020-11-22 19:47 ` Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 24/26] MAINTAINERS: Add entry for MIPS Loongson TCG Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 25/26] MAINTAINERS: Add entry for MIPS Ingenic Xburst TCG Philippe Mathieu-Daudé
2020-11-20 21:08 ` [PATCH 26/26] MAINTAINERS: Add entry for MIPS Toshiba TCG Philippe Mathieu-Daudé
2020-12-12 16:04 ` Fredrik Noring
2020-12-13 15:23 ` Philippe Mathieu-Daudé
2020-12-13 16:40 ` Fredrik Noring
2020-12-14 12:05 ` Fredrik Noring
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