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From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: mchehab@kernel.org
Subject: [PATCH 26/38] ccs-pll: Better separate OP and VT sub-tree calculation
Date: Wed,  2 Dec 2020 20:06:29 +0200	[thread overview]
Message-ID: <20201202180641.17401-27-sakari.ailus@linux.intel.com> (raw)
In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com>

Better separate OP PLL branch calculation from VT branch calculation.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs-pll.c | 54 +++++++++++++++++++++----------------
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 96eb71f16c81..e879c03a3d3b 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -162,11 +162,11 @@ static int check_all_bounds(struct device *dev,
 #define PHY_CONST_DIV		16
 
 static void
-__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
-		       const struct ccs_pll_branch_limits_bk *op_lim_bk,
-		       struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
-		       struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
-		       uint32_t phy_const)
+ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
+		     const struct ccs_pll_branch_limits_bk *op_lim_bk,
+		     struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+		     struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
+		     uint32_t phy_const)
 {
 	uint32_t sys_div;
 	uint32_t best_pix_div = INT_MAX >> 1;
@@ -174,6 +174,9 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 	uint32_t min_vt_div, max_vt_div, vt_div;
 	uint32_t min_sys_div, max_sys_div;
 
+	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+		goto out_calc_pixel_rate;
+
 	/*
 	 * Find out whether a sensor supports derating. If it does not, VT and
 	 * OP domains are required to run at the same pixel rate.
@@ -313,6 +316,10 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 		pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
 	pll->vt_bk.pix_clk_freq_hz =
 		pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
+
+out_calc_pixel_rate:
+	pll->pixel_rate_pixel_array =
+		pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
 }
 
 /*
@@ -327,12 +334,12 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
  * @return Zero on success, error code on error.
  */
 static int
-__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
-		    const struct ccs_pll_branch_limits_fr *op_lim_fr,
-		    const struct ccs_pll_branch_limits_bk *op_lim_bk,
-		    struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
-		    struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
-		    uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
+ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
+		     const struct ccs_pll_branch_limits_fr *op_lim_fr,
+		     const struct ccs_pll_branch_limits_bk *op_lim_bk,
+		     struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
+		     struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
+		     uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
 {
 	/*
 	 * Higher multipliers (and divisors) are often required than
@@ -430,15 +437,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 
 	dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
 
-	if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS))
-		__ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
-				       op_pll_bk, cphy, phy_const);
-
-	pll->pixel_rate_pixel_array =
-		pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
-
-	return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr,
-				op_pll_bk);
+	return 0;
 }
 
 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
@@ -558,13 +557,22 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	     op_pll_fr->pre_pll_clk_div +=
 		     (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
 		     2 - (op_pll_fr->pre_pll_clk_div & 1)) {
-		rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
-					   op_pll_fr, op_pll_bk, mul, div, l,
-					   cphy, phy_const);
+		rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
+					    op_pll_fr, op_pll_bk, mul, div, l,
+					    cphy, phy_const);
+		if (rval)
+			continue;
+
+		ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
+				     op_pll_bk, cphy, phy_const);
+
+		rval = check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll,
+					op_pll_fr, op_pll_bk);
 		if (rval)
 			continue;
 
 		print_pll(dev, pll);
+
 		return 0;
 	}
 
-- 
2.27.0


  parent reply	other threads:[~2020-12-02 18:14 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-02 18:06 [PATCH 00/38] Support additional CCS PLL features, C-PHY Sakari Ailus
2020-12-02 18:06 ` [PATCH 01/38] ccs-pll: Don't use div_u64 to divide a 32-bit number Sakari Ailus
2020-12-02 18:06 ` [PATCH 02/38] ccs-pll: Split limits and PLL configuration into front and back parts Sakari Ailus
2020-12-02 18:06 ` [PATCH 03/38] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Sakari Ailus
2020-12-02 18:06 ` [PATCH 04/38] ccs-pll: End search if there are no better values available Sakari Ailus
2020-12-02 18:06 ` [PATCH 05/38] ccs-pll: Remove parallel bus support Sakari Ailus
2020-12-02 18:06 ` [PATCH 06/38] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Sakari Ailus
2020-12-02 18:06 ` [PATCH 07/38] ccs-pll: Move the flags field down, away from 8-bit fields Sakari Ailus
2020-12-02 18:06 ` [PATCH 08/38] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
2020-12-02 18:06 ` [PATCH 09/38] ccs-pll: Use the BIT macro Sakari Ailus
2020-12-02 18:06 ` [PATCH 10/38] ccs-pll: Begin calculation from OP system clock frequency Sakari Ailus
2020-12-02 18:06 ` [PATCH 11/38] ccs-pll: Fix condition for pre-PLL divider lower bound Sakari Ailus
2020-12-02 18:06 ` [PATCH 12/38] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Sakari Ailus
2020-12-02 18:06 ` [PATCH 13/38] ccs-pll: Fix comment on check against maximum PLL multiplier Sakari Ailus
2020-12-02 18:06 ` [PATCH 14/38] ccs-pll: Fix check for PLL multiplier upper bound Sakari Ailus
2020-12-02 18:06 ` [PATCH 15/38] ccs-pll: Use explicit 32-bit unsigned type Sakari Ailus
2020-12-02 18:06 ` [PATCH 16/38] ccs-pll: Add support for lane speed model Sakari Ailus
2020-12-02 18:06 ` [PATCH 17/38] ccs: " Sakari Ailus
2020-12-02 18:06 ` [PATCH 18/38] ccs-pll: Add support for decoupled OP domain calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 19/38] ccs-pll: Add support for extended input PLL clock divider Sakari Ailus
2020-12-02 18:06 ` [PATCH 20/38] ccs-pll: Support two cycles per pixel on OP domain Sakari Ailus
2020-12-02 18:06 ` [PATCH 21/38] ccs-pll: Add support flexible OP PLL pixel clock divider Sakari Ailus
2020-12-02 18:06 ` [PATCH 22/38] ccs-pll: Add sanity checks Sakari Ailus
2020-12-02 18:06 ` [PATCH 23/38] ccs-pll: Add C-PHY support Sakari Ailus
2020-12-02 18:06 ` [PATCH 24/38] ccs-pll: Split off VT subtree calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 25/38] ccs-pll: Check for derating and overrating, support non-derating sensors Sakari Ailus
2020-12-02 18:06 ` Sakari Ailus [this message]
2020-12-02 18:06 ` [PATCH 27/38] ccs-pll: Print relevant information on PLL tree Sakari Ailus
2020-12-02 18:06 ` [PATCH 28/38] ccs-pll: Rework bounds checks Sakari Ailus
2020-12-02 18:06 ` [PATCH 29/38] ccs-pll: Make VT divisors 16-bit Sakari Ailus
2020-12-02 18:06 ` [PATCH 30/38] ccs-pll: Fix VT post-PLL divisor calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 31/38] ccs-pll: Separate VT divisor limit calculation from the rest Sakari Ailus
2020-12-02 18:06 ` [PATCH 32/38] ccs-pll: Add trivial dual PLL support Sakari Ailus
2020-12-02 18:06 ` [PATCH 33/38] ccs: Dual " Sakari Ailus
2020-12-02 18:06 ` [PATCH 34/38] ccs-pll: Add support for DDR OP system and pixel clocks Sakari Ailus
2020-12-02 18:06 ` [PATCH 35/38] ccs: Add support for DDR OP SYS and OP PIX clocks Sakari Ailus
2020-12-02 18:06 ` [PATCH 36/38] ccs: Print written register values Sakari Ailus
2020-12-02 18:06 ` [PATCH 37/38] ccs-pll: Print pixel rates Sakari Ailus
2020-12-02 18:06 ` [PATCH 38/38] ccs: Add support for obtaining C-PHY configuration from firmware Sakari Ailus

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