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From: Bin Meng <bmeng.cn@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	qemu-block@nongnu.org, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH 21/22] docs/system: Add RISC-V documentation
Date: Thu, 31 Dec 2020 19:30:09 +0800	[thread overview]
Message-ID: <20201231113010.27108-22-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20201231113010.27108-1-bmeng.cn@gmail.com>

From: Bin Meng <bin.meng@windriver.com>

Add RISC-V system emulator documentation for generic information.
`Board-specific documentation` and `RISC-V CPU features` are only
a placeholder and will be added in the future.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 docs/system/target-riscv.rst | 62 ++++++++++++++++++++++++++++++++++++
 docs/system/targets.rst      |  1 +
 2 files changed, 63 insertions(+)
 create mode 100644 docs/system/target-riscv.rst

diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
new file mode 100644
index 0000000000..978b96cbdb
--- /dev/null
+++ b/docs/system/target-riscv.rst
@@ -0,0 +1,62 @@
+.. _RISC-V-System-emulator:
+
+RISC-V System emulator
+======================
+
+QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the
+``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine,
+``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine.
+
+QEMU has generally good support for RISC-V guests. It has support for
+several different machines. The reason we support so many is that
+RISC-V hardware is much more widely varying than x86 hardware. RISC-V
+CPUs are generally built into "system-on-chip" (SoC) designs created by
+many different companies with different devices, and these SoCs are
+then built into machines which can vary still further even if they use
+the same SoC.
+
+For most boards the CPU type is fixed (matching what the hardware has),
+so typically you don't need to specify the CPU type by hand, except for
+special cases like the ``virt`` board.
+
+Choosing a board model
+----------------------
+
+For QEMU's RISC-V system emulation, you must specify which board
+model you want to use with the ``-M`` or ``--machine`` option;
+there is no default.
+
+Because RISC-V systems differ so much and in fundamental ways, typically
+operating system or firmware images intended to run on one machine
+will not run at all on any other. This is often surprising for new
+users who are used to the x86 world where every system looks like a
+standard PC. (Once the kernel has booted, most userspace software
+cares much less about the detail of the hardware.)
+
+If you already have a system image or a kernel that works on hardware
+and you want to boot with QEMU, check whether QEMU lists that machine
+in its ``-machine help`` output. If it is listed, then you can probably
+use that board model. If it is not listed, then unfortunately your image
+will almost certainly not boot on QEMU. (You might be able to
+extract the filesystem and use that with a different kernel which
+boots on a system that QEMU does emulate.)
+
+If you don't care about reproducing the idiosyncrasies of a particular
+bit of hardware, such as small amount of RAM, no PCI or other hard
+disk, etc., and just want to run Linux, the best option is to use the
+``virt`` board. This is a platform which doesn't correspond to any
+real hardware and is designed for use in virtual machines. You'll
+need to compile Linux with a suitable configuration for running on
+the ``virt`` board. ``virt`` supports PCI, virtio, recent CPUs and
+large amounts of RAM. It also supports 64-bit CPUs.
+
+Board-specific documentation
+----------------------------
+
+Unfortunately many of the RISC-V boards QEMU supports are currently
+undocumented; you can get a complete list by running
+``qemu-system-riscv64 --machine help``, or
+``qemu-system-riscv32 --machine help``.
+
+RISC-V CPU features
+-------------------
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 564cea9a9b..75ed1087fd 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -19,6 +19,7 @@ Contents:
    target-m68k
    target-mips
    target-ppc
+   target-riscv
    target-rx
    target-s390x
    target-sparc
-- 
2.25.1



  parent reply	other threads:[~2020-12-31 11:53 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-31 11:29 [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support Bin Meng
2020-12-31 11:29 ` [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support Bin Meng
2021-01-04 16:00   ` Francisco Iglesias
2021-01-04 16:00     ` Francisco Iglesias
2021-01-04 23:30     ` Bin Meng
2021-01-04 23:30       ` Bin Meng
2020-12-31 11:29 ` [PATCH 02/22] hw/block: m25p80: Add various ISSI flash information Bin Meng
2021-01-05 21:16   ` Alistair Francis
2021-01-05 21:16     ` Alistair Francis
2020-12-31 11:29 ` [PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence Bin Meng
2021-01-02 13:49   ` Pragnesh Patel
2021-01-02 13:49     ` Pragnesh Patel
2020-12-31 11:29 ` [PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode Bin Meng
2021-01-02 13:50   ` Pragnesh Patel
2021-01-02 13:50     ` Pragnesh Patel
2020-12-31 11:29 ` [PATCH 05/22] hw/sd: sd: Drop sd_crc16() Bin Meng
2021-01-02 13:53   ` Pragnesh Patel
2021-01-02 13:53     ` Pragnesh Patel
2021-01-14 11:51   ` Philippe Mathieu-Daudé
2020-12-31 11:29 ` [PATCH 06/22] util: Add CRC16 (CCITT) calculation routines Bin Meng
2021-01-14 20:20   ` Alistair Francis
2021-01-14 20:20     ` Alistair Francis
2020-12-31 11:29 ` [PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16 Bin Meng
2021-01-13 16:54   ` Alistair Francis
2021-01-13 16:54     ` Alistair Francis
2020-12-31 11:29 ` [PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18) Bin Meng
2021-01-13 16:59   ` Alistair Francis
2021-01-13 16:59     ` Alistair Francis
2020-12-31 11:29 ` [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer Bin Meng
2021-01-13 17:00   ` Alistair Francis
2021-01-13 17:00     ` Alistair Francis
2021-01-14 11:40   ` Philippe Mathieu-Daudé
2020-12-31 11:29 ` [PATCH 10/22] hw/sd: sd: Remove duplicated codes in single/multiple block read/write Bin Meng
2021-01-13 17:02   ` Alistair Francis
2021-01-13 17:02     ` Alistair Francis
2020-12-31 11:29 ` [PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode Bin Meng
2021-01-13 17:03   ` Alistair Francis
2021-01-13 17:03     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 12/22] hw/sd: sd.h: Cosmetic change of using spaces Bin Meng
2021-01-13 17:59   ` Alistair Francis
2021-01-13 17:59     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 13/22] hw/sd: Introduce receive_ready() callback Bin Meng
2021-01-13 17:22   ` Alistair Francis
2021-01-13 17:22     ` Alistair Francis
2021-01-14 11:44   ` Philippe Mathieu-Daudé
2020-12-31 11:30 ` [PATCH 14/22] hw/sd: ssi-sd: Support single block write Bin Meng
2021-01-13 18:07   ` Alistair Francis
2021-01-13 18:07     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 15/22] hw/sd: ssi-sd: Support multiple " Bin Meng
2021-01-13 18:11   ` Alistair Francis
2021-01-13 18:11     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 16/22] hw/ssi: Add SiFive SPI controller support Bin Meng
2021-01-13 18:28   ` Alistair Francis
2021-01-13 18:28     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Bin Meng
2021-01-13 18:30   ` Alistair Francis
2021-01-13 18:30     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 18/22] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Bin Meng
2021-01-13 18:32   ` Alistair Francis
2021-01-13 18:32     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 19/22] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Bin Meng
2021-01-13 18:33   ` Alistair Francis
2021-01-13 18:33     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 20/22] docs/system: Sort targets in alphabetical order Bin Meng
2021-01-13 18:33   ` Alistair Francis
2021-01-13 18:33     ` Alistair Francis
2020-12-31 11:30 ` Bin Meng [this message]
2021-01-14  0:11   ` [PATCH 21/22] docs/system: Add RISC-V documentation Alistair Francis
2021-01-14  0:11     ` Alistair Francis
2020-12-31 11:30 ` [PATCH 22/22] docs/system: riscv: Add documentation for sifive_u machine Bin Meng
2021-01-14  0:11   ` Alistair Francis
2021-01-14  0:11     ` Alistair Francis
2021-01-02 12:26 ` [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support Pragnesh Patel
2021-01-02 12:26   ` Pragnesh Patel
2021-01-02 13:15   ` Bin Meng
2021-01-02 13:15     ` Bin Meng
2021-01-02 13:30     ` Pragnesh Patel
2021-01-02 13:30       ` Pragnesh Patel
2021-01-02 13:36       ` Bin Meng
2021-01-02 13:36         ` Bin Meng

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