From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/31] coresight: etm4x: Add commentary on the registers Date: Mon, 1 Feb 2021 11:13:32 -0700 [thread overview] Message-ID: <20210201181351.1475223-13-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> From: Suzuki K Poulose <suzuki.poulose@arm.com> As we are about define a switch..case table for individual register access by offset for implementing the system instruction support, document the possible set of registers for each group to make it easier to correlate. Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210110224850.1880240-11-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b6854f6fd666..3c2b49ffabc8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -45,13 +45,13 @@ #define TRCVDSACCTLR 0x0A4 #define TRCVDARCCTLR 0x0A8 /* Derived resources registers */ -#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ #define TRCSEQRSTEVR 0x118 #define TRCSEQSTR 0x11C #define TRCEXTINSELR 0x120 -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) -#define TRCCNTVRn(n) (0x160 + (n * 4)) +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ /* ID registers */ #define TRCIDR8 0x180 #define TRCIDR9 0x184 @@ -60,7 +60,7 @@ #define TRCIDR12 0x190 #define TRCIDR13 0x194 #define TRCIMSPEC0 0x1C0 -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ #define TRCIDR0 0x1E0 #define TRCIDR1 0x1E4 #define TRCIDR2 0x1E8 @@ -69,9 +69,12 @@ #define TRCIDR5 0x1F4 #define TRCIDR6 0x1F8 #define TRCIDR7 0x1FC -/* Resource selection registers */ +/* + * Resource selection registers, n = 2-31. + * First pair (regs 0, 1) is always present and is reserved. + */ #define TRCRSCTLRn(n) (0x200 + (n * 4)) -/* Single-shot comparator registers */ +/* Single-shot comparator registers, n = 0-7 */ #define TRCSSCCRn(n) (0x280 + (n * 4)) #define TRCSSCSRn(n) (0x2A0 + (n * 4)) #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) @@ -81,11 +84,13 @@ #define TRCPDCR 0x310 #define TRCPDSR 0x314 /* Trace registers (0x318-0xEFC) */ -/* Comparator registers */ +/* Address Comparator registers n = 0-15 */ #define TRCACVRn(n) (0x400 + (n * 8)) #define TRCACATRn(n) (0x480 + (n * 8)) +/* Data Value Comparator Value registers, n = 0-7 */ #define TRCDVCVRn(n) (0x500 + (n * 16)) #define TRCDVCMRn(n) (0x580 + (n * 16)) +/* ContextID/Virtual ContextID comparators, n = 0-7 */ #define TRCCIDCVRn(n) (0x600 + (n * 8)) #define TRCVMIDCVRn(n) (0x640 + (n * 8)) #define TRCCIDCCTLR0 0x680 -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/31] coresight: etm4x: Add commentary on the registers Date: Mon, 1 Feb 2021 11:13:32 -0700 [thread overview] Message-ID: <20210201181351.1475223-13-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> From: Suzuki K Poulose <suzuki.poulose@arm.com> As we are about define a switch..case table for individual register access by offset for implementing the system instruction support, document the possible set of registers for each group to make it easier to correlate. Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210110224850.1880240-11-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b6854f6fd666..3c2b49ffabc8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -45,13 +45,13 @@ #define TRCVDSACCTLR 0x0A4 #define TRCVDARCCTLR 0x0A8 /* Derived resources registers */ -#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ #define TRCSEQRSTEVR 0x118 #define TRCSEQSTR 0x11C #define TRCEXTINSELR 0x120 -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) -#define TRCCNTVRn(n) (0x160 + (n * 4)) +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ /* ID registers */ #define TRCIDR8 0x180 #define TRCIDR9 0x184 @@ -60,7 +60,7 @@ #define TRCIDR12 0x190 #define TRCIDR13 0x194 #define TRCIMSPEC0 0x1C0 -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ #define TRCIDR0 0x1E0 #define TRCIDR1 0x1E4 #define TRCIDR2 0x1E8 @@ -69,9 +69,12 @@ #define TRCIDR5 0x1F4 #define TRCIDR6 0x1F8 #define TRCIDR7 0x1FC -/* Resource selection registers */ +/* + * Resource selection registers, n = 2-31. + * First pair (regs 0, 1) is always present and is reserved. + */ #define TRCRSCTLRn(n) (0x200 + (n * 4)) -/* Single-shot comparator registers */ +/* Single-shot comparator registers, n = 0-7 */ #define TRCSSCCRn(n) (0x280 + (n * 4)) #define TRCSSCSRn(n) (0x2A0 + (n * 4)) #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) @@ -81,11 +84,13 @@ #define TRCPDCR 0x310 #define TRCPDSR 0x314 /* Trace registers (0x318-0xEFC) */ -/* Comparator registers */ +/* Address Comparator registers n = 0-15 */ #define TRCACVRn(n) (0x400 + (n * 8)) #define TRCACATRn(n) (0x480 + (n * 8)) +/* Data Value Comparator Value registers, n = 0-7 */ #define TRCDVCVRn(n) (0x500 + (n * 16)) #define TRCDVCMRn(n) (0x580 + (n * 16)) +/* ContextID/Virtual ContextID comparators, n = 0-7 */ #define TRCCIDCVRn(n) (0x600 + (n * 8)) #define TRCVMIDCVRn(n) (0x640 + (n * 8)) #define TRCCIDCCTLR0 0x680 -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-01 18:17 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-01 18:13 [PATCH 00/31] coresight: Patches for v5.12 Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 01/31] coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 02/31] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 03/31] coresight: etm4x: Handle access to TRCSSPCICRn Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 04/31] coresight: etm4x: Skip accessing TRCPDCR in save/restore Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 05/31] coresight: Introduce device access abstraction Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 06/31] coresight: tpiu: Prepare for using coresight " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 07/31] coresight: Convert coresight_timeout to use " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 08/31] coresight: Convert claim/disclaim operations to use access wrappers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 10/31] coresight: etm4x: Convert all register accesses Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 11/31] coresight: etm4x: Make offset available for sysfs attributes Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier [this message] 2021-02-01 18:13 ` [PATCH 12/31] coresight: etm4x: Add commentary on the registers Mathieu Poirier 2021-02-01 18:13 ` [PATCH 13/31] coresight: etm4x: Add sysreg access helpers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 14/31] coresight: etm4x: Hide sysfs attributes for unavailable registers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 15/31] coresight: etm4x: Define DEVARCH register fields Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 16/31] coresight: etm4x: Check for Software Lock Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 17/31] coresight: etm4x: Cleanup secure exception level masks Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 18/31] coresight: etm4x: Clean up " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 19/31] coresight: etm4x: Handle ETM architecture version Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 20/31] coresight: etm4x: Detect access early on the target CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 21/31] coresight: etm4x: Use TRCDEVARCH for component discovery Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 22/31] coresight: etm4x: Expose trcdevarch via sysfs Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 23/31] coresight: etm4x: Add necessary synchronization for sysreg access Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 24/31] coresight: etm4x: Detect system instructions support Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 25/31] coresight: etm4x: Refactor probing routine Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 26/31] coresight: etm4x: Run arch feature detection on the CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 27/31] coresight: etm4x: Add support for sysreg only devices Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 28/31] dts: bindings: coresight: ETM system register access only units Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 29/31] arm64: Add TRFCR_ELx definitions Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 30/31] coresight: Add support for v8.4 SelfHosted tracing Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 31/31] coresight: etm4x: Handle accesses to TRCSTALLCTLR Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-04 16:01 ` [PATCH 00/31] coresight: Patches for v5.12 Greg KH 2021-02-04 16:01 ` Greg KH
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