From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
Date: Thu, 6 May 2021 00:06:12 +0800 [thread overview]
Message-ID: <20210505160620.15723-12-frank.chang@sifive.com> (raw)
In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++++++++++
3 files changed, 81 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6bc9bbae9e0..71a9a182c01 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 28640322c43..429738db155 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotl_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_sro);
}
+
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rolw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 088cf9f7678..c09b93f1b8a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
Date: Thu, 6 May 2021 00:06:12 +0800 [thread overview]
Message-ID: <20210505160620.15723-12-frank.chang@sifive.com> (raw)
In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++++++++++
3 files changed, 81 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6bc9bbae9e0..71a9a182c01 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 28640322c43..429738db155 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotl_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_sro);
}
+
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rolw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 088cf9f7678..c09b93f1b8a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
next prev parent reply other threads:[~2021-05-05 16:18 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
2021-05-05 16:06 ` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-06 2:04 ` Alistair Francis
2021-05-06 2:04 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 03/17] target/riscv: rvb: count bits set frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 04/17] target/riscv: rvb: logic-with-negate frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 06/17] target/riscv: rvb: min/max instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:23 ` Alistair Francis
2021-05-10 7:23 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:24 ` Alistair Francis
2021-05-10 7:24 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 10/17] target/riscv: rvb: shift ones frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:26 ` Alistair Francis
2021-05-10 7:26 ` Alistair Francis
2021-05-05 16:06 ` frank.chang [this message]
2021-05-05 16:06 ` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) frank.chang
2021-05-20 7:11 ` Alistair Francis
2021-05-20 7:11 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 12/17] target/riscv: rvb: generalized reverse frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 14/17] target/riscv: rvb: address calculation frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-27 22:05 ` Alistair Francis
2021-05-27 22:05 ` Alistair Francis
2021-05-27 22:08 ` [PATCH v6 00/17] support subsets of bitmanip extension Alistair Francis
2021-05-27 22:08 ` Alistair Francis
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