From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 13/17] drm/i915/fbc: Finish polishing FBC1 registers
Date: Thu, 4 Nov 2021 16:45:16 +0200 [thread overview]
Message-ID: <20211104144520.22605-14-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Switch all the FBC1 registers over to REG_BTT()/etc.
And while at it add a few more registers/bits that
escaped the net previously.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++----------
2 files changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1c9ada22b4de..888ee814e8bb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -189,7 +189,7 @@ static u32 i965_fbc_ctl2(struct drm_i915_private *i915)
FBC_CTL_PLANE(params->crtc.i9xx_plane);
if (params->fence_id >= 0)
- fbc_ctl2 |= FBC_CTL_CPU_FENCE;
+ fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
return fbc_ctl2;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d937958e7a6b..3463853e4a6d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3309,34 +3309,44 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
#define FBC_CONTROL _MMIO(0x3208)
-#define FBC_CTL_EN REG_BIT(31)
-#define FBC_CTL_PERIODIC REG_BIT(30)
-#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
-#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
-#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
-#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
-#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */
-#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
-#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
-#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
-#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
+#define FBC_CTL_EN REG_BIT(31)
+#define FBC_CTL_PERIODIC REG_BIT(30)
+#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
+#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
+#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
+#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
+#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
+#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
+#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
+#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
+#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
#define FBC_COMMAND _MMIO(0x320c)
-#define FBC_CMD_COMPRESS (1 << 0)
+#define FBC_CMD_COMPRESS REG_BIT(0)
#define FBC_STATUS _MMIO(0x3210)
-#define FBC_STAT_COMPRESSING (1 << 31)
-#define FBC_STAT_COMPRESSED (1 << 30)
-#define FBC_STAT_MODIFIED (1 << 29)
-#define FBC_STAT_CURRENT_LINE_SHIFT (0)
-#define FBC_CONTROL2 _MMIO(0x3214)
-#define FBC_CTL_FENCE_DBL (0 << 4)
-#define FBC_CTL_IDLE_IMM (0 << 2)
-#define FBC_CTL_IDLE_FULL (1 << 2)
-#define FBC_CTL_IDLE_LINE (2 << 2)
-#define FBC_CTL_IDLE_DEBUG (3 << 2)
-#define FBC_CTL_CPU_FENCE (1 << 1)
-#define FBC_CTL_PLANE(plane) ((plane) << 0)
-#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
-#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
+#define FBC_STAT_COMPRESSING REG_BIT(31)
+#define FBC_STAT_COMPRESSED REG_BIT(30)
+#define FBC_STAT_MODIFIED REG_BIT(29)
+#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
+#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
+#define FBC_CTL_FENCE_DBL REG_BIT(4)
+#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
+#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
+#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
+#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
+#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
+#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
+#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
+#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
+#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
+#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
+#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
+#define FBC_MOD_NUM_VALID REG_BIT(0)
+#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
+#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
+#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
+#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
+#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
+#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
#define FBC_LL_SIZE (1536)
--
2.32.0
next prev parent reply other threads:[~2021-11-04 14:46 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 14:45 [Intel-gfx] [PATCH 00/17] drm/i915/fbc: Prep work for multiple FBC instances Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 01/17] drm/i915/fbc: Exract snb_fbc_program_fence() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 02/17] drm/i915/fbc: Extract {skl, glk}_fbc_program_cfb_stride() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 03/17] drm/i915/fbc: Just use params->fence_y_offset always Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 04/17] drm/i915/fbc: Introduce intel_fbc_is_compressing() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 05/17] drm/i915/fbc: Extract helpers to compute FBC control register values Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 06/17] drm/i915/fbc: Introduce intel_fbc_funcs Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 07/17] drm/i915/fbc: Introduce .nuke() vfunc Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 08/17] drm/i915/fbc: s/gen7/ivb/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc Ville Syrjala
2021-11-12 11:11 ` Jani Nikula
2021-11-04 14:45 ` [Intel-gfx] [PATCH 10/17] drm/i915/fbc: Introduce intel_fbc_set_false_color() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 11/17] drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 12/17] drm/i915/fbc: Clean up all register defines Ville Syrjala
2021-11-04 14:45 ` Ville Syrjala [this message]
2021-11-04 14:45 ` [Intel-gfx] [PATCH 14/17] drm/i915: Relocate FBC_LLC_READ_CTRL Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 15/17] drm/i915/fbc: s/dev_priv/i915/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 16/17] drm/i915/fbc: Start passing around intel_fbc Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 17/17] drm/1915/fbc: Replace plane->has_fbc with a pointer to the fbc instance Ville Syrjala
2021-11-04 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: Prep work for multiple FBC instances Patchwork
2021-11-04 18:52 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-04 19:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-04 22:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-11-05 13:08 ` [Intel-gfx] [PATCH 00/17] " Jani Nikula
2021-11-11 12:28 ` Kahola, Mika
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