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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Rename divider table
Date: Thu, 16 Dec 2021 12:54:29 +0000	[thread overview]
Message-ID: <20211216125446.15451-8-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Biju Das <biju.das.jz@bp.renesas.com>

commit e93c1373613fb2f3e59db5f13271f155820e6a67 upstream.

As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 50b5269586a4..d5803fb1242e 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -42,12 +42,13 @@ enum clk_ids {
 };
 
 /* Divider tables */
-static const struct clk_div_table dtable_3b[] = {
+static const struct clk_div_table dtable_1_32[] = {
 	{0, 1},
 	{1, 2},
 	{2, 4},
 	{3, 8},
 	{4, 32},
+	{0, 0},
 };
 
 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -72,10 +73,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	/* Core output clk */
 	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
 	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
-		dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+		dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
 	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
-		DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 };
 
 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
-- 
2.17.1



  parent reply	other threads:[~2021-12-16 12:54 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-16 12:54 [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-12-17 10:10   ` Pavel Machek
2021-12-17 11:03     ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 06/24] clk: renesas: Add support for R9A07G044 SoC Lad Prabhakar
2021-12-16 12:54 ` Lad Prabhakar [this message]
2021-12-16 12:54 ` [PATCH 5.10.y-cip 08/24] clk: renesas: r9a07g044: Fix P1 Clock Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 09/24] clk: renesas: r9a07g044: Add P2 Clock support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l: Add multi clock PM support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar
2021-12-17 10:19   ` Pavel Machek
2021-12-17 11:11     ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 13/24] arm64: dts: renesas: r9a07g044: Add SYSC node Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 14/24] dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 15/24] clk: renesas: rzg2l: Remove unneeded semicolon Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 16/24] clk: renesas: rzg2l: Fix return value and unused assignment Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 17/24] clk: renesas: rzg2l: Fix a double free on error Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 18/24] clk: renesas: rzg2l: Avoid mixing error pointers and NULL Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 19/24] clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 20/24] clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 21/24] clk: mux: provide devm_clk_hw_register_mux() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 22/24] clk: renesas: rzg2l: Add support to handle MUX clocks Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 23/24] clk: renesas: rzg2l: Add support to handle coupled clocks Lad Prabhakar
2021-12-17 10:38   ` Pavel Machek
2021-12-17 11:29     ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 24/24] clk: renesas: rzg2l: Fix clk status function Lad Prabhakar
2021-12-17  7:42 ` [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK nobuhiro1.iwamatsu
2021-12-17 10:39   ` Pavel Machek

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