From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [PATCH 08/11] drm/i915/pvc: Interrupt support for new copy engines Date: Mon, 2 May 2022 09:34:14 -0700 [thread overview] Message-ID: <20220502163417.2635462-9-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220502163417.2635462-1-matthew.d.roper@intel.com> This patch adds the interrupt handler support for new copy engines. Bspec: 54030 Original-author: CQ Tang Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 88b4becfcb17..3a72d4fd0214 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt) /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) + intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) + intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) + intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) + intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) @@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); + if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) + intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) + intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) + intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) + intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index aa2c0974b02c..fe09288a3145 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1529,6 +1529,10 @@ #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) +#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110) +#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114) +#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118) +#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c) #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 08/11] drm/i915/pvc: Interrupt support for new copy engines Date: Mon, 2 May 2022 09:34:14 -0700 [thread overview] Message-ID: <20220502163417.2635462-9-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220502163417.2635462-1-matthew.d.roper@intel.com> This patch adds the interrupt handler support for new copy engines. Bspec: 54030 Original-author: CQ Tang Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 88b4becfcb17..3a72d4fd0214 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt) /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) + intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) + intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) + intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); + if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) + intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) @@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); + if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) + intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) + intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) + intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); + if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) + intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index aa2c0974b02c..fe09288a3145 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1529,6 +1529,10 @@ #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) +#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110) +#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114) +#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118) +#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c) #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) -- 2.35.1
next prev parent reply other threads:[~2022-05-02 16:34 UTC|newest] Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-02 16:34 [PATCH 00/11] i915: Introduce Ponte Vecchio Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 16:34 ` [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 20:44 ` Lucas De Marchi 2022-05-02 20:44 ` [Intel-gfx] " Lucas De Marchi 2022-05-02 16:34 ` [PATCH 02/11] drm/i915/pvc: Add forcewake support Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 22:33 ` Summers, Stuart 2022-05-02 22:33 ` [Intel-gfx] " Summers, Stuart 2022-05-05 0:34 ` Matt Roper 2022-05-05 0:34 ` Matt Roper 2022-05-02 16:34 ` [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 16:50 ` Matt Roper 2022-05-02 16:50 ` [Intel-gfx] " Matt Roper 2022-05-02 18:39 ` Lucas De Marchi 2022-05-02 18:50 ` Matt Roper 2022-05-02 19:27 ` Lucas De Marchi 2022-05-02 19:42 ` Matt Roper 2022-05-02 21:03 ` Lucas De Marchi 2022-05-02 21:03 ` [Intel-gfx] " Lucas De Marchi 2022-05-02 21:14 ` Matt Roper 2022-05-02 21:14 ` [Intel-gfx] " Matt Roper 2022-05-03 6:22 ` Lucas De Marchi 2022-05-03 6:22 ` [Intel-gfx] " Lucas De Marchi 2022-05-02 16:34 ` [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 16:55 ` Rodrigo Vivi 2022-05-02 16:55 ` [Intel-gfx] " Rodrigo Vivi 2022-05-02 16:34 ` [PATCH 05/11] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 16:34 ` [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 18:46 ` Souza, Jose 2022-05-02 18:46 ` [Intel-gfx] " Souza, Jose 2022-05-03 8:25 ` Tvrtko Ursulin 2022-05-02 16:34 ` [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 18:45 ` Souza, Jose 2022-05-03 8:05 ` Tvrtko Ursulin 2022-05-03 8:05 ` Tvrtko Ursulin 2022-05-05 20:59 ` Matt Roper 2022-05-05 20:59 ` Matt Roper 2022-05-06 7:21 ` Tvrtko Ursulin 2022-05-06 7:21 ` Tvrtko Ursulin 2022-05-06 14:29 ` Matt Roper 2022-05-06 14:29 ` Matt Roper 2022-05-02 16:34 ` Matt Roper [this message] 2022-05-02 16:34 ` [Intel-gfx] [PATCH 08/11] drm/i915/pvc: Interrupt support " Matt Roper 2022-05-02 22:23 ` Summers, Stuart 2022-05-02 22:23 ` [Intel-gfx] " Summers, Stuart 2022-05-02 16:34 ` [PATCH 09/11] drm/i915/pvc: Reset " Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 18:44 ` Souza, Jose 2022-05-02 22:23 ` Summers, Stuart 2022-05-02 16:34 ` [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 18:40 ` Souza, Jose 2022-05-02 22:58 ` Kumar Valsan, Prathap 2022-05-02 22:58 ` Kumar Valsan, Prathap 2022-05-02 16:34 ` [PATCH 11/11] drm/i915/pvc: read fuses for link copy engines Matt Roper 2022-05-02 16:34 ` [Intel-gfx] " Matt Roper 2022-05-02 18:48 ` Souza, Jose 2022-05-02 18:48 ` [Intel-gfx] " Souza, Jose 2022-05-03 8:19 ` Tvrtko Ursulin 2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio Patchwork 2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-05-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-05-02 22:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-05-03 17:32 ` Matt Roper 2022-05-04 17:03 ` Vudum, Lakshminarayana 2022-05-03 8:21 ` [Intel-gfx] [PATCH 00/11] " Tvrtko Ursulin 2022-05-03 14:56 ` Matt Roper 2022-05-03 15:01 ` Tvrtko Ursulin 2022-05-04 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork 2022-05-04 16:43 ` Patchwork
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