From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 00/13] Mediatek MT6735 main clock and reset drivers
Date: Wed, 4 May 2022 16:25:48 +0400 [thread overview]
Message-ID: <20220504122601.335495-1-y.oudjana@protonmail.com> (raw)
From: Yassine Oudjana <y.oudjana@protonmail.com>
This series adds support for the main clock and reset controllers on the
Mediatek MT6735 SoC:
- apmixedsys (global PLLs)
- topckgen (global divisors and muxes)
- infracfg (gates and resets for internal components)
- pericfg (gates and resets for peripherals)
MT6735 has other more specialized clock controllers, support for which is
not included in this series:
- imgsys (camera)
- mmsys (display)
- vdecsys (video decoder)
- audsys (audio)
Some symbols in common objects are exported to get the drivers to compile
as modules, and mtk_unregister_reset_controller() is implemented to allow
for unregistering reset controllers in the infracfg and pericfg drivers
when unloading them.
Yassine Oudjana (13):
dt-bindings: clock: Add Mediatek MT6735 clock bindings
dt-bindings: reset: Add MT6735 reset bindings
dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
clk: composite: Export clk_unregister_composite
clk: mediatek: Export mtk_free_clk_data
clk: mediatek: Add driver for MT6735 apmixedsys
clk: mediatek: Add driver for MT6735 topckgen
clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
clk: mediatek: reset: Export mtk_register_reset_controller symbols
clk: mediatek: reset: Return mtk_reset pointer on register
clk: mediatek: reset: Implement mtk_unregister_reset_controller() API
clk: mediatek: Add driver for MT6735 infracfg
clk: mediatek: Add driver for MT6735 pericfg
.../arm/mediatek/mediatek,infracfg.yaml | 8 +-
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 4 +-
.../bindings/clock/mediatek,topckgen.yaml | 4 +-
MAINTAINERS | 16 +
drivers/clk/clk-composite.c | 1 +
drivers/clk/mediatek/Kconfig | 28 +
drivers/clk/mediatek/Makefile | 4 +
drivers/clk/mediatek/clk-gate.c | 1 +
drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++
drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 ++++
drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 +++++
drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 1 +
drivers/clk/mediatek/clk-mtk.h | 8 +-
drivers/clk/mediatek/reset.c | 31 +-
.../clock/mediatek,mt6735-apmixedsys.h | 16 +
.../clock/mediatek,mt6735-infracfg.h | 25 +
.../clock/mediatek,mt6735-pericfg.h | 37 +
.../clock/mediatek,mt6735-topckgen.h | 79 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +
.../reset/mediatek,mt6735-pericfg.h | 31 +
22 files changed, 2366 insertions(+), 18 deletions(-)
create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
--
2.36.0
WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 00/13] Mediatek MT6735 main clock and reset drivers
Date: Wed, 4 May 2022 16:25:48 +0400 [thread overview]
Message-ID: <20220504122601.335495-1-y.oudjana@protonmail.com> (raw)
From: Yassine Oudjana <y.oudjana@protonmail.com>
This series adds support for the main clock and reset controllers on the
Mediatek MT6735 SoC:
- apmixedsys (global PLLs)
- topckgen (global divisors and muxes)
- infracfg (gates and resets for internal components)
- pericfg (gates and resets for peripherals)
MT6735 has other more specialized clock controllers, support for which is
not included in this series:
- imgsys (camera)
- mmsys (display)
- vdecsys (video decoder)
- audsys (audio)
Some symbols in common objects are exported to get the drivers to compile
as modules, and mtk_unregister_reset_controller() is implemented to allow
for unregistering reset controllers in the infracfg and pericfg drivers
when unloading them.
Yassine Oudjana (13):
dt-bindings: clock: Add Mediatek MT6735 clock bindings
dt-bindings: reset: Add MT6735 reset bindings
dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
clk: composite: Export clk_unregister_composite
clk: mediatek: Export mtk_free_clk_data
clk: mediatek: Add driver for MT6735 apmixedsys
clk: mediatek: Add driver for MT6735 topckgen
clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
clk: mediatek: reset: Export mtk_register_reset_controller symbols
clk: mediatek: reset: Return mtk_reset pointer on register
clk: mediatek: reset: Implement mtk_unregister_reset_controller() API
clk: mediatek: Add driver for MT6735 infracfg
clk: mediatek: Add driver for MT6735 pericfg
.../arm/mediatek/mediatek,infracfg.yaml | 8 +-
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 4 +-
.../bindings/clock/mediatek,topckgen.yaml | 4 +-
MAINTAINERS | 16 +
drivers/clk/clk-composite.c | 1 +
drivers/clk/mediatek/Kconfig | 28 +
drivers/clk/mediatek/Makefile | 4 +
drivers/clk/mediatek/clk-gate.c | 1 +
drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++
drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 ++++
drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 +++++
drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 1 +
drivers/clk/mediatek/clk-mtk.h | 8 +-
drivers/clk/mediatek/reset.c | 31 +-
.../clock/mediatek,mt6735-apmixedsys.h | 16 +
.../clock/mediatek,mt6735-infracfg.h | 25 +
.../clock/mediatek,mt6735-pericfg.h | 37 +
.../clock/mediatek,mt6735-topckgen.h | 79 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +
.../reset/mediatek,mt6735-pericfg.h | 31 +
22 files changed, 2366 insertions(+), 18 deletions(-)
create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
--
2.36.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 00/13] Mediatek MT6735 main clock and reset drivers
Date: Wed, 4 May 2022 16:25:48 +0400 [thread overview]
Message-ID: <20220504122601.335495-1-y.oudjana@protonmail.com> (raw)
From: Yassine Oudjana <y.oudjana@protonmail.com>
This series adds support for the main clock and reset controllers on the
Mediatek MT6735 SoC:
- apmixedsys (global PLLs)
- topckgen (global divisors and muxes)
- infracfg (gates and resets for internal components)
- pericfg (gates and resets for peripherals)
MT6735 has other more specialized clock controllers, support for which is
not included in this series:
- imgsys (camera)
- mmsys (display)
- vdecsys (video decoder)
- audsys (audio)
Some symbols in common objects are exported to get the drivers to compile
as modules, and mtk_unregister_reset_controller() is implemented to allow
for unregistering reset controllers in the infracfg and pericfg drivers
when unloading them.
Yassine Oudjana (13):
dt-bindings: clock: Add Mediatek MT6735 clock bindings
dt-bindings: reset: Add MT6735 reset bindings
dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
clk: composite: Export clk_unregister_composite
clk: mediatek: Export mtk_free_clk_data
clk: mediatek: Add driver for MT6735 apmixedsys
clk: mediatek: Add driver for MT6735 topckgen
clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
clk: mediatek: reset: Export mtk_register_reset_controller symbols
clk: mediatek: reset: Return mtk_reset pointer on register
clk: mediatek: reset: Implement mtk_unregister_reset_controller() API
clk: mediatek: Add driver for MT6735 infracfg
clk: mediatek: Add driver for MT6735 pericfg
.../arm/mediatek/mediatek,infracfg.yaml | 8 +-
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 4 +-
.../bindings/clock/mediatek,topckgen.yaml | 4 +-
MAINTAINERS | 16 +
drivers/clk/clk-composite.c | 1 +
drivers/clk/mediatek/Kconfig | 28 +
drivers/clk/mediatek/Makefile | 4 +
drivers/clk/mediatek/clk-gate.c | 1 +
drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++
drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 ++++
drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 +++++
drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 1 +
drivers/clk/mediatek/clk-mtk.h | 8 +-
drivers/clk/mediatek/reset.c | 31 +-
.../clock/mediatek,mt6735-apmixedsys.h | 16 +
.../clock/mediatek,mt6735-infracfg.h | 25 +
.../clock/mediatek,mt6735-pericfg.h | 37 +
.../clock/mediatek,mt6735-topckgen.h | 79 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +
.../reset/mediatek,mt6735-pericfg.h | 31 +
22 files changed, 2366 insertions(+), 18 deletions(-)
create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-05-04 12:28 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 12:25 Yassine Oudjana [this message]
2022-05-04 12:25 ` [PATCH 00/13] Mediatek MT6735 main clock and reset drivers Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:48 ` Rob Herring
2022-05-16 23:48 ` Rob Herring
2022-05-16 23:48 ` Rob Herring
2022-05-04 12:25 ` [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-04 12:25 ` [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 12:25 ` [PATCH 04/13] clk: composite: Export clk_unregister_composite Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
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