From: Tamseel Shams <m.shams@samsung.com> To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, krzk+dt@kernel.org Cc: geert@linux-m68k.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, alim.akhtar@samsung.com, paul@crapouillou.net, linux-fsd@tesla.com, Tamseel Shams <m.shams@samsung.com> Subject: [PATCH v2 2/3] iio: adc: exynos-adc: Add support for ADC FSD-HW controller Date: Fri, 20 May 2022 20:28:19 +0530 [thread overview] Message-ID: <20220520145820.67667-3-m.shams@samsung.com> (raw) In-Reply-To: <20220520145820.67667-1-m.shams@samsung.com> From: Alim Akhtar <alim.akhtar@samsung.com> Exynos's ADC-FSD-HW has some difference in registers set, number of programmable channels (16 channel) etc. This patch adds support for ADC-FSD-HW controller version. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tamseel Shams <m.shams@samsung.com> --- - Changes since v1 * Addressed Jonathan's comment by using already provided isr handle drivers/iio/adc/exynos_adc.c | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index cff1ba57fb16..183ae591327a 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -55,6 +55,11 @@ #define ADC_V2_INT_ST(x) ((x) + 0x14) #define ADC_V2_VER(x) ((x) + 0x20) +/* ADC_FSD_HW register definitions */ +#define ADC_FSD_DAT(x) ((x) + 0x08) +#define ADC_FSD_DAT_SUM(x) ((x) + 0x0C) +#define ADC_FSD_DBG_DATA(x) ((x) + 0x1C) + /* Bit definitions for ADC_V1 */ #define ADC_V1_CON_RES (1u << 16) #define ADC_V1_CON_PRSCEN (1u << 14) @@ -92,6 +97,7 @@ /* Bit definitions for ADC_V2 */ #define ADC_V2_CON1_SOFT_RESET (1u << 2) +#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1) #define ADC_V2_CON2_OSEL (1u << 10) #define ADC_V2_CON2_ESEL (1u << 9) @@ -100,6 +106,7 @@ #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) #define ADC_V2_CON2_ACH_MASK 0xF +#define MAX_ADC_FSD_CHANNELS 16 #define MAX_ADC_V2_CHANNELS 10 #define MAX_ADC_V1_CHANNELS 8 #define MAX_EXYNOS3250_ADC_CHANNELS 2 @@ -484,6 +491,43 @@ static const struct exynos_adc_data exynos7_adc_data = { .start_conv = exynos_adc_v2_start_conv, }; +static void exynos_adc_fsd_init_hw(struct exynos_adc *info) +{ + u32 con2; + + writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs)); + + writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info->regs)); + + con2 = ADC_V2_CON2_C_TIME(6); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); +} + +static void exynos_adc_fsd_exit_hw(struct exynos_adc *info) +{ + u32 con2; + + con2 = readl(ADC_V2_CON2(info->regs)); + con2 &= ~ADC_V2_CON2_C_TIME(7); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Disable interrupts */ + writel(0, ADC_V2_INT_EN(info->regs)); +} + +static const struct exynos_adc_data fsd_hw_adc_data = { + .num_channels = MAX_ADC_FSD_CHANNELS, + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ + + .init_hw = exynos_adc_fsd_init_hw, + .exit_hw = exynos_adc_fsd_exit_hw, + .clear_irq = exynos_adc_v2_clear_irq, + .start_conv = exynos_adc_v2_start_conv, +}; + static const struct of_device_id exynos_adc_match[] = { { .compatible = "samsung,s3c2410-adc", @@ -518,6 +562,9 @@ static const struct of_device_id exynos_adc_match[] = { }, { .compatible = "samsung,exynos7-adc", .data = &exynos7_adc_data, + }, { + .compatible = "samsung,exynos-adc-fsd-hw", + .data = &fsd_hw_adc_data, }, {}, }; @@ -626,6 +673,8 @@ static irqreturn_t exynos_adc_isr(int irq, void *dev_id) info->ts_x = readl(ADC_V1_DATX(info->regs)); info->ts_y = readl(ADC_V1_DATY(info->regs)); writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs)); + } else if (of_device_is_compatible(info->dev->of_node, "samsung,exynos-adc-fsd-hw")) { + info->value = readl(ADC_FSD_DAT(info->regs)) & mask; } else { info->value = readl(ADC_V1_DATX(info->regs)) & mask; } @@ -719,6 +768,12 @@ static const struct iio_chan_spec exynos_adc_iio_channels[] = { ADC_CHANNEL(7, "adc7"), ADC_CHANNEL(8, "adc8"), ADC_CHANNEL(9, "adc9"), + ADC_CHANNEL(10, "adc10"), + ADC_CHANNEL(11, "adc11"), + ADC_CHANNEL(12, "adc12"), + ADC_CHANNEL(13, "adc13"), + ADC_CHANNEL(14, "adc14"), + ADC_CHANNEL(15, "adc15"), }; static int exynos_adc_remove_devices(struct device *dev, void *c) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Tamseel Shams <m.shams@samsung.com> To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, krzk+dt@kernel.org Cc: geert@linux-m68k.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, alim.akhtar@samsung.com, paul@crapouillou.net, linux-fsd@tesla.com, Tamseel Shams <m.shams@samsung.com> Subject: [PATCH v2 2/3] iio: adc: exynos-adc: Add support for ADC FSD-HW controller Date: Fri, 20 May 2022 20:28:19 +0530 [thread overview] Message-ID: <20220520145820.67667-3-m.shams@samsung.com> (raw) In-Reply-To: <20220520145820.67667-1-m.shams@samsung.com> From: Alim Akhtar <alim.akhtar@samsung.com> Exynos's ADC-FSD-HW has some difference in registers set, number of programmable channels (16 channel) etc. This patch adds support for ADC-FSD-HW controller version. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tamseel Shams <m.shams@samsung.com> --- - Changes since v1 * Addressed Jonathan's comment by using already provided isr handle drivers/iio/adc/exynos_adc.c | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index cff1ba57fb16..183ae591327a 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -55,6 +55,11 @@ #define ADC_V2_INT_ST(x) ((x) + 0x14) #define ADC_V2_VER(x) ((x) + 0x20) +/* ADC_FSD_HW register definitions */ +#define ADC_FSD_DAT(x) ((x) + 0x08) +#define ADC_FSD_DAT_SUM(x) ((x) + 0x0C) +#define ADC_FSD_DBG_DATA(x) ((x) + 0x1C) + /* Bit definitions for ADC_V1 */ #define ADC_V1_CON_RES (1u << 16) #define ADC_V1_CON_PRSCEN (1u << 14) @@ -92,6 +97,7 @@ /* Bit definitions for ADC_V2 */ #define ADC_V2_CON1_SOFT_RESET (1u << 2) +#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1) #define ADC_V2_CON2_OSEL (1u << 10) #define ADC_V2_CON2_ESEL (1u << 9) @@ -100,6 +106,7 @@ #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) #define ADC_V2_CON2_ACH_MASK 0xF +#define MAX_ADC_FSD_CHANNELS 16 #define MAX_ADC_V2_CHANNELS 10 #define MAX_ADC_V1_CHANNELS 8 #define MAX_EXYNOS3250_ADC_CHANNELS 2 @@ -484,6 +491,43 @@ static const struct exynos_adc_data exynos7_adc_data = { .start_conv = exynos_adc_v2_start_conv, }; +static void exynos_adc_fsd_init_hw(struct exynos_adc *info) +{ + u32 con2; + + writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs)); + + writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info->regs)); + + con2 = ADC_V2_CON2_C_TIME(6); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); +} + +static void exynos_adc_fsd_exit_hw(struct exynos_adc *info) +{ + u32 con2; + + con2 = readl(ADC_V2_CON2(info->regs)); + con2 &= ~ADC_V2_CON2_C_TIME(7); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Disable interrupts */ + writel(0, ADC_V2_INT_EN(info->regs)); +} + +static const struct exynos_adc_data fsd_hw_adc_data = { + .num_channels = MAX_ADC_FSD_CHANNELS, + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ + + .init_hw = exynos_adc_fsd_init_hw, + .exit_hw = exynos_adc_fsd_exit_hw, + .clear_irq = exynos_adc_v2_clear_irq, + .start_conv = exynos_adc_v2_start_conv, +}; + static const struct of_device_id exynos_adc_match[] = { { .compatible = "samsung,s3c2410-adc", @@ -518,6 +562,9 @@ static const struct of_device_id exynos_adc_match[] = { }, { .compatible = "samsung,exynos7-adc", .data = &exynos7_adc_data, + }, { + .compatible = "samsung,exynos-adc-fsd-hw", + .data = &fsd_hw_adc_data, }, {}, }; @@ -626,6 +673,8 @@ static irqreturn_t exynos_adc_isr(int irq, void *dev_id) info->ts_x = readl(ADC_V1_DATX(info->regs)); info->ts_y = readl(ADC_V1_DATY(info->regs)); writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs)); + } else if (of_device_is_compatible(info->dev->of_node, "samsung,exynos-adc-fsd-hw")) { + info->value = readl(ADC_FSD_DAT(info->regs)) & mask; } else { info->value = readl(ADC_V1_DATX(info->regs)) & mask; } @@ -719,6 +768,12 @@ static const struct iio_chan_spec exynos_adc_iio_channels[] = { ADC_CHANNEL(7, "adc7"), ADC_CHANNEL(8, "adc8"), ADC_CHANNEL(9, "adc9"), + ADC_CHANNEL(10, "adc10"), + ADC_CHANNEL(11, "adc11"), + ADC_CHANNEL(12, "adc12"), + ADC_CHANNEL(13, "adc13"), + ADC_CHANNEL(14, "adc14"), + ADC_CHANNEL(15, "adc15"), }; static int exynos_adc_remove_devices(struct device *dev, void *c) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-22 9:54 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220520145757epcas5p145e5546f71fe836ad6d6a5f1b40459ec@epcas5p1.samsung.com> 2022-05-20 14:58 ` [PATCH v2 0/3] Adds support of ADC for FSD SoC Tamseel Shams 2022-05-20 14:58 ` Tamseel Shams [not found] ` <CGME20220520145759epcas5p240de0ce6d1a1bfea6c8a6bfb61c5d27d@epcas5p2.samsung.com> 2022-05-20 14:58 ` [PATCH v2 1/3] dt-bindings: iio: adc: Add FSD-HW variant Tamseel Shams 2022-05-20 14:58 ` Tamseel Shams 2022-05-23 10:16 ` Krzysztof Kozlowski 2022-05-23 10:16 ` Krzysztof Kozlowski 2022-05-31 8:27 ` m.shams 2022-05-31 8:27 ` m.shams [not found] ` <CGME20220520145802epcas5p2153cb572493e3bccd702e0ecce1171fb@epcas5p2.samsung.com> 2022-05-20 14:58 ` Tamseel Shams [this message] 2022-05-20 14:58 ` [PATCH v2 2/3] iio: adc: exynos-adc: Add support for ADC FSD-HW controller Tamseel Shams 2022-05-22 11:25 ` Jonathan Cameron 2022-05-22 11:25 ` Jonathan Cameron 2022-05-31 8:42 ` m.shams 2022-05-31 8:42 ` m.shams 2022-06-03 15:10 ` Jonathan Cameron 2022-06-03 15:10 ` Jonathan Cameron 2022-05-23 10:20 ` Krzysztof Kozlowski 2022-05-23 10:20 ` Krzysztof Kozlowski 2022-05-31 8:29 ` m.shams 2022-05-31 8:29 ` m.shams [not found] ` <CGME20220520145804epcas5p2925e66d30b18378fc62c92999ec269f7@epcas5p2.samsung.com> 2022-05-20 14:58 ` [PATCH v2 3/3] arm64: dts: fsd: Add ADC device tree node Tamseel Shams 2022-05-20 14:58 ` Tamseel Shams 2022-05-23 10:22 ` Krzysztof Kozlowski 2022-05-23 10:22 ` Krzysztof Kozlowski 2022-05-31 8:32 ` m.shams 2022-05-31 8:32 ` m.shams
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220520145820.67667-3-m.shams@samsung.com \ --to=m.shams@samsung.com \ --cc=alim.akhtar@samsung.com \ --cc=devicetree@vger.kernel.org \ --cc=geert@linux-m68k.org \ --cc=jic23@kernel.org \ --cc=krzk+dt@kernel.org \ --cc=lars@metafoo.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-fsd@tesla.com \ --cc=linux-iio@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=paul@crapouillou.net \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.