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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Steven Rostedt <rostedt@goodmis.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Date: Thu,  1 Sep 2022 01:59:18 +0800	[thread overview]
Message-ID: <20220831175920.2806-4-jszhang@kernel.org> (raw)
In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org>

Move POSIX CPU timer expiry and signal delivery into task context to
allow PREEMPT_RT setups to coexist with KVM.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 79e52441e18b..7a8134fd7ec9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -104,6 +104,7 @@ config RISCV
 	select HAVE_PERF_EVENTS
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
+	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_FUNCTION_ARG_ACCESS_API
 	select HAVE_STACKPROTECTOR
-- 
2.34.1


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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Steven Rostedt <rostedt@goodmis.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Date: Thu,  1 Sep 2022 01:59:18 +0800	[thread overview]
Message-ID: <20220831175920.2806-4-jszhang@kernel.org> (raw)
In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org>

Move POSIX CPU timer expiry and signal delivery into task context to
allow PREEMPT_RT setups to coexist with KVM.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 79e52441e18b..7a8134fd7ec9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -104,6 +104,7 @@ config RISCV
 	select HAVE_PERF_EVENTS
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
+	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_FUNCTION_ARG_ACCESS_API
 	select HAVE_STACKPROTECTOR
-- 
2.34.1


  parent reply	other threads:[~2022-08-31 18:09 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-31 17:59 [PATCH v2 0/5] riscv: add PREEMPT_RT support Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang
2022-08-31 17:59   ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang
2022-08-31 17:59   ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang [this message]
2022-08-31 17:59   ` [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 4/5] riscv: add lazy preempt support Jisheng Zhang
2022-08-31 17:59   ` Jisheng Zhang
2022-09-04 15:16   ` Guo Ren
2022-09-04 15:16     ` Guo Ren
2022-09-05  6:34     ` Sebastian Andrzej Siewior
2022-09-05  6:34       ` Sebastian Andrzej Siewior
2022-09-05  8:33       ` Guo Ren
2022-09-05  8:33         ` Guo Ren
2022-09-05  8:46         ` Sebastian Andrzej Siewior
2022-09-05  8:46           ` Sebastian Andrzej Siewior
2022-09-06  1:46           ` Guo Ren
2022-09-06  1:46             ` Guo Ren
2022-09-05 12:58         ` Jisheng Zhang
2022-09-05 12:58           ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 5/5] riscv: Allow to enable RT Jisheng Zhang
2022-08-31 17:59   ` Jisheng Zhang
2022-09-01  7:04 ` [PATCH v2 0/5] riscv: add PREEMPT_RT support Sebastian Andrzej Siewior
2022-09-01  7:04   ` Sebastian Andrzej Siewior
2022-09-01 13:44   ` Jisheng Zhang
2022-09-01 13:44     ` Jisheng Zhang
2022-09-01 16:41 ` Conor.Dooley
2022-09-01 16:41   ` Conor.Dooley
2022-09-02 13:09   ` Jisheng Zhang
2022-09-02 13:09     ` Jisheng Zhang
2022-09-02 13:29     ` Conor.Dooley
2022-09-02 13:29       ` Conor.Dooley
2022-11-11 14:32       ` Sebastian Andrzej Siewior
2022-11-11 14:32         ` Sebastian Andrzej Siewior
2022-11-11 14:34         ` Conor.Dooley
2022-11-11 14:34           ` Conor.Dooley
2022-11-12 21:40           ` Conor.Dooley
2022-11-12 21:40             ` Conor.Dooley
2023-03-14 13:07 ` Schaffner, Tobias
2023-03-14 13:07   ` Schaffner, Tobias

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