From: Chris Stillson <stillson@rivosinc.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Vincent Chen <vincent.chen@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Oleg Nesterov <oleg@redhat.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Guo Ren <guoren@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>,
Chris Stillson <stillson@rivosinc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Qinglin Pan <panqinglin2020@iscas.ac.cn>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
Arnd Bergmann <arnd@arndb.de>, Heiko Stuebner <heiko@sntech.de>,
Jisheng Zhang <jszhang@kernel.org>, Dao Lu <daolu@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Knight <nick.knight@sifive.com>,
Han-Kuan Chen <hankuan.chen@sifive.com>,
Changbin Du <changbin.du@intel.com>,
Li Zhengyu <lizhengyu3@huawei.com>,
Ard Biesheuvel <ardb@kernel.org>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Yury Norov <yury.norov@gmail.com>,
Frederic Weisbecker <frederic@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Vitaly Wool <vitaly.wool@konsulko.com>,
Myrtle Shah <gatecat@ds0.me>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
Janosch Frank <frankja@linux.ibm.com>,
Huacai Chen <chenhuacai@kernel.org>,
Alexey Dobriyan <adobriyan@gmail.com>,
Christian Brauner <brauner@kernel.org>,
Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
Eugene Syromiatnikov <esyr@redhat.com>,
Colin Cross <ccross@google.com>,
Peter Collingbourne <pcc@google.com>,
Andrew Morton <akpm@linux-foundation.org>,
Barret Rhoden <brho@google.com>,
Suren Baghdasaryan <surenb@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org
Subject: [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list
Date: Wed, 21 Sep 2022 14:43:57 -0700 [thread overview]
Message-ID: <20220921214439.1491510-15-stillson@rivosinc.com> (raw)
In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com>
From: Vincent Chen <vincent.chen@sifive.com>
Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU
to support V extension.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..b242ed155262 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -35,6 +35,7 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_m ('m' - 'a')
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
+#define RISCV_ISA_EXT_v ('v' - 'a')
/*
* Increse this to higher value as kernel support more ISA extensions.
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Chris Stillson <stillson@rivosinc.com>
Cc: Vincent Chen <vincent.chen@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Oleg Nesterov <oleg@redhat.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Guo Ren <guoren@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>,
Chris Stillson <stillson@rivosinc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Qinglin Pan <panqinglin2020@iscas.ac.cn>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
Arnd Bergmann <arnd@arndb.de>, Heiko Stuebner <heiko@sntech.de>,
Jisheng Zhang <jszhang@kernel.org>, Dao Lu <daolu@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Knight <nick.knight@sifive.com>,
Han-Kuan Chen <hankuan.chen@sifive.com>,
Changbin Du <changbin.du@intel.com>,
Li Zhengyu <lizhengyu3@huawei.com>,
Ard Biesheuvel <ardb@kernel.org>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Yury Norov <yury.norov@gmail.com>,
Frederic Weisbecker <frederic@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Vitaly Wool <vitaly.wool@konsulko.com>,
Myrtle Shah <gatecat@ds0.me>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
Janosch Frank <frankja@linux.ibm.com>,
Huacai Chen <chenhuacai@kernel.org>,
Alexey Dobriyan <adobriyan@gmail.com>,
Christian Brauner <brauner@kernel.org>,
Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
Eugene Syromiatnikov <esyr@redhat.com>,
Colin Cross <ccross@google.com>,
Peter Collingbourne <pcc@google.com>,
Andrew Morton <akpm@linux-foundation.org>,
Barret Rhoden <brho@google.com>,
Suren Baghdasaryan <surenb@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org
Subject: [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list
Date: Wed, 21 Sep 2022 14:43:57 -0700 [thread overview]
Message-ID: <20220921214439.1491510-15-stillson@rivosinc.com> (raw)
In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com>
From: Vincent Chen <vincent.chen@sifive.com>
Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU
to support V extension.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..b242ed155262 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -35,6 +35,7 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_m ('m' - 'a')
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
+#define RISCV_ISA_EXT_v ('v' - 'a')
/*
* Increse this to higher value as kernel support more ISA extensions.
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Chris Stillson <stillson@rivosinc.com>
Cc: Vincent Chen <vincent.chen@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Oleg Nesterov <oleg@redhat.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Guo Ren <guoren@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>,
Chris Stillson <stillson@rivosinc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Qinglin Pan <panqinglin2020@iscas.ac.cn>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
Arnd Bergmann <arnd@arndb.de>, Heiko Stuebner <heiko@sntech.de>,
Jisheng Zhang <jszhang@kernel.org>, Dao Lu <daolu@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Knight <nick.knight@sifive.com>,
Han-Kuan Chen <hankuan.chen@sifive.com>,
Changbin Du <changbin.du@intel.com>,
Li Zhengyu <lizhengyu3@huawei.com>,
Ard Biesheuvel <ardb@kernel.org>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Yury Norov <yury.norov@gmail.com>,
Frederic Weisbecker <frederic@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Vitaly Wool <vitaly.wool@konsulko.com>,
Myrtle Shah <gatecat@ds0.me>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
Janosch Frank <frankja@linux.ibm.com>,
Huacai Chen <chenhuacai@kernel.org>,
Alexey Dobriyan <adobriyan@gmail.com>,
Christian Brauner <brauner@kernel.org>,
Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
Eugene Syromiatnikov <esyr@redhat.com>,
Colin Cross <ccross@google.com>,
Peter Collingbourne <pcc@google.com>,
Andrew Morton <akpm@linux-foundation.org>,
Barret Rhoden <brho@google.com>,
Suren Baghdasaryan <surenb@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org
Subject: [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list
Date: Wed, 21 Sep 2022 14:43:57 -0700 [thread overview]
Message-ID: <20220921214439.1491510-15-stillson@rivosinc.com> (raw)
In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com>
From: Vincent Chen <vincent.chen@sifive.com>
Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU
to support V extension.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..b242ed155262 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -35,6 +35,7 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_m ('m' - 'a')
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
+#define RISCV_ISA_EXT_v ('v' - 'a')
/*
* Increse this to higher value as kernel support more ISA extensions.
--
2.25.1
next prev parent reply other threads:[~2022-09-21 21:55 UTC|newest]
Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 21:43 [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
[not found] ` <4b6e20fb-d013-0a09-0b74-b6c46e045af3@rivosinc.com>
[not found] ` <CAJF2gTSPoKu_owEb6+MLhAgK5nz2FTRDkTn4qfXF4KyA-XTwvw@mail.gmail.com>
[not found] ` <CAJF2gTT_z96V3kjPtr9hpTq8XRn0x=91wFNPYFFdetAA2u-01Q@mail.gmail.com>
2022-11-04 9:13 ` Conor.Dooley
2022-11-04 18:04 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2023-01-23 11:24 ` Heiko Stübner
2023-01-23 11:24 ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 04/17] riscv: Add vector feature to compile Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-07 17:21 ` Björn Töpel
2022-11-07 17:21 ` Björn Töpel
2022-11-08 0:04 ` Vineet Gupta
2022-11-08 0:04 ` Vineet Gupta
2022-11-08 7:56 ` Conor Dooley
2022-11-08 7:56 ` Conor Dooley
2022-11-08 17:17 ` Vineet Gupta
2022-11-08 17:17 ` Vineet Gupta
2022-11-08 17:22 ` Conor Dooley
2022-11-08 17:22 ` Conor Dooley
2022-11-13 16:16 ` Conor.Dooley
2022-11-13 16:16 ` Conor.Dooley
2022-11-15 17:38 ` Vineet Gupta
2022-11-15 17:38 ` Vineet Gupta
2022-11-15 22:17 ` Conor Dooley
2022-11-15 22:17 ` Conor Dooley
2022-12-15 0:40 ` Atish Patra
2022-12-15 0:40 ` Atish Patra
2022-09-21 21:43 ` [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-22 4:23 ` Samuel Holland
2022-09-22 4:23 ` Samuel Holland
2022-09-23 16:27 ` Chris Stillson
2022-09-23 16:27 ` Chris Stillson
2022-09-24 18:01 ` Conor Dooley
2022-09-24 18:01 ` Conor Dooley
2022-11-04 4:10 ` Vineet Gupta
2022-11-04 4:10 ` Vineet Gupta
2022-11-04 4:33 ` Vineet Gupta
2022-11-04 4:33 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 06/17] riscv: Reset vector register Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-04 5:01 ` Vineet Gupta
2022-11-04 5:01 ` Vineet Gupta
2022-11-04 8:45 ` Guo Ren
2022-11-04 8:45 ` Guo Ren
2023-01-20 12:20 ` Heiko Stübner
2023-01-20 12:20 ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-04 5:13 ` Vineet Gupta
2022-11-04 5:13 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 08/17] riscv: Add task switch support for vector Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-04 22:08 ` Vineet Gupta
2022-11-04 22:08 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 09/17] riscv: Add ptrace vector support Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-08 1:38 ` Vineet Gupta
2022-11-08 1:38 ` Vineet Gupta
2022-11-14 20:01 ` Arnd Bergmann
2022-11-14 20:01 ` Arnd Bergmann
2022-09-21 21:43 ` [PATCH v12 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-11-09 1:27 ` Vineet Gupta
2022-11-09 1:27 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson [this message]
2022-09-21 21:43 ` [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 17/17] riscv: prctl to enable vector commands Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-12-09 5:16 ` RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Vineet Gupta
2022-12-09 5:16 ` Vineet Gupta
2022-12-09 6:27 ` Palmer Dabbelt
2022-12-09 6:27 ` Palmer Dabbelt
2022-12-09 7:42 ` Andrew Waterman
2022-12-09 7:42 ` Andrew Waterman
2022-12-09 10:02 ` Florian Weimer
2022-12-09 10:02 ` Florian Weimer
2022-12-09 12:21 ` Darius Rad
2022-12-09 12:21 ` Darius Rad
2022-12-09 12:32 ` Florian Weimer
2022-12-09 12:32 ` Florian Weimer
2022-12-09 12:42 ` Darius Rad
2022-12-09 12:42 ` Darius Rad
2022-12-09 13:04 ` Florian Weimer
2022-12-09 13:04 ` Florian Weimer
2022-12-09 17:21 ` Palmer Dabbelt
2022-12-09 17:21 ` Palmer Dabbelt
2022-12-09 19:42 ` Vineet Gupta
2022-12-09 19:42 ` Vineet Gupta
2022-12-09 19:58 ` Andrew Waterman
2022-12-09 19:58 ` Andrew Waterman
2022-12-13 16:43 ` Darius Rad
2022-12-13 16:43 ` Darius Rad
2022-12-14 20:07 ` Vineet Gupta
2022-12-14 20:07 ` Vineet Gupta
2022-12-14 23:13 ` Samuel Holland
2022-12-14 23:13 ` Samuel Holland
2022-12-15 2:09 ` Darius Rad
2022-12-15 2:09 ` Darius Rad
2022-12-15 11:48 ` Björn Töpel
2022-12-15 11:48 ` Björn Töpel
2022-12-15 12:28 ` Florian Weimer
2022-12-15 12:28 ` Florian Weimer
2022-12-15 15:33 ` Richard Henderson
2022-12-15 15:33 ` Richard Henderson
2022-12-15 18:57 ` Vineet Gupta
2022-12-15 18:57 ` Vineet Gupta
2022-12-15 18:59 ` Andrew Pinski
2022-12-15 18:59 ` Andrew Pinski
2022-12-15 19:01 ` Andrew Pinski
2022-12-15 19:01 ` Andrew Pinski
2022-12-15 19:56 ` Richard Henderson
2022-12-15 19:56 ` Richard Henderson
2022-12-09 13:58 ` Icenowy Zheng
2022-12-09 13:58 ` Icenowy Zheng
2023-01-23 11:20 ` [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Heiko Stübner
2023-01-23 11:20 ` Heiko Stübner
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