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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 7/7] target/arm: Report FEAT_EVT for TCG '-cpu max'
Date: Fri, 28 Oct 2022 14:40:02 +0100	[thread overview]
Message-ID: <20221028134002.730598-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221028134002.730598-1-peter.maydell@linaro.org>

Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index cfb4b0768b0..bc330cff463 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -25,6 +25,7 @@ the following architecture extensions:
 - FEAT_DotProd (Advanced SIMD dot product instructions)
 - FEAT_DoubleFault (Double Fault Extension)
 - FEAT_ETS (Enhanced Translation Synchronization)
+- FEAT_EVT (Enhanced Virtualization Traps)
 - FEAT_FCMA (Floating-point complex number instructions)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP16 (Half-precision floating-point data processing)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 85e0d1daf1c..3a5df146ac2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1185,6 +1185,7 @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1);      /* FEAT_S2FWB */
     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
     t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2);      /* FEAT_EVT */
     cpu->isar.id_aa64mmfr2 = t;
 
     t = cpu->isar.id_aa64zfr0;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 60ff539fa18..4553d20edd4 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -65,6 +65,7 @@ void aa32_max_features(ARMCPU *cpu)
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_mmfr5;
-- 
2.25.1



  parent reply	other threads:[~2022-10-28 13:44 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-28 13:39 [PATCH 0/7] target/arm: Implement FEAT_EVT Peter Maydell
2022-10-28 13:39 ` [PATCH 1/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB Peter Maydell
2022-10-28 19:29   ` Richard Henderson
2022-10-28 13:39 ` [PATCH 2/7] target/arm: Allow relevant HCR bits to be written for FEAT_EVT Peter Maydell
2022-10-28 19:35   ` Richard Henderson
2022-10-28 13:39 ` [PATCH 3/7] target/arm: Implement HCR_EL2.TTLBIS traps Peter Maydell
2022-10-28 19:39   ` Richard Henderson
2022-10-28 13:39 ` [PATCH 4/7] target/arm: Implement HCR_EL2.TTLBOS traps Peter Maydell
2022-10-28 19:40   ` Richard Henderson
2022-10-28 13:40 ` [PATCH 5/7] target/arm: Implement HCR_EL2.TICAB,TOCU traps Peter Maydell
2022-10-28 19:43   ` Richard Henderson
2022-10-28 13:40 ` [PATCH 6/7] target/arm: Implement HCR_EL2.TID4 traps Peter Maydell
2022-10-28 19:46   ` Richard Henderson
2022-10-28 13:40 ` Peter Maydell [this message]
2022-10-28 19:47   ` [PATCH 7/7] target/arm: Report FEAT_EVT for TCG '-cpu max' Richard Henderson

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