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From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
Date: Mon, 28 Nov 2022 21:44:16 +0530	[thread overview]
Message-ID: <20221128161424.608889-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com>

The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
be done for isa config register.

Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/kvm/vcpu.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 17d5b3f8c2ee..982a3f5e7130 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 		return -EFAULT;
 
-	/* This ONE REG interface is only defined for single letter extensions */
-	if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
-		return -EINVAL;
-
 	switch (reg_num) {
 	case KVM_REG_RISCV_CONFIG_REG(isa):
+		/*
+		 * This ONE REG interface is only defined for
+		 * single letter extensions.
+		 */
+		if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
+			return -EINVAL;
+
 		if (!vcpu->arch.ran_atleast_once) {
 			/* Ignore the enable/disable request for certain extensions */
 			for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
Date: Mon, 28 Nov 2022 21:44:16 +0530	[thread overview]
Message-ID: <20221128161424.608889-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com>

The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
be done for isa config register.

Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/kvm/vcpu.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 17d5b3f8c2ee..982a3f5e7130 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 		return -EFAULT;
 
-	/* This ONE REG interface is only defined for single letter extensions */
-	if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
-		return -EINVAL;
-
 	switch (reg_num) {
 	case KVM_REG_RISCV_CONFIG_REG(isa):
+		/*
+		 * This ONE REG interface is only defined for
+		 * single letter extensions.
+		 */
+		if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
+			return -EINVAL;
+
 		if (!vcpu->arch.ran_atleast_once) {
 			/* Ignore the enable/disable request for certain extensions */
 			for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
-- 
2.34.1


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  reply	other threads:[~2022-11-28 16:14 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-28 16:14 [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 16:14 ` Anup Patel [this message]
2022-11-28 16:14   ` [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() Anup Patel
2022-11-28 21:03   ` Atish Patra
2022-11-28 21:03     ` Atish Patra
2022-11-28 16:14 ` [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:04   ` Atish Patra
2022-11-28 21:04     ` Atish Patra
2022-11-29  5:20   ` Andrew Jones
2022-11-29  5:20     ` Andrew Jones
2022-11-28 16:14 ` [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:04   ` Atish Patra
2022-11-28 21:04     ` Atish Patra
2022-11-28 16:14 ` [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:04   ` Atish Patra
2022-11-28 21:04     ` Atish Patra
2022-11-28 16:14 ` [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:06   ` Atish Patra
2022-11-28 21:06     ` Atish Patra
2022-11-29  5:21   ` Andrew Jones
2022-11-29  5:21     ` Andrew Jones
2022-11-28 16:14 ` [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:07   ` Atish Patra
2022-11-28 21:07     ` Atish Patra
2022-12-09  4:33     ` Palmer Dabbelt
2022-12-09  4:33       ` Palmer Dabbelt
2022-11-29  5:21   ` Andrew Jones
2022-11-29  5:21     ` Andrew Jones
2022-12-02 17:53   ` Palmer Dabbelt
2022-12-02 17:53     ` Palmer Dabbelt
2022-11-28 16:14 ` [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:08   ` Atish Patra
2022-11-28 21:08     ` Atish Patra
2022-11-29  5:22   ` Andrew Jones
2022-11-29  5:22     ` Andrew Jones
2022-11-28 16:14 ` [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-28 21:09   ` Atish Patra
2022-11-28 21:09     ` Atish Patra
2022-11-29  5:46   ` Andrew Jones
2022-11-29  5:46     ` Andrew Jones
2022-12-03 12:18     ` Anup Patel
2022-12-03 12:18       ` Anup Patel
2022-11-28 16:14 ` [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions Anup Patel
2022-11-28 16:14   ` Anup Patel
2022-11-29  6:09   ` Andrew Jones
2022-11-29  6:09     ` Andrew Jones
2022-12-03 12:39 ` [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-12-03 12:39   ` Anup Patel

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